board.c 6.0 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-06 SummerGift first version
  9. * 2019-04-09 WillianChan add stm32f469-st-disco bsp
  10. * 2020-06-20 thread-liu add stm32mp157-dk1 bsp
  11. */
  12. #include "board.h"
  13. void PeriphCommonClock_Config(void);
  14. /**
  15. * @brief System Clock Configuration
  16. * @retval None
  17. */
  18. void SystemClock_Config(void)
  19. {
  20. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  21. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  22. /**Configure LSE Drive Capability
  23. */
  24. HAL_PWR_EnableBkUpAccess();
  25. __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
  26. /**Initializes the CPU, AHB and APB busses clocks
  27. */
  28. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
  29. |RCC_OSCILLATORTYPE_LSE;
  30. RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG;
  31. RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  32. RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  33. RCC_OscInitStruct.HSICalibrationValue = 16;
  34. RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
  35. /**PLL1 Config
  36. */
  37. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  38. RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
  39. RCC_OscInitStruct.PLL.PLLM = 3;
  40. RCC_OscInitStruct.PLL.PLLN = 81;
  41. RCC_OscInitStruct.PLL.PLLP = 1;
  42. RCC_OscInitStruct.PLL.PLLQ = 1;
  43. RCC_OscInitStruct.PLL.PLLR = 1;
  44. RCC_OscInitStruct.PLL.PLLFRACV = 0x800;
  45. RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
  46. RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
  47. RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
  48. /**PLL2 Config
  49. */
  50. RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
  51. RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
  52. RCC_OscInitStruct.PLL2.PLLM = 3;
  53. RCC_OscInitStruct.PLL2.PLLN = 66;
  54. RCC_OscInitStruct.PLL2.PLLP = 2;
  55. RCC_OscInitStruct.PLL2.PLLQ = 1;
  56. RCC_OscInitStruct.PLL2.PLLR = 1;
  57. RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400;
  58. RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
  59. RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
  60. RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
  61. /**PLL3 Config
  62. */
  63. RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
  64. RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
  65. RCC_OscInitStruct.PLL3.PLLM = 2;
  66. RCC_OscInitStruct.PLL3.PLLN = 34;
  67. RCC_OscInitStruct.PLL3.PLLP = 2;
  68. RCC_OscInitStruct.PLL3.PLLQ = 17;
  69. RCC_OscInitStruct.PLL3.PLLR = 37;
  70. RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
  71. RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04;
  72. RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
  73. RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
  74. RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
  75. /**PLL4 Config
  76. */
  77. RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
  78. RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
  79. RCC_OscInitStruct.PLL4.PLLM = 4;
  80. RCC_OscInitStruct.PLL4.PLLN = 99;
  81. RCC_OscInitStruct.PLL4.PLLP = 6;
  82. RCC_OscInitStruct.PLL4.PLLQ = 8;
  83. RCC_OscInitStruct.PLL4.PLLR = 8;
  84. RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0;
  85. RCC_OscInitStruct.PLL4.PLLFRACV = 0;
  86. RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
  87. RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
  88. RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
  89. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  90. {
  91. Error_Handler();
  92. }
  93. /**RCC Clock Config
  94. */
  95. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK
  96. |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
  97. |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4
  98. |RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU;
  99. RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
  100. RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2;
  101. RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
  102. RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1;
  103. RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3;
  104. RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1;
  105. RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2;
  106. RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4;
  107. RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
  108. RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
  109. RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
  110. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
  111. {
  112. Error_Handler();
  113. }
  114. /**Set the HSE division factor for RTC clock
  115. */
  116. __HAL_RCC_RTC_HSEDIV(24);
  117. /* Configure the peripherals common clocks */
  118. if(IS_ENGINEERING_BOOT_MODE())
  119. {
  120. PeriphCommonClock_Config();
  121. }
  122. }
  123. /**
  124. * @brief Peripherals Common Clock Configuration
  125. * @retval None
  126. */
  127. void PeriphCommonClock_Config(void) {
  128. RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  129. /** Initializes the common periph clock
  130. */
  131. PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
  132. PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE;
  133. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
  134. Error_Handler();
  135. }
  136. }
  137. extern void rt_hw_systick_init(void);
  138. extern int rt_hw_usart_init(void);
  139. void rt_hw_board_init()
  140. {
  141. /* HAL_Init() function is called at the beginning of the program */
  142. HAL_Init();
  143. /* enable interrupt */
  144. __set_PRIMASK(0);
  145. /* Configure the system clock */
  146. if (IS_ENGINEERING_BOOT_MODE()) {
  147. /* Configure the system clock */
  148. SystemClock_Config();
  149. }
  150. /* disable interrupt */
  151. __set_PRIMASK(1);
  152. rt_hw_systick_init();
  153. /* Heap initialization */
  154. #if defined(RT_USING_HEAP)
  155. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  156. #endif
  157. /* Pin driver initialization is open by default */
  158. #ifdef RT_USING_PIN
  159. rt_hw_pin_init();
  160. #endif
  161. /* USART driver initialization is open by default */
  162. #ifdef RT_USING_SERIAL
  163. rt_hw_usart_init();
  164. #endif
  165. /* Set the shell console output device */
  166. #ifdef RT_USING_CONSOLE
  167. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  168. #endif
  169. /* Board underlying hardware initialization */
  170. #ifdef RT_USING_COMPONENTS_INIT
  171. rt_components_board_init();
  172. #endif
  173. }