xpseudo_asm_gcc.h 7.3 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a copy
  6. * of this software and associated documentation files (the "Software"), to deal
  7. * in the Software without restriction, including without limitation the rights
  8. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  9. * copies of the Software, and to permit persons to whom the Software is
  10. * furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  21. * THE SOFTWARE.
  22. *
  23. *
  24. *
  25. ******************************************************************************/
  26. /*****************************************************************************/
  27. /**
  28. *
  29. * @file xpseudo_asm_gcc.h
  30. *
  31. * This header file contains macros for using inline assembler code. It is
  32. * written specifically for the GNU compiler.
  33. *
  34. * <pre>
  35. * MODIFICATION HISTORY:
  36. *
  37. * Ver Who Date Changes
  38. * ----- -------- -------- -----------------------------------------------
  39. * 5.00 pkp 05/21/14 First release
  40. * 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
  41. * </pre>
  42. *
  43. ******************************************************************************/
  44. #ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
  45. #define XPSEUDO_ASM_GCC_H /* by using protection macros */
  46. /***************************** Include Files ********************************/
  47. #include <rtdef.h>
  48. #ifdef __cplusplus
  49. extern "C" {
  50. #endif /* __cplusplus */
  51. /************************** Constant Definitions ****************************/
  52. /**************************** Type Definitions ******************************/
  53. /***************** Macros (Inline Functions) Definitions ********************/
  54. /* necessary for pre-processor */
  55. #define stringify(s) tostring(s)
  56. #define tostring(s) #s
  57. #if defined (__aarch64__)
  58. /* pseudo assembler instructions */
  59. #define mfcpsr() ({rt_uint32_t rval = 0U; \
  60. asm volatile("mrs %0, DAIF" : "=r" (rval));\
  61. rval;\
  62. })
  63. #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
  64. #define cpsiei() //__asm__ __volatile__("cpsie i\n")
  65. #define cpsidi() //__asm__ __volatile__("cpsid i\n")
  66. #define cpsief() //__asm__ __volatile__("cpsie f\n")
  67. #define cpsidf() //__asm__ __volatile__("cpsid f\n")
  68. #define mtgpr(rn, v) /*__asm__ __volatile__(\
  69. "mov r" stringify(rn) ", %0 \n"\
  70. : : "r" (v)\
  71. )*/
  72. #define mfgpr(rn) /*({rt_uint32_t rval; \
  73. __asm__ __volatile__(\
  74. "mov %0,r" stringify(rn) "\n"\
  75. : "=r" (rval)\
  76. );\
  77. rval;\
  78. })*/
  79. /* memory synchronization operations */
  80. /* Instruction Synchronization Barrier */
  81. #define isb() __asm__ __volatile__ ("isb sy")
  82. /* Data Synchronization Barrier */
  83. #define dsb() __asm__ __volatile__("dsb sy")
  84. /* Data Memory Barrier */
  85. #define dmb() __asm__ __volatile__("dmb sy")
  86. /* Memory Operations */
  87. #define ldr(adr) ({u64 rval; \
  88. __asm__ __volatile__(\
  89. "ldr %0,[%1]"\
  90. : "=r" (rval) : "r" (adr)\
  91. );\
  92. rval;\
  93. })
  94. #define mfelrel3() ({u64 rval = 0U; \
  95. asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
  96. rval;\
  97. })
  98. #define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
  99. #else
  100. /* pseudo assembler instructions */
  101. #define mfcpsr() ({rt_uint32_t rval = 0U; \
  102. __asm__ __volatile__(\
  103. "mrs %0, cpsr\n"\
  104. : "=r" (rval)\
  105. );\
  106. rval;\
  107. })
  108. #define mtcpsr(v) __asm__ __volatile__(\
  109. "msr cpsr,%0\n"\
  110. : : "r" (v)\
  111. )
  112. #define cpsiei() __asm__ __volatile__("cpsie i\n")
  113. #define cpsidi() __asm__ __volatile__("cpsid i\n")
  114. #define cpsief() __asm__ __volatile__("cpsie f\n")
  115. #define cpsidf() __asm__ __volatile__("cpsid f\n")
  116. #define mtgpr(rn, v) __asm__ __volatile__(\
  117. "mov r" stringify(rn) ", %0 \n"\
  118. : : "r" (v)\
  119. )
  120. #define mfgpr(rn) ({rt_uint32_t rval; \
  121. __asm__ __volatile__(\
  122. "mov %0,r" stringify(rn) "\n"\
  123. : "=r" (rval)\
  124. );\
  125. rval;\
  126. })
  127. /* memory synchronization operations */
  128. /* Instruction Synchronization Barrier */
  129. #define isb() __asm__ __volatile__ ("isb" : : : "memory")
  130. /* Data Synchronization Barrier */
  131. #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
  132. /* Data Memory Barrier */
  133. #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
  134. /* Memory Operations */
  135. #define ldr(adr) ({rt_uint32_t rval; \
  136. __asm__ __volatile__(\
  137. "ldr %0,[%1]"\
  138. : "=r" (rval) : "r" (adr)\
  139. );\
  140. rval;\
  141. })
  142. #endif
  143. #define ldrb(adr) ({rt_uint8_t rval; \
  144. __asm__ __volatile__(\
  145. "ldrb %0,[%1]"\
  146. : "=r" (rval) : "r" (adr)\
  147. );\
  148. rval;\
  149. })
  150. #define str(adr, val) __asm__ __volatile__(\
  151. "str %0,[%1]\n"\
  152. : : "r" (val), "r" (adr)\
  153. )
  154. #define strb(adr, val) __asm__ __volatile__(\
  155. "strb %0,[%1]\n"\
  156. : : "r" (val), "r" (adr)\
  157. )
  158. /* Count leading zeroes (clz) */
  159. #define clz(arg) ({rt_uint8_t rval; \
  160. __asm__ __volatile__(\
  161. "clz %0,%1"\
  162. : "=r" (rval) : "r" (arg)\
  163. );\
  164. rval;\
  165. })
  166. #if defined (__aarch64__)
  167. #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
  168. #define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
  169. #define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
  170. #define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
  171. #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
  172. /* CP15 operations */
  173. #define mfcp(reg) ({u64 rval = 0U;\
  174. __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
  175. rval;\
  176. })
  177. #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
  178. #else
  179. /* CP15 operations */
  180. #define mtcp(rn, v) __asm__ __volatile__(\
  181. "mcr " rn "\n"\
  182. : : "r" (v)\
  183. );
  184. #define mfcp(rn) ({rt_uint32_t rval = 0U; \
  185. __asm__ __volatile__(\
  186. "mrc " rn "\n"\
  187. : "=r" (rval)\
  188. );\
  189. rval;\
  190. })
  191. #endif
  192. /************************** Variable Definitions ****************************/
  193. /************************** Function Prototypes *****************************/
  194. #ifdef __cplusplus
  195. }
  196. #endif /* __cplusplus */
  197. #endif /* XPSEUDO_ASM_GCC_H */