mips_mmu.h 2.4 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-07-26 lizhirui the first version
  9. */
  10. #ifndef __MIPS_MMU_H__
  11. #define __MIPS_MMU_H__
  12. typedef enum cpu_mode_t
  13. {
  14. CPU_MODE_KERNEL = 0x00,
  15. CPU_MODE_SUPERVISOR = 0x01,
  16. CPU_MODE_USER = 0x02
  17. }cpu_mode_t;
  18. typedef enum page_mask_enum_t
  19. {
  20. PAGE_MASK_4KB = 0x00,
  21. PAGE_MASK_16KB = 0x03,
  22. PAGE_MASK_64KB = 0x0F,
  23. PAGE_MASK_256KB = 0x3F,
  24. PAGE_MASK_1MB = 0xFF,
  25. PAGE_MASK_4MB = 0x3FF,
  26. PAGE_MASK_16MB = 0xFFF,
  27. PAGE_MASK_64MB = 0x3FFF,
  28. PAGE_MASK_256MB = 0xFFFF,
  29. PAGE_MASK_1GB = 0x3FFFF
  30. }page_mask_enum_t;
  31. typedef struct page_mask_t
  32. {
  33. uint64_t : 11;
  34. uint64_t : 2;
  35. uint64_t mask : 18;
  36. uint64_t : 33;
  37. }page_mask_t;
  38. typedef struct entry_lo_t
  39. {
  40. uint64_t g : 1;
  41. uint64_t v : 1;
  42. uint64_t d : 1;
  43. uint64_t c : 3;
  44. uint64_t pfn : 24;
  45. uint64_t pfnx : 3;
  46. uint64_t : 29;
  47. uint64_t xi : 1;
  48. uint64_t ri : 1;
  49. }entry_lo_t;
  50. typedef struct entry_hi_t
  51. {
  52. uint64_t asid : 8;
  53. uint64_t : 5;
  54. uint64_t vpn2 : 27;
  55. uint64_t : 22;
  56. uint64_t r : 2;
  57. }entry_hi_t;
  58. typedef struct tlb_item_t
  59. {
  60. entry_lo_t entry_lo[2];
  61. entry_hi_t entry_hi;
  62. page_mask_t page_mask;
  63. }tlb_item_t;
  64. #define read_c0_diag() __read_32bit_c0_register($22, 0)
  65. #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
  66. #define read_c0_badvaddr() __read_64bit_c0_register($8, 0)
  67. #define read_c0_random() __read_32bit_c0_register($1, 0)
  68. #define reg_type_convert(variable,new_type) *((new_type *)(&variable))
  69. #define lowbit(x) ((x) & (-(x)))
  70. void mmu_init();
  71. void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
  72. cpu_mode_t mmu_get_cpu_mode();
  73. void mmu_clear_tlb();
  74. void mmu_clear_itlb();
  75. uint32_t mmu_get_max_tlb_index();
  76. void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
  77. void mmu_tlb_write_random(tlb_item_t *tlb_item);
  78. void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
  79. uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
  80. void mmu_tlb_item_init(tlb_item_t *tlb_item);
  81. void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
  82. uint32_t mmu_tlb_get_random();
  83. uint32_t mmu_tlb_get_index();
  84. void mmu_tlb_set_index(uint32_t index);
  85. uint32_t mmu_tlb_is_matched();
  86. uint64_t mmu_tlb_get_bad_vaddr();
  87. void tlb_dump();
  88. #endif