startup_gcc.S 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139
  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018/10/01 Bernard The first version
  9. * 2018/12/27 Jesven Add SMP support
  10. */
  11. #define MSTATUS_FS 0x00006000U /* initial state of FPU */
  12. #include <cpuport.h>
  13. .global _start
  14. .section ".start", "ax"
  15. _start:
  16. j 1f
  17. .word 0xdeadbeef
  18. .align 3
  19. .global g_wake_up
  20. g_wake_up:
  21. .dword 1
  22. .dword 0
  23. 1:
  24. csrw mideleg, 0
  25. csrw medeleg, 0
  26. csrw mie, 0
  27. csrw mip, 0
  28. la t0, trap_entry
  29. csrw mtvec, t0
  30. li x1, 0
  31. li x2, 0
  32. li x3, 0
  33. li x4, 0
  34. li x5, 0
  35. li x6, 0
  36. li x7, 0
  37. li x8, 0
  38. li x9, 0
  39. li x10,0
  40. li x11,0
  41. li x12,0
  42. li x13,0
  43. li x14,0
  44. li x15,0
  45. li x16,0
  46. li x17,0
  47. li x18,0
  48. li x19,0
  49. li x20,0
  50. li x21,0
  51. li x22,0
  52. li x23,0
  53. li x24,0
  54. li x25,0
  55. li x26,0
  56. li x27,0
  57. li x28,0
  58. li x29,0
  59. li x30,0
  60. li x31,0
  61. /* set to initial state of FPU and disable interrupt */
  62. li t0, MSTATUS_FS
  63. csrs mstatus, t0
  64. fssr x0
  65. fmv.w.x f0, x0
  66. fmv.w.x f1, x0
  67. fmv.w.x f2, x0
  68. fmv.w.x f3, x0
  69. fmv.w.x f4, x0
  70. fmv.w.x f5, x0
  71. fmv.w.x f6, x0
  72. fmv.w.x f7, x0
  73. fmv.w.x f8, x0
  74. fmv.w.x f9, x0
  75. fmv.w.x f10,x0
  76. fmv.w.x f11,x0
  77. fmv.w.x f12,x0
  78. fmv.w.x f13,x0
  79. fmv.w.x f14,x0
  80. fmv.w.x f15,x0
  81. fmv.w.x f16,x0
  82. fmv.w.x f17,x0
  83. fmv.w.x f18,x0
  84. fmv.w.x f19,x0
  85. fmv.w.x f20,x0
  86. fmv.w.x f21,x0
  87. fmv.w.x f22,x0
  88. fmv.w.x f23,x0
  89. fmv.w.x f24,x0
  90. fmv.w.x f25,x0
  91. fmv.w.x f26,x0
  92. fmv.w.x f27,x0
  93. fmv.w.x f28,x0
  94. fmv.w.x f29,x0
  95. fmv.w.x f30,x0
  96. fmv.w.x f31,x0
  97. .option push
  98. .option norelax
  99. la gp, __global_pointer$
  100. .option pop
  101. /* get cpu id */
  102. csrr a0, mhartid
  103. la sp, __stack_start__
  104. addi t1, a0, 1
  105. li t2, __STACKSIZE__
  106. mul t1, t1, t2
  107. add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
  108. /* other cpu core, jump to cpu entry directly */
  109. bnez a0, secondary_cpu_entry
  110. tail primary_cpu_entry
  111. secondary_cpu_entry:
  112. #ifdef RT_USING_SMP
  113. la a0, secondary_boot_flag
  114. ld a0, 0(a0)
  115. li a1, 0xa55a
  116. beq a0, a1, 1f
  117. #endif
  118. j secondary_cpu_entry
  119. #ifdef RT_USING_SMP
  120. 1:
  121. tail secondary_cpu_c_start
  122. .data
  123. .global secondary_boot_flag
  124. .align 3
  125. secondary_boot_flag:
  126. .dword 0
  127. #endif