HAL_TIMER.h 24 KB

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  1. /***********************************************************************
  2. * Filename : hal_timer.h
  3. * Description : timer driver header file
  4. * Author(s) : Eric
  5. * version : V1.0
  6. * Modify date : 2016-03-24
  7. ***********************************************************************/
  8. #ifndef __HAL_TIMER_H__
  9. #define __HAL_TIMER_H__
  10. #include "ACM32Fxx_HAL.h"
  11. #define IS_TIMER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) \
  12. || ((INSTANCE) == TIM6) \
  13. || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\
  14. | ((INSTANCE) == TIM17) )
  15. /****************** TIM Instances : supporting the break function *************/
  16. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  17. ((INSTANCE) == TIM15) || \
  18. ((INSTANCE) == TIM16) || \
  19. ((INSTANCE) == TIM17))
  20. /************** TIM Instances : supporting Break source selection *************/
  21. #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  22. ((INSTANCE) == TIM15) || \
  23. ((INSTANCE) == TIM16) || \
  24. ((INSTANCE) == TIM17))
  25. /************* TIM Instances : at least 1 capture/compare channel *************/
  26. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  27. ((INSTANCE) == TIM2) || \
  28. ((INSTANCE) == TIM3) || \
  29. ((INSTANCE) == TIM4) || \
  30. ((INSTANCE) == TIM14) || \
  31. ((INSTANCE) == TIM15) || \
  32. ((INSTANCE) == TIM16) || \
  33. ((INSTANCE) == TIM17))
  34. /************ TIM Instances : at least 2 capture/compare channels *************/
  35. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  36. ((INSTANCE) == TIM2) || \
  37. ((INSTANCE) == TIM3) || \
  38. ((INSTANCE) == TIM4) || \
  39. ((INSTANCE) == TIM15))
  40. /************ TIM Instances : at least 3 capture/compare channels *************/
  41. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  42. ((INSTANCE) == TIM2) || \
  43. ((INSTANCE) == TIM3) || \
  44. ((INSTANCE) == TIM4))
  45. /************ TIM Instances : at least 4 capture/compare channels *************/
  46. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  47. ((INSTANCE) == TIM2) || \
  48. ((INSTANCE) == TIM3) || \
  49. ((INSTANCE) == TIM4))
  50. /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
  51. #define IS_TIM_UDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  52. ((INSTANCE) == TIM3) || \
  53. ((INSTANCE) == TIM6) || \
  54. ((INSTANCE) == TIM7) || \
  55. ((INSTANCE) == TIM15) || \
  56. ((INSTANCE) == TIM16) || \
  57. ((INSTANCE) == TIM17))
  58. /******************* TIM Instances : output(s) available **********************/
  59. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  60. ( (((INSTANCE) == TIM1) && \
  61. (((CHANNEL) == TIM_CHANNEL_1) || \
  62. ((CHANNEL) == TIM_CHANNEL_2) || \
  63. ((CHANNEL) == TIM_CHANNEL_3) || \
  64. ((CHANNEL) == TIM_CHANNEL_4) ) ) \
  65. || \
  66. (((INSTANCE) == TIM3) && \
  67. (((CHANNEL) == TIM_CHANNEL_1) || \
  68. ((CHANNEL) == TIM_CHANNEL_2) || \
  69. ((CHANNEL) == TIM_CHANNEL_3) || \
  70. ((CHANNEL) == TIM_CHANNEL_4)) ) \
  71. || \
  72. (((INSTANCE) == TIM14) && \
  73. (((CHANNEL) == TIM_CHANNEL_1)) ) \
  74. || \
  75. (((INSTANCE) == TIM15) && \
  76. (((CHANNEL) == TIM_CHANNEL_1) || \
  77. ((CHANNEL) == TIM_CHANNEL_2)) ) \
  78. || \
  79. (((INSTANCE) == TIM16) && \
  80. (((CHANNEL) == TIM_CHANNEL_1)) ) \
  81. || \
  82. (((INSTANCE) == TIM17) && \
  83. ((CHANNEL) == TIM_CHANNEL_1) ) )
  84. /****************** TIM Instances : supporting complementary output(s) ********/
  85. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  86. ((( (INSTANCE) == TIM1) && \
  87. (((CHANNEL) == TIM_CHANNEL_1) || \
  88. ((CHANNEL) == TIM_CHANNEL_2) || \
  89. ((CHANNEL) == TIM_CHANNEL_3)) ) \
  90. || \
  91. (((INSTANCE) == TIM15) && \
  92. ((CHANNEL) == TIM_CHANNEL_1)) \
  93. || \
  94. (((INSTANCE) == TIM16) && \
  95. ((CHANNEL) == TIM_CHANNEL_1)) \
  96. || \
  97. (((INSTANCE) == TIM17) && \
  98. ((CHANNEL) == TIM_CHANNEL_1) ) )
  99. /****************** TIM Instances : supporting clock division *****************/
  100. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  101. ((INSTANCE) == TIM3) || \
  102. ((INSTANCE) == TIM14) || \
  103. ((INSTANCE) == TIM15) || \
  104. ((INSTANCE) == TIM16) || \
  105. ((INSTANCE) == TIM17))
  106. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  107. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  108. ((INSTANCE) == TIM2) \
  109. ((INSTANCE) == TIM3) \
  110. ((INSTANCE) == TIM4) )
  111. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  112. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  113. ((INSTANCE) == TIM2) \
  114. ((INSTANCE) == TIM3) \
  115. ((INSTANCE) == TIM4) )
  116. /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
  117. #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  118. /****************** TIM Instances : supporting commutation event generation ***/
  119. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  120. ((INSTANCE) == TIM15) || \
  121. ((INSTANCE) == TIM16) || \
  122. ((INSTANCE) == TIM17))
  123. /****************** TIM Instances : supporting encoder interface **************/
  124. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  125. ((INSTANCE) == TIM2) \
  126. ((INSTANCE) == TIM3) \
  127. ((INSTANCE) == TIM4) )
  128. /****************** TIM Instances : supporting Hall sensor interface **********/
  129. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  130. ((INSTANCE) == TIM2) \
  131. ((INSTANCE) == TIM3) \
  132. ((INSTANCE) == TIM4) )
  133. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  134. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  135. ((INSTANCE) == TIM3) || \
  136. ((INSTANCE) == TIM15))
  137. /****************** TIM Instances : supporting repetition counter *************/
  138. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  139. ((INSTANCE) == TIM15) || \
  140. ((INSTANCE) == TIM16) || \
  141. ((INSTANCE) == TIM17))
  142. #define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
  143. #define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
  144. #define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__))
  145. #define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__))
  146. #define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__))
  147. #define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__))
  148. #define TIM_CR2_CCPC_Pos (0U)
  149. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
  150. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
  151. #define TIM_CR2_CCUS_Pos (2U)
  152. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
  153. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
  154. #define TIM_CR2_CCDS_Pos (3U)
  155. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
  156. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
  157. #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
  158. #define TIM_COMMUTATION_SOFTWARE 0x00000000U
  159. #define TIM_IT_UPDATE BIT0
  160. #define TIM_IT_CC1 BIT1
  161. #define TIM_IT_CC2 BIT2
  162. #define TIM_IT_CC3 BIT3
  163. #define TIM_IT_CC4 BIT4
  164. #define TIM_IT_COM BIT5
  165. #define TIM_IT_TRIGGER BIT6
  166. #define TIM_IT_BREAK BIT7
  167. #define TIM_DMA_UPDATE BIT8
  168. #define TIM_DMA_CC1 BIT9
  169. #define TIM_DMA_CC2 BIT10
  170. #define TIM_DMA_CC3 BIT11
  171. #define TIM_DMA_CC4 BIT12
  172. #define TIM_DMA_COM BIT13
  173. #define TIM_DMA_TRIGGER BIT14
  174. #define TIM_DMA_BREAK BIT15
  175. #define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */
  176. #define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */
  177. #define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */
  178. #define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */
  179. #define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */
  180. #define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */
  181. #define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */
  182. #define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */
  183. #define TIM_ARR_PRELOAD_DISABLE 0
  184. #define TIM_ARR_PRELOAD_ENABLE 1
  185. #define TIM_COUNTERMODE_DIR_INDEX 4
  186. #define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX)
  187. #define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX)
  188. #define TIM_COUNTERMODE_CMS_INDEX 5
  189. #define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX)
  190. #define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX)
  191. #define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX)
  192. #define TIM_CLKCK_DIV_INDEX 8
  193. #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
  194. #define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */
  195. #define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */
  196. #define TIM_TRGO_RESET (0 << 4)
  197. #define TIM_TRGO_ENABLE (1 << 4)
  198. #define TIM_TRGO_UPDATE (2 << 4)
  199. #define TIM_TRGO_CMP_PULSE (3 << 4)
  200. #define TIM_TRGO_OC1REF (4 << 4)
  201. #define TIM_TRGO_OC2REF (5 << 4)
  202. #define TIM_TRGO_OC3REF (6 << 4)
  203. #define TIM_TRGO_OC4REF (7 << 4)
  204. #define TIM_MASTERSLAVEMODE_DISABLE 0
  205. #define TIM_MASTERSLAVEMODE_ENABLE BIT7
  206. #define TIM_SLAVE_MODE_INDEX 0
  207. #define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX)
  208. #define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX)
  209. #define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX)
  210. #define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX)
  211. #define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX)
  212. #define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX)
  213. #define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX)
  214. #define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX)
  215. #define TIM_TRIGGER_SOURCE_INDEX 4
  216. #define TIM_TRIGGER_SOURCE_ITR0 (0U << TIM_TRIGGER_SOURCE_INDEX)
  217. #define TIM_TRIGGER_SOURCE_ITR1 (1U << TIM_TRIGGER_SOURCE_INDEX)
  218. #define TIM_TRIGGER_SOURCE_ITR2 (2U << TIM_TRIGGER_SOURCE_INDEX)
  219. #define TIM_TRIGGER_SOURCE_ITR3 (3U << TIM_TRIGGER_SOURCE_INDEX)
  220. #define TIM_TRIGGER_SOURCE_TI1F_ED (4U << TIM_TRIGGER_SOURCE_INDEX)
  221. #define TIM_TRIGGER_SOURCE_TI1FP1 (5U << TIM_TRIGGER_SOURCE_INDEX)
  222. #define TIM_TRIGGER_SOURCE_TI2FP2 (6U << TIM_TRIGGER_SOURCE_INDEX)
  223. #define TIM_TRIGGER_SOURCE_ETRF (7U << TIM_TRIGGER_SOURCE_INDEX)
  224. #define TIMER_SR_UIF BIT0
  225. #define TIMER_SR_CC1IF BIT1
  226. #define TIMER_SR_CC2IF BIT2
  227. #define TIMER_SR_CC3IF BIT3
  228. #define TIMER_SR_CC4IF BIT4
  229. #define TIMER_SR_COMIF BIT5
  230. #define TIMER_SR_TIF BIT6
  231. #define TIMER_SR_BIF BIT7
  232. #define TIMER_SR_CC1OF BIT9
  233. #define TIMER_SR_CC2OF BIT10
  234. #define TIMER_SR_CC3OF BIT11
  235. #define TIMER_SR_CC4OF BIT12
  236. #define TIMER_INT_EN_UPD BIT0
  237. #define TIMER_INT_EN_CC1 BIT1
  238. #define TIMER_INT_EN_CC2 BIT2
  239. #define TIMER_INT_EN_CC3 BIT3
  240. #define TIMER_INT_EN_CC4 BIT4
  241. #define TIMER_INT_EN_COM BIT5
  242. #define TIMER_INT_EN_TRI BIT6
  243. #define TIMER_INT_EN_BRK BIT7
  244. #define TIMER_DMA_EN_UPD BIT8
  245. #define TIMER_DMA_EN_CC1 BIT9
  246. #define TIMER_DMA_EN_CC2 BIT10
  247. #define TIMER_DMA_EN_CC3 BIT11
  248. #define TIMER_DMA_EN_CC4 BIT12
  249. #define TIMER_DMA_EN_COM BIT13
  250. #define TIMER_DMA_EN_TRI BIT14
  251. #define TIM_CHANNEL_1 0
  252. #define TIM_CHANNEL_2 1
  253. #define TIM_CHANNEL_3 2
  254. #define TIM_CHANNEL_4 3
  255. #define OUTPUT_FAST_MODE_DISABLE 0
  256. #define OUTPUT_FAST_MODE_ENABLE 1
  257. #define OUTPUT_POL_ACTIVE_HIGH 0
  258. #define OUTPUT_POL_ACTIVE_LOW 1
  259. #define OUTPUT_DISABLE_IDLE_STATE 0
  260. #define OUTPUT_ENABLE_IDLE_STATE 1
  261. #define OUTPUT_IDLE_STATE_0 0
  262. #define OUTPUT_IDLE_STATE_1 1
  263. #define OUTPUT_MODE_FROZEN 0
  264. #define OUTPUT_MODE_MATCH_HIGH 1
  265. #define OUTPUT_MODE_MATCH_LOW 2
  266. #define OUTPUT_MODE_MATCH_TOGGLE 3
  267. #define OUTPUT_MODE_FORCE_LOW 4
  268. #define OUTPUT_MODE_FORCE_HIGH 5
  269. #define OUTPUT_MODE_PWM1 6
  270. #define OUTPUT_MODE_PWM2 7
  271. #define TIM_CLOCKSOURCE_INT 0
  272. #define TIM_CLOCKSOURCE_ITR0 1
  273. #define TIM_CLOCKSOURCE_ITR1 2
  274. #define TIM_CLOCKSOURCE_ITR2 3
  275. #define TIM_CLOCKSOURCE_ITR3 4
  276. #define TIM_CLOCKSOURCE_TI1FP1 5
  277. #define TIM_CLOCKSOURCE_TI2FP2 6
  278. #define TIM_CLOCKSOURCE_ETR 7
  279. #define TIM_ETR_POLAIRTY_HIGH 0
  280. #define TIM_ETR_POLAIRTY_LOW (BIT15)
  281. #define TIM_ETR_FILTER_LVL(x) (x << 8) //BIT8-BIT11
  282. #define TIM_ETR_PRESCALER_1 0
  283. #define TIM_ETR_PRESCALER_2 (BIT12)
  284. #define TIM_ETR_PRESCALER_4 (BIT13)
  285. #define TIM_ETR_PRESCALER_8 (BIT12|BIT13)
  286. #define ETR_SELECT_GPIO 0
  287. #define ETR_SELECT_COMP1_OUT BIT14
  288. #define ETR_SELECT_COMP2_OUT BIT15
  289. #define ETR_SELECT_ADC_AWD BIT14|BIT15
  290. #define ETR_SELECT_MASK (BIT14|BIT15)
  291. #define TIM_TI1_FILTER_LVL(x) (x << 4)
  292. #define TIM_TI2_FILTER_LVL(x) (x << 12)
  293. #define TIM_TI3_FILTER_LVL(x) (x << 4)
  294. #define TIM_TI4_FILTER_LVL(x) (x << 12)
  295. #define TIM_IC1_PRESCALER_1 0
  296. #define TIM_IC1_PRESCALER_2 (BIT2)
  297. #define TIM_IC1_PRESCALER_4 (BIT3)
  298. #define TIM_IC1_PRESCALER_8 (BIT2|BIT3)
  299. #define TIM_IC2_PRESCALER_1 0
  300. #define TIM_IC2_PRESCALER_2 (BIT10)
  301. #define TIM_IC2_PRESCALER_4 (BIT11)
  302. #define TIM_IC2_PRESCALER_8 (BIT10|BIT11)
  303. #define TIM_IC3_PRESCALER_1 0
  304. #define TIM_IC3_PRESCALER_2 (BIT2)
  305. #define TIM_IC3_PRESCALER_4 (BIT3)
  306. #define TIM_IC3_PRESCALER_8 (BIT2|BIT3)
  307. #define TIM_IC4_PRESCALER_1 0
  308. #define TIM_IC4_PRESCALER_2 (BIT10)
  309. #define TIM_IC4_PRESCALER_4 (BIT11)
  310. #define TIM_IC4_PRESCALER_8 (BIT10|BIT11)
  311. typedef struct
  312. {
  313. uint32_t ClockSource; //TIMER clock sources
  314. uint32_t ClockPolarity; //TIMER clock polarity
  315. uint32_t ClockPrescaler; //TIMER clock prescaler
  316. uint32_t ClockFilter; //TIMER clock filter
  317. } TIM_ClockConfigTypeDef;
  318. typedef struct
  319. {
  320. uint32_t OCMode; // Specifies the TIM mode.
  321. uint32_t Pulse; // Specifies the pulse value to be loaded into the Capture Compare Register.
  322. uint32_t OCPolarity; // Specifies the output polarity.
  323. uint32_t OCNPolarity; // Specifies the complementary output polarity.
  324. uint32_t OCFastMode; // Specifies the Fast mode state.
  325. uint32_t OCIdleState; // Specifies the TIM Output Compare pin state during Idle state.
  326. uint32_t OCNIdleState; // Specifies the TIM Output Compare complementary pin state during Idle state.
  327. } TIM_OC_InitTypeDef;
  328. #define TIM_SLAVE_CAPTURE_ACTIVE_RISING 0
  329. #define TIM_SLAVE_CAPTURE_ACTIVE_FALLING 1
  330. #define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING 2
  331. #define TIM_ICSELECTION_DIRECTTI 0
  332. #define TIM_ICSELECTION_INDIRECTTI 1
  333. #define TIM_CC1_SLAVE_CAPTURE_POL_RISING (0)
  334. #define TIM_CC1_SLAVE_CAPTURE_POL_FALLING (BIT1)
  335. #define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3)
  336. #define TIM_CC2_SLAVE_CAPTURE_POL_RISING (0)
  337. #define TIM_CC2_SLAVE_CAPTURE_POL_FALLING (BIT5)
  338. #define TIM_CC2_SLAVE_CAPTURE_POL_BOTH (BIT5 | BIT7)
  339. #define TIM_CC3_SLAVE_CAPTURE_POL_RISING (0)
  340. #define TIM_CC3_SLAVE_CAPTURE_POL_FALLING (BIT9)
  341. #define TIM_CC3_SLAVE_CAPTURE_POL_BOTH (BIT9 | BIT11)
  342. #define TIM_CC4_SLAVE_CAPTURE_POL_RISING (0)
  343. #define TIM_CC4_SLAVE_CAPTURE_POL_FALLING (BIT13)
  344. #define TIM_CC4_SLAVE_CAPTURE_POL_BOTH (BIT13 | BIT15)
  345. typedef struct
  346. {
  347. uint32_t SlaveMode; // Slave mode selection
  348. uint32_t InputTrigger; // Input Trigger source
  349. uint32_t TriggerPolarity; // Input Trigger polarity
  350. uint32_t TriggerPrescaler; // input prescaler, only for ETR input
  351. uint32_t TriggerFilter; // Input trigger filter
  352. } TIM_SlaveConfigTypeDef;
  353. typedef struct
  354. {
  355. uint32_t ICPolarity; // Specifies the active edge of the input signal.
  356. uint32_t ICSelection; // Specifies the input
  357. uint32_t ICPrescaler; // Specifies the Input Capture Prescaler.
  358. uint32_t TIFilter; // Specifies the input capture filter.
  359. } TIM_IC_InitTypeDef;
  360. typedef struct
  361. {
  362. uint32_t MasterOutputTrigger; // Trigger output (TRGO) selection
  363. uint32_t MasterSlaveMode; // Master/slave mode selection
  364. } TIM_MasterConfigTypeDef;
  365. #define TIM_DMA_UPDATE_INDEX 0
  366. #define TIM_DMA_CC1_INDEX 1
  367. #define TIM_DMA_CC2_INDEX 2
  368. #define TIM_DMA_CC3_INDEX 3
  369. #define TIM_DMA_CC4_INDEX 4
  370. #define TIM_DMA_COM_INDEX 5
  371. #define TIM_DMA_TRIG_INDEX 6
  372. #define MAX_DMA_REQ_ONE_TIMER 7
  373. typedef struct
  374. {
  375. uint32_t Prescaler; // Specifies the prescaler value used to divide the TIM clock.
  376. uint32_t Period; // Specifies the ARR value
  377. uint32_t ARRPreLoadEn; // Specifies the preload enable or disable
  378. uint32_t RepetitionCounter; // Specifies the repetition counter value
  379. uint32_t CounterMode; // Specifies the counter mode.Up/Down/Center
  380. uint32_t ClockDivision; // Specifies the clock division, used for deadtime or sampling
  381. } TIM_Base_InitTypeDef;
  382. typedef struct
  383. {
  384. TIM_TypeDef *Instance;
  385. TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
  386. DMA_HandleTypeDef *hdma[MAX_DMA_REQ_ONE_TIMER];
  387. }TIM_HandleTypeDef;
  388. /* HAL_TIMER_MSP_Init */
  389. extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim);
  390. /* HAL_TIMER_Slave_Mode_Config */
  391. extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
  392. /* HAL_TIMER_Base_Init */
  393. extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim);
  394. /* HAL_TIMER_Output_Config */
  395. extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel);
  396. /* HAL_TIMER_Base_Start */
  397. extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx);
  398. extern HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx);
  399. /* HAL_TIM_PWM_Output_Start */
  400. extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel);
  401. /* HAL_TIM_PWM_Output_Stop */
  402. extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel);
  403. /* HAL_TIMER_OC_Start */
  404. extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel);
  405. /* HAL_TIMER_OCxN_Start */
  406. extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel);
  407. /* HAL_TIMER_OC_Stop */
  408. extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel);
  409. /* HAL_TIM_Capture_Start */
  410. extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel);
  411. /* HAL_TIM_Capture_Stop */
  412. extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel);
  413. /* HAL_TIMER_Capture_Config */
  414. extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel);
  415. /* HAL_TIMER_Master_Mode_Config */
  416. extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig);
  417. /* HAL_TIMER_SelectClockSource */
  418. extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
  419. /* HAL_TIMER_ReadCapturedValue */
  420. extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
  421. /* HAL_TIMER_Clear_Capture_Flag */
  422. extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel);
  423. #endif