i2c.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-12-04 Haley the first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "am_mcu_apollo.h"
  13. /* I2C0 */
  14. #define AM_I2C0_IOM_INST 0
  15. #define I2C0_GPIO_SCL 5
  16. #define I2C0_GPIO_CFG_SCK AM_HAL_PIN_5_M0SCL
  17. #define I2C0_GPIO_SDA 6
  18. #define I2C0_GPIO_CFG_SDA AM_HAL_PIN_6_M0SDA
  19. /* I2C2 */
  20. #define AM_I2C2_IOM_INST 2
  21. #define I2C2_GPIO_SCL 27
  22. #define I2C2_GPIO_CFG_SCK AM_HAL_PIN_27_M2SCL
  23. #define I2C2_GPIO_SDA 25
  24. #define I2C2_GPIO_CFG_SDA AM_HAL_PIN_25_M2SDA
  25. /* I2C3 */
  26. #define AM_I2C3_IOM_INST 3
  27. #define I2C3_GPIO_SCL 42
  28. #define I2C3_GPIO_CFG_SCK AM_HAL_PIN_42_M3SCL
  29. #define I2C3_GPIO_SDA 43
  30. #define I2C3_GPIO_CFG_SDA AM_HAL_PIN_43_M3SDA
  31. /* I2C4 */
  32. #define AM_I2C4_IOM_INST 4
  33. #define I2C4_GPIO_SCL 39
  34. #define I2C4_GPIO_CFG_SCK AM_HAL_PIN_39_M4SCL
  35. #define I2C4_GPIO_SDA 40
  36. #define I2C4_GPIO_CFG_SDA AM_HAL_PIN_40_M4SDA
  37. static am_hal_iom_config_t g_sIOMConfig =
  38. {
  39. AM_HAL_IOM_I2CMODE, // ui32InterfaceMode
  40. AM_HAL_IOM_100KHZ, // ui32ClockFrequency
  41. 0, // bSPHA
  42. 0, // bSPOL
  43. 4, // ui8WriteThreshold
  44. 60, // ui8ReadThreshold
  45. };
  46. /* AM i2c driver */
  47. struct am_i2c_bus
  48. {
  49. struct rt_i2c_bus_device parent;
  50. rt_uint32_t u32Module;
  51. };
  52. //connect am drv to rt drv.
  53. rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
  54. struct rt_i2c_msg *msgs,
  55. rt_uint32_t num)
  56. {
  57. struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus;
  58. struct rt_i2c_msg *msg;
  59. int i;
  60. rt_uint32_t msg_len = 0;
  61. for (i = 0; i < num; i++)
  62. {
  63. msg = &msgs[i];
  64. if (msg->flags == RT_I2C_RD)
  65. {
  66. am_hal_iom_i2c_read(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
  67. msg_len += msg->len;
  68. }
  69. else if(msg->flags == RT_I2C_WR)
  70. {
  71. am_hal_iom_i2c_write(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
  72. msg_len += (msg->len - 1);
  73. }
  74. }
  75. return msg_len;
  76. }
  77. rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus,
  78. rt_uint32_t cmd,
  79. rt_uint32_t arg)
  80. {
  81. struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus;
  82. //rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
  83. RT_ASSERT(bus != RT_NULL);
  84. am_i2c_bus = (struct am_i2c_bus *)bus->parent.user_data;
  85. RT_ASSERT(am_i2c_bus != RT_NULL);
  86. switch (cmd)
  87. {
  88. /* I2C config */
  89. case RT_DEVICE_CTRL_CONFIG :
  90. break;
  91. }
  92. return RT_EOK;
  93. }
  94. static const struct rt_i2c_bus_device_ops am_i2c_ops =
  95. {
  96. rt_i2c_master_xfer,
  97. RT_NULL,
  98. rt_i2c_bus_control
  99. };
  100. #ifdef RT_USING_I2C0
  101. static struct am_i2c_bus am_i2c_bus_0 =
  102. {
  103. {0},
  104. AM_I2C0_IOM_INST
  105. };
  106. #endif
  107. #ifdef RT_USING_I2C1
  108. static struct am_i2c_bus am_i2c_bus_1 =
  109. {
  110. {1},
  111. AM_I2C1_IOM_INST
  112. };
  113. #endif
  114. #ifdef RT_USING_I2C2
  115. static struct am_i2c_bus am_i2c_bus_2 =
  116. {
  117. {2},
  118. AM_I2C2_IOM_INST
  119. };
  120. #endif
  121. #ifdef RT_USING_I2C3
  122. static struct am_i2c_bus am_i2c_bus_3 =
  123. {
  124. {3},
  125. AM_I2C3_IOM_INST
  126. };
  127. #endif
  128. #ifdef RT_USING_I2C4
  129. static struct am_i2c_bus am_i2c_bus_4 =
  130. {
  131. {4},
  132. AM_I2C4_IOM_INST
  133. };
  134. #endif
  135. int rt_i2c_init(void)
  136. {
  137. struct am_i2c_bus* am_i2c;
  138. #ifdef RT_USING_I2C0
  139. /* init i2c gpio */
  140. am_hal_gpio_pin_config(I2C0_GPIO_SCL, I2C0_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
  141. am_hal_gpio_pin_config(I2C0_GPIO_SDA, I2C0_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
  142. /* Initialize IOM 0 in I2C mode at 100KHz */
  143. am_hal_iom_pwrctrl_enable(AM_I2C0_IOM_INST);
  144. g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_100KHZ;
  145. am_hal_iom_config(AM_I2C0_IOM_INST, &g_sIOMConfig);
  146. am_hal_iom_enable(AM_I2C0_IOM_INST);
  147. /* init i2c bus device */
  148. am_i2c = &am_i2c_bus_0;
  149. am_i2c->parent.ops = &am_i2c_ops;
  150. rt_i2c_bus_device_register(&am_i2c->parent, "i2c0");
  151. #endif
  152. #ifdef RT_USING_I2C2
  153. /* init i2c gpio */
  154. am_hal_gpio_pin_config(I2C2_GPIO_SCL, I2C2_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
  155. am_hal_gpio_pin_config(I2C2_GPIO_SDA, I2C2_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
  156. /* Initialize IOM 2 in I2C mode at 400KHz */
  157. am_hal_iom_pwrctrl_enable(AM_I2C2_IOM_INST);
  158. g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
  159. am_hal_iom_config(AM_I2C2_IOM_INST, &g_sIOMConfig);
  160. am_hal_iom_enable(AM_I2C2_IOM_INST);
  161. /* init i2c bus device */
  162. am_i2c = &am_i2c_bus_2;
  163. am_i2c->parent.ops = &am_i2c_ops;
  164. rt_i2c_bus_device_register(&am_i2c->parent, "i2c2");
  165. #endif
  166. #ifdef RT_USING_I2C3
  167. /* init i2c gpio */
  168. am_hal_gpio_pin_config(I2C3_GPIO_SCL, I2C3_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
  169. am_hal_gpio_pin_config(I2C3_GPIO_SDA, I2C3_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
  170. /* Initialize IOM 3 in I2C mode at 400KHz */
  171. am_hal_iom_pwrctrl_enable(AM_I2C3_IOM_INST);
  172. g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
  173. am_hal_iom_config(AM_I2C3_IOM_INST, &g_sIOMConfig);
  174. am_hal_iom_enable(AM_I2C3_IOM_INST);
  175. /* init i2c bus device */
  176. am_i2c = &am_i2c_bus_3;
  177. am_i2c->parent.ops = &am_i2c_ops;
  178. rt_i2c_bus_device_register(&am_i2c->parent, "i2c3");
  179. #endif
  180. #ifdef RT_USING_I2C4
  181. /* init i2c gpio */
  182. am_hal_gpio_pin_config(I2C4_GPIO_SCL, I2C4_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
  183. am_hal_gpio_pin_config(I2C4_GPIO_SDA, I2C4_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
  184. /* Initialize IOM 4 in I2C mode at 400KHz */
  185. am_hal_iom_pwrctrl_enable(AM_I2C4_IOM_INST);
  186. g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
  187. am_hal_iom_config(AM_I2C4_IOM_INST, &g_sIOMConfig);
  188. am_hal_iom_enable(AM_I2C4_IOM_INST);
  189. /* init i2c bus device */
  190. am_i2c = &am_i2c_bus_4;
  191. am_i2c->parent.ops = &am_i2c_ops;
  192. rt_i2c_bus_device_register(&am_i2c->parent, "i2c4");
  193. #endif
  194. //rt_kprintf("i2c_init!\n");
  195. return 0;
  196. }
  197. #ifdef RT_USING_COMPONENTS_INIT
  198. INIT_BOARD_EXPORT(rt_i2c_init);
  199. #endif
  200. /*@}*/