drv_spi.c 10 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-03-04 stevetong459 first version
  9. * 2022-07-15 Aligagago add apm32F4 serie MCU support
  10. * 2022-12-26 luobeihai add apm32F0 serie MCU support
  11. */
  12. #include "drv_spi.h"
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.spi"
  15. #include "drv_log.h"
  16. #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
  17. static struct apm32_spi_config spi_config[] = {
  18. #ifdef BSP_USING_SPI1
  19. {SPI1, "spi1"},
  20. #endif
  21. #ifdef BSP_USING_SPI2
  22. {SPI2, "spi2"},
  23. #endif
  24. #ifdef BSP_USING_SPI3
  25. {SPI3, "spi3"},
  26. #endif
  27. };
  28. static struct apm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
  29. /**
  30. * Attach the spi device to SPI bus, this function must be used after initialization.
  31. */
  32. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_T *cs_gpiox, uint16_t cs_gpio_pin)
  33. {
  34. RT_ASSERT(bus_name != RT_NULL);
  35. RT_ASSERT(device_name != RT_NULL);
  36. rt_err_t result;
  37. struct rt_spi_device *spi_device;
  38. struct apm32_spi_cs *cs_pin;
  39. GPIO_Config_T GPIO_InitStructure;
  40. /* initialize the cs pin && select the slave */
  41. #if defined(SOC_SERIES_APM32F0)
  42. GPIO_ConfigStructInit(&GPIO_InitStructure);
  43. GPIO_InitStructure.pin = cs_gpio_pin;
  44. GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
  45. GPIO_InitStructure.mode = GPIO_MODE_OUT;
  46. GPIO_InitStructure.outtype = GPIO_OUT_TYPE_PP;
  47. GPIO_InitStructure.pupd = GPIO_PUPD_NO;
  48. GPIO_Config(cs_gpiox, &GPIO_InitStructure);
  49. GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, Bit_SET);
  50. #elif defined(SOC_SERIES_APM32F1)
  51. GPIO_ConfigStructInit(&GPIO_InitStructure);
  52. GPIO_InitStructure.pin = cs_gpio_pin;
  53. GPIO_InitStructure.mode = GPIO_MODE_OUT_PP;
  54. GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
  55. GPIO_Config(cs_gpiox, &GPIO_InitStructure);
  56. GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, BIT_SET);
  57. #elif defined(SOC_SERIES_APM32F4)
  58. GPIO_ConfigStructInit(&GPIO_InitStructure);
  59. GPIO_InitStructure.pin = cs_gpio_pin;
  60. GPIO_InitStructure.speed = GPIO_SPEED_100MHz;
  61. GPIO_InitStructure.mode = GPIO_MODE_OUT;
  62. GPIO_InitStructure.otype = GPIO_OTYPE_PP;
  63. GPIO_InitStructure.pupd = GPIO_PUPD_NOPULL;
  64. GPIO_Config(cs_gpiox, &GPIO_InitStructure);
  65. GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, BIT_SET);
  66. #endif
  67. /* attach the device to spi bus */
  68. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  69. RT_ASSERT(spi_device != RT_NULL);
  70. cs_pin = (struct apm32_spi_cs *)rt_malloc(sizeof(struct apm32_spi_cs));
  71. RT_ASSERT(cs_pin != RT_NULL);
  72. cs_pin->GPIOx = cs_gpiox;
  73. cs_pin->GPIO_Pin = cs_gpio_pin;
  74. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  75. if (result != RT_EOK)
  76. {
  77. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  78. }
  79. RT_ASSERT(result == RT_EOK);
  80. LOG_D("%s attach to %s done", device_name, bus_name);
  81. return result;
  82. }
  83. static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  84. {
  85. RT_ASSERT(device != RT_NULL);
  86. RT_ASSERT(cfg != RT_NULL);
  87. SPI_Config_T hw_spi_config;
  88. struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus;
  89. struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data;
  90. SPI_T *spi = spi_device->config->spi_x;
  91. uint32_t hw_spi_apb_clock;
  92. #if (DBG_LVL == DBG_LOG)
  93. uint32_t hw_spi_sys_clock = RCM_ReadSYSCLKFreq();
  94. #endif
  95. /* apm32 spi gpio init and enable clock */
  96. extern void apm32_msp_spi_init(void *Instance);
  97. apm32_msp_spi_init(spi);
  98. /* apm32 spi init */
  99. hw_spi_config.mode = (cfg->mode & RT_SPI_SLAVE) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
  100. hw_spi_config.direction = (cfg->mode & RT_SPI_3WIRE) ? SPI_DIRECTION_1LINE_RX : SPI_DIRECTION_2LINES_FULLDUPLEX;
  101. hw_spi_config.phase = (cfg->mode & RT_SPI_CPHA) ? SPI_CLKPHA_2EDGE : SPI_CLKPHA_1EDGE;
  102. hw_spi_config.polarity = (cfg->mode & RT_SPI_CPOL) ? SPI_CLKPOL_HIGH : SPI_CLKPOL_LOW;
  103. #if defined(SOC_SERIES_APM32F0)
  104. hw_spi_config.slaveSelect = (cfg->mode & RT_SPI_NO_CS) ? SPI_SSC_DISABLE : SPI_SSC_ENABLE;
  105. hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRST_BIT_MSB : SPI_FIRST_BIT_LSB;
  106. #else
  107. hw_spi_config.nss = (cfg->mode & RT_SPI_NO_CS) ? SPI_NSS_HARD : SPI_NSS_SOFT;
  108. hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRSTBIT_MSB : SPI_FIRSTBIT_LSB;
  109. #endif
  110. if (cfg->data_width == 8)
  111. {
  112. hw_spi_config.length = SPI_DATA_LENGTH_8B;
  113. }
  114. else if (cfg->data_width == 16)
  115. {
  116. hw_spi_config.length = SPI_DATA_LENGTH_16B;
  117. }
  118. else
  119. {
  120. return -RT_EIO;
  121. }
  122. #if defined(SOC_SERIES_APM32F0)
  123. hw_spi_apb_clock = RCM_ReadPCLKFreq();
  124. #else
  125. if (spi == SPI1)
  126. {
  127. RCM_ReadPCLKFreq(NULL, &hw_spi_apb_clock);
  128. }
  129. else
  130. {
  131. RCM_ReadPCLKFreq(&hw_spi_apb_clock, NULL);
  132. }
  133. #endif
  134. if (cfg->max_hz >= hw_spi_apb_clock / 2)
  135. {
  136. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_2;
  137. }
  138. else if (cfg->max_hz >= hw_spi_apb_clock / 4)
  139. {
  140. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_4;
  141. }
  142. else if (cfg->max_hz >= hw_spi_apb_clock / 8)
  143. {
  144. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_8;
  145. }
  146. else if (cfg->max_hz >= hw_spi_apb_clock / 16)
  147. {
  148. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_16;
  149. }
  150. else if (cfg->max_hz >= hw_spi_apb_clock / 32)
  151. {
  152. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_32;
  153. }
  154. else if (cfg->max_hz >= hw_spi_apb_clock / 64)
  155. {
  156. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_64;
  157. }
  158. else if (cfg->max_hz >= hw_spi_apb_clock / 128)
  159. {
  160. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_128;
  161. }
  162. else
  163. {
  164. /* min prescaler 256 */
  165. hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_256;
  166. }
  167. LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
  168. hw_spi_sys_clock, hw_spi_apb_clock, cfg->max_hz, hw_spi_config.baudrateDiv);
  169. #if defined(SOC_SERIES_APM32F0)
  170. SPI_DisableCRC(spi);
  171. SPI_EnableSSoutput(spi);
  172. SPI_ConfigFIFOThreshold(spi, SPI_RXFIFO_QUARTER);
  173. #endif
  174. SPI_Config(spi, &hw_spi_config);
  175. SPI_Enable(spi);
  176. return RT_EOK;
  177. }
  178. static rt_ssize_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
  179. {
  180. RT_ASSERT(device != NULL);
  181. RT_ASSERT(message != NULL);
  182. struct rt_spi_configuration *config = &device->config;
  183. struct apm32_spi_cs *cs = device->parent.user_data;
  184. struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus;
  185. struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data;
  186. SPI_T *spi = spi_device->config->spi_x;
  187. /* take CS */
  188. if (message->cs_take)
  189. {
  190. #if defined(SOC_SERIES_APM32F0)
  191. GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, (GPIO_BSRET_T)RESET);
  192. #else
  193. GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, RESET);
  194. #endif
  195. LOG_D("spi take cs\n");
  196. }
  197. if (config->data_width <= 8)
  198. {
  199. const rt_uint8_t *send_ptr = message->send_buf;
  200. rt_uint8_t *recv_ptr = message->recv_buf;
  201. rt_uint32_t size = message->length;
  202. LOG_D("spi poll transfer start: %d\n", size);
  203. while (size--)
  204. {
  205. rt_uint8_t data = 0xFF;
  206. if (send_ptr != RT_NULL)
  207. {
  208. data = *send_ptr++;
  209. }
  210. #if defined(SOC_SERIES_APM32F0)
  211. /* Wait until the transmit buffer is empty */
  212. while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
  213. SPI_TxData8(spi, data);
  214. /* Wait until a data is received */
  215. while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
  216. data = SPI_RxData8(spi);
  217. #else
  218. /* Wait until the transmit buffer is empty */
  219. while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
  220. SPI_I2S_TxData(spi, data);
  221. /* Wait until a data is received */
  222. while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
  223. data = SPI_I2S_RxData(spi);
  224. #endif
  225. if (recv_ptr != RT_NULL)
  226. {
  227. *recv_ptr++ = data;
  228. }
  229. }
  230. LOG_D("spi poll transfer finsh\n");
  231. }
  232. else if (config->data_width <= 16)
  233. {
  234. const rt_uint16_t *send_ptr = message->send_buf;
  235. rt_uint16_t *recv_ptr = message->recv_buf;
  236. rt_uint32_t size = message->length;
  237. while (size--)
  238. {
  239. rt_uint16_t data = 0xFF;
  240. if (send_ptr != RT_NULL)
  241. {
  242. data = *send_ptr++;
  243. }
  244. #if defined(SOC_SERIES_APM32F0)
  245. /* Wait until the transmit buffer is empty */
  246. while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
  247. SPI_I2S_TxData16(spi, data);
  248. /* Wait until a data is received */
  249. while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
  250. data = SPI_I2S_RxData16(spi);
  251. #else
  252. /* Wait until the transmit buffer is empty */
  253. while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
  254. /* Send the byte */
  255. SPI_I2S_TxData(spi, data);
  256. /* Wait until a data is received */
  257. while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
  258. /* Get the received data */
  259. data = SPI_I2S_RxData(spi);
  260. #endif
  261. if (recv_ptr != RT_NULL)
  262. {
  263. *recv_ptr++ = data;
  264. }
  265. }
  266. }
  267. /* release CS */
  268. if (message->cs_release)
  269. {
  270. #if defined(SOC_SERIES_APM32F0)
  271. GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, (GPIO_BSRET_T)SET);
  272. #else
  273. GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, SET);
  274. #endif
  275. LOG_D("spi release cs\n");
  276. }
  277. return message->length;
  278. };
  279. static const struct rt_spi_ops apm32_spi_ops =
  280. {
  281. apm32_spi_configure,
  282. apm32_spi_xfer
  283. };
  284. static int rt_hw_spi_init(void)
  285. {
  286. rt_err_t result;
  287. for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
  288. {
  289. spi_bus_obj[i].config = &spi_config[i];
  290. spi_bus_obj[i].spi_bus.parent.user_data = (void *)&spi_bus_obj[i];
  291. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].spi_bus_name, &apm32_spi_ops);
  292. RT_ASSERT(result == RT_EOK);
  293. LOG_D("%s bus init done", spi_config[i].spi_bus_name);
  294. }
  295. return result;
  296. }
  297. INIT_BOARD_EXPORT(rt_hw_spi_init);
  298. #endif /* RT_USING_SPI */