exception.x 6.9 KB

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  1. /* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
  2. /*This file is prepared for Doxygen automatic documentation generation.*/
  3. /*! \file *********************************************************************
  4. *
  5. * \brief Exception and interrupt vectors.
  6. *
  7. * This file maps all events supported by an AVR32.
  8. *
  9. * - Compiler: GNU GCC for AVR32
  10. * - Supported devices: All AVR32 devices with an INTC module can be used.
  11. * - AppNote:
  12. *
  13. * \author Atmel Corporation: http://www.atmel.com \n
  14. * Support and FAQ: http://support.atmel.no/
  15. *
  16. ******************************************************************************/
  17. /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
  18. *
  19. * Redistribution and use in source and binary forms, with or without
  20. * modification, are permitted provided that the following conditions are met:
  21. *
  22. * 1. Redistributions of source code must retain the above copyright notice, this
  23. * list of conditions and the following disclaimer.
  24. *
  25. * 2. Redistributions in binary form must reproduce the above copyright notice,
  26. * this list of conditions and the following disclaimer in the documentation
  27. * and/or other materials provided with the distribution.
  28. *
  29. * 3. The name of Atmel may not be used to endorse or promote products derived
  30. * from this software without specific prior written permission.
  31. *
  32. * 4. This software may only be redistributed and used in connection with an Atmel
  33. * AVR product.
  34. *
  35. * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  36. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  37. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  38. * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  39. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  41. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  42. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  44. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
  45. *
  46. */
  47. #if !__AVR32_UC__ && !__AVR32_AP__
  48. #error Implementation of the AVR32 architecture not supported by the INTC driver.
  49. #endif
  50. #include <avr32/io.h>
  51. //! @{
  52. //! \verbatim
  53. .section .exception, "ax", @progbits
  54. // Start of Exception Vector Table.
  55. // EVBA must be aligned with a power of two strictly greater than the EVBA-
  56. // relative offset of the last vector.
  57. .balign 0x200
  58. // Export symbol.
  59. .global _evba
  60. .type _evba, @function
  61. _evba:
  62. .org 0x000
  63. // Unrecoverable Exception.
  64. _handle_Unrecoverable_Exception:
  65. rjmp $
  66. .org 0x004
  67. // TLB Multiple Hit.
  68. _handle_TLB_Multiple_Hit:
  69. rjmp $
  70. .org 0x008
  71. // Bus Error Data Fetch.
  72. _handle_Bus_Error_Data_Fetch:
  73. rjmp $
  74. .org 0x00C
  75. // Bus Error Instruction Fetch.
  76. _handle_Bus_Error_Instruction_Fetch:
  77. rjmp $
  78. .org 0x010
  79. // NMI.
  80. _handle_NMI:
  81. rjmp $
  82. .org 0x014
  83. // Instruction Address.
  84. _handle_Instruction_Address:
  85. rjmp $
  86. .org 0x018
  87. // ITLB Protection.
  88. _handle_ITLB_Protection:
  89. rjmp $
  90. .org 0x01C
  91. // Breakpoint.
  92. _handle_Breakpoint:
  93. rjmp $
  94. .org 0x020
  95. // Illegal Opcode.
  96. _handle_Illegal_Opcode:
  97. rjmp $
  98. .org 0x024
  99. // Unimplemented Instruction.
  100. _handle_Unimplemented_Instruction:
  101. rjmp $
  102. .org 0x028
  103. // Privilege Violation.
  104. _handle_Privilege_Violation:
  105. rjmp $
  106. .org 0x02C
  107. // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
  108. _handle_Floating_Point:
  109. rjmp $
  110. .org 0x030
  111. // Coprocessor Absent: UNUSED IN AVR32UC.
  112. _handle_Coprocessor_Absent:
  113. rjmp $
  114. .org 0x034
  115. // Data Address (Read).
  116. _handle_Data_Address_Read:
  117. rjmp $
  118. .org 0x038
  119. // Data Address (Write).
  120. _handle_Data_Address_Write:
  121. rjmp $
  122. .org 0x03C
  123. // DTLB Protection (Read).
  124. _handle_DTLB_Protection_Read:
  125. rjmp $
  126. .org 0x040
  127. // DTLB Protection (Write).
  128. _handle_DTLB_Protection_Write:
  129. rjmp $
  130. .org 0x044
  131. // DTLB Modified: UNUSED IN AVR32UC.
  132. _handle_DTLB_Modified:
  133. rjmp $
  134. .org 0x050
  135. // ITLB Miss.
  136. _handle_ITLB_Miss:
  137. rjmp $
  138. .org 0x060
  139. // DTLB Miss (Read).
  140. _handle_DTLB_Miss_Read:
  141. rjmp $
  142. .org 0x070
  143. // DTLB Miss (Write).
  144. _handle_DTLB_Miss_Write:
  145. rjmp $
  146. .org 0x100
  147. // Supervisor Call.
  148. _handle_Supervisor_Call:
  149. rjmp $
  150. // Interrupt support.
  151. // The interrupt controller must provide the offset address relative to EVBA.
  152. // Important note:
  153. // All interrupts call a C function named _get_interrupt_handler.
  154. // This function will read group and interrupt line number to then return in
  155. // R12 a pointer to a user-provided interrupt handler.
  156. .balign 4
  157. .irp priority, 0, 1, 2, 3
  158. _int\priority:
  159. #if __AVR32_UC__
  160. // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
  161. // CPU upon interrupt entry. No other register is saved by hardware.
  162. #elif __AVR32_AP__
  163. // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
  164. // the CPU upon interrupt entry. No other register is saved by hardware.
  165. pushm r8-r12, lr
  166. #endif
  167. mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
  168. call _get_interrupt_handler
  169. cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
  170. #if __AVR32_UC__
  171. movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
  172. #elif __AVR32_AP__
  173. breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch.
  174. st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
  175. popm r8-r12, lr, pc // Restore registers and jump to the handler.
  176. spint\priority:
  177. popm r8-r12, lr
  178. #endif
  179. rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
  180. .endr
  181. // Constant data area.
  182. .balign 4
  183. // Values to store in the interrupt priority registers for the various interrupt priority levels.
  184. // The interrupt priority registers contain the interrupt priority level and
  185. // the EVBA-relative interrupt vector offset.
  186. .global ipr_val
  187. .type ipr_val, @object
  188. ipr_val:
  189. .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
  190. (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
  191. (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
  192. (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
  193. //! \endverbatim
  194. //! @}