drv_smc911x.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020/12/31 Bernard Add license info
  9. */
  10. #include <board.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include <automac.h>
  14. #include <netif/ethernetif.h>
  15. #include <lwipopts.h>
  16. #include "mmu.h"
  17. #include "drv_smc911x.h"
  18. #define MAX_ADDR_LEN 6
  19. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  20. #define DRIVERNAME "EMAC"
  21. #define DBG_LVL DBG_LOG
  22. #define DBG_TAG "EMAC"
  23. #include <rtdbg.h>
  24. struct eth_device_smc911x
  25. {
  26. /* inherit from Ethernet device */
  27. struct eth_device parent;
  28. /* interface address info. */
  29. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  30. uint32_t iobase;
  31. uint32_t irqno;
  32. };
  33. static struct eth_device_smc911x _emac;
  34. #if defined (CONFIG_SMC911X_32_BIT)
  35. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  36. {
  37. return *(volatile uint32_t *)(dev->iobase + offset);
  38. }
  39. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  40. {
  41. *(volatile uint32_t *)(dev->iobase + offset) = val;
  42. }
  43. #elif defined (CONFIG_SMC911X_16_BIT)
  44. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  45. {
  46. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  47. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  48. }
  49. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  50. {
  51. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  52. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  53. }
  54. #else
  55. #error "SMC911X: undefined bus width"
  56. #endif /* CONFIG_SMC911X_16_BIT */
  57. struct chip_id
  58. {
  59. uint16_t id;
  60. char *name;
  61. };
  62. static const struct chip_id chip_ids[] =
  63. {
  64. { LAN9118_ID_89218, "LAN89218" },
  65. { LAN9118_ID_9115, "LAN9115" },
  66. { LAN9118_ID_9116, "LAN9116" },
  67. { LAN9118_ID_9117, "LAN9117" },
  68. { LAN9118_ID_9118, "LAN9118" },
  69. { LAN9210_ID_9211, "LAN9211" },
  70. { LAN9218_ID_9215, "LAN9215" },
  71. { LAN9218_ID_9216, "LAN9216" },
  72. { LAN9218_ID_9217, "LAN9217" },
  73. { LAN9218_ID_9218, "LAN9218" },
  74. { LAN9220_ID_9220, "LAN9220" },
  75. { LAN9220_ID_9221, "LAN9221" },
  76. { 0, RT_NULL },
  77. };
  78. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  79. {
  80. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  81. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
  82. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  83. return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
  84. }
  85. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  86. {
  87. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  88. smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
  89. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
  90. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  91. }
  92. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  93. {
  94. unsigned long val, i;
  95. val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
  96. if (val == 0xffffffff)
  97. {
  98. /* Special case -- no chip present */
  99. return -1;
  100. }
  101. else if (val != 0x87654321)
  102. {
  103. LOG_E("Invalid chip endian 0x%08lx\n", val);
  104. return -1;
  105. }
  106. val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
  107. for (i = 0; chip_ids[i].id != 0; i++)
  108. {
  109. if (chip_ids[i].id == val) break;
  110. }
  111. if (!chip_ids[i].id)
  112. {
  113. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  114. return -1;
  115. }
  116. return 0;
  117. }
  118. static void smc911x_reset(struct eth_device_smc911x *dev)
  119. {
  120. int timeout;
  121. /*
  122. * Take out of PM setting first
  123. * Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
  124. */
  125. if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
  126. {
  127. /* Write to the bytetest will take out of powerdown */
  128. smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
  129. timeout = 10;
  130. while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
  131. udelay(10);
  132. if (timeout < 0)
  133. {
  134. rt_kprintf(DRIVERNAME
  135. ": timeout waiting for PM restore\n");
  136. return;
  137. }
  138. }
  139. /* Disable interrupts */
  140. smc911x_reg_write(dev, LAN9118_INT_EN, 0);
  141. smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
  142. timeout = 1000;
  143. while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
  144. udelay(10);
  145. if (timeout < 0)
  146. {
  147. rt_kprintf(DRIVERNAME ": reset timeout\n");
  148. return;
  149. }
  150. /* Reset the FIFO level and flow control settings */
  151. smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
  152. smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
  153. /* Set to LED outputs */
  154. smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
  155. }
  156. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  157. {
  158. unsigned long addrh, addrl;
  159. uint8_t *m = dev->enetaddr;
  160. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  161. addrh = m[4] | (m[5] << 8);
  162. smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
  163. smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
  164. }
  165. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  166. uint8_t phy, uint8_t reg, uint16_t *val)
  167. {
  168. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  169. smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
  170. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  171. *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
  172. return 0;
  173. }
  174. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  175. uint8_t phy, uint8_t reg, uint16_t val)
  176. {
  177. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  178. ;
  179. smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
  180. smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
  181. phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
  182. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  183. ;
  184. return 0;
  185. }
  186. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  187. {
  188. uint32_t reg;
  189. reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
  190. reg &= ~0xfffff030;
  191. reg |= LAN9118_PMT_CTRL_PHY_RST;
  192. smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
  193. mdelay(100);
  194. return 0;
  195. }
  196. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  197. {
  198. int timeout;
  199. uint16_t status;
  200. smc911x_phy_reset(dev);
  201. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
  202. mdelay(1);
  203. smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
  204. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
  205. timeout = 5000;
  206. do
  207. {
  208. mdelay(1);
  209. if ((timeout--) == 0)
  210. goto err_out;
  211. if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
  212. goto err_out;
  213. }
  214. while (!(status & LAN9118_BMSR_LSTATUS));
  215. return;
  216. err_out:
  217. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  218. }
  219. static void smc911x_enable(struct eth_device_smc911x *dev)
  220. {
  221. /* Enable TX */
  222. smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
  223. smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
  224. smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
  225. /* no padding to start of packets */
  226. smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
  227. smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
  228. LAN9118_MAC_CR_HBDIS);
  229. }
  230. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  231. /* wrapper for smc911x_eth_phy_read */
  232. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  233. int reg)
  234. {
  235. uint16_t val = 0;
  236. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  237. if (dev)
  238. {
  239. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  240. if (retval < 0)
  241. return retval;
  242. return val;
  243. }
  244. return -ENODEV;
  245. }
  246. /* wrapper for smc911x_eth_phy_write */
  247. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  248. int reg, uint16_t val)
  249. {
  250. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  251. if (dev)
  252. return smc911x_eth_phy_write(dev, phy, reg, val);
  253. return -ENODEV;
  254. }
  255. #endif
  256. static void smc911x_isr(int vector, void *param)
  257. {
  258. uint32_t status;
  259. struct eth_device_smc911x *emac;
  260. emac = SMC911X_EMAC_DEVICE(param);
  261. status = smc911x_reg_read(emac, LAN9118_INT_STS);
  262. if (status & LAN9118_INT_STS_RSFL)
  263. {
  264. eth_device_ready(&emac->parent);
  265. }
  266. smc911x_reg_write(emac, LAN9118_INT_STS, status);
  267. return ;
  268. }
  269. static rt_err_t smc911x_emac_init(rt_device_t dev)
  270. {
  271. // uint32_t value;
  272. struct eth_device_smc911x *emac;
  273. emac = SMC911X_EMAC_DEVICE(dev);
  274. RT_ASSERT(emac != RT_NULL);
  275. smc911x_reset(emac);
  276. /* Configure the PHY, initialize the link state */
  277. smc911x_phy_configure(emac);
  278. smc911x_handle_mac_address(emac);
  279. /* Turn on Tx + Rx */
  280. smc911x_enable(emac);
  281. /* Interrupt on every received packet */
  282. smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
  283. smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
  284. /* enable interrupt */
  285. smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  286. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  287. rt_hw_interrupt_umask(emac->irqno);
  288. return RT_EOK;
  289. }
  290. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  291. {
  292. struct eth_device_smc911x *emac;
  293. emac = SMC911X_EMAC_DEVICE(dev);
  294. RT_ASSERT(emac != RT_NULL);
  295. switch (cmd)
  296. {
  297. case NIOCTL_GADDR:
  298. /* get MAC address */
  299. if (args) rt_memcpy(args, emac->enetaddr, 6);
  300. else return -RT_ERROR;
  301. break;
  302. default :
  303. break;
  304. }
  305. return RT_EOK;
  306. }
  307. /* Ethernet device interface */
  308. /* transmit packet. */
  309. static uint8_t tx_buf[2048];
  310. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
  311. {
  312. struct eth_device_smc911x *emac;
  313. uint32_t *data;
  314. uint32_t tmplen;
  315. uint32_t status;
  316. uint32_t length;
  317. emac = SMC911X_EMAC_DEVICE(dev);
  318. RT_ASSERT(emac != RT_NULL);
  319. /* copy pbuf to a whole ETH frame */
  320. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  321. /* send it out */
  322. data = (uint32_t *)tx_buf;
  323. length = p->tot_len;
  324. smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
  325. smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
  326. tmplen = (length + 3) / 4;
  327. while (tmplen--)
  328. {
  329. smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
  330. }
  331. /* wait for transmission */
  332. while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
  333. /* get status. Ignore 'no carrier' error, it has no meaning for
  334. * full duplex operation
  335. */
  336. status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
  337. (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
  338. LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
  339. if (!status) return 0;
  340. LOG_E(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  341. status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
  342. status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
  343. status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
  344. status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
  345. status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
  346. return -RT_EIO;
  347. }
  348. /* reception packet. */
  349. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  350. {
  351. struct pbuf *p = RT_NULL;
  352. struct eth_device_smc911x *emac;
  353. emac = SMC911X_EMAC_DEVICE(dev);
  354. RT_ASSERT(emac != RT_NULL);
  355. /* take the emac buffer to the pbuf */
  356. if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
  357. {
  358. uint32_t status;
  359. uint32_t pktlen, tmplen;
  360. status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
  361. /* get frame length */
  362. pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
  363. smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
  364. tmplen = (pktlen + 3) / 4;
  365. /* allocate pbuf */
  366. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  367. if (p)
  368. {
  369. uint32_t *data = (uint32_t *)p->payload;
  370. while (tmplen--)
  371. {
  372. *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
  373. }
  374. }
  375. if (status & LAN9118_RXS_ES)
  376. {
  377. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  378. }
  379. }
  380. return p;
  381. }
  382. #ifdef RT_USING_DEVICE_OPS
  383. const static struct rt_device_ops smc911x_emac_ops =
  384. {
  385. smc911x_emac_init,
  386. RT_NULL,
  387. RT_NULL,
  388. RT_NULL,
  389. RT_NULL,
  390. smc911x_emac_control
  391. };
  392. #endif
  393. int smc911x_emac_hw_init(void)
  394. {
  395. rt_memset(&_emac, 0x0, sizeof(_emac));
  396. _emac.iobase = VEXPRESS_ETH_BASE;
  397. #ifdef RT_USING_SMART
  398. _emac.iobase = (uint32_t)rt_ioremap((void*)VEXPRESS_ETH_BASE, 0x1000);
  399. #endif
  400. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  401. if (smc911x_detect_chip(&_emac))
  402. {
  403. rt_kprintf("no smc911x network interface found!\n");
  404. return -1;
  405. }
  406. /* set INT CFG */
  407. smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  408. /* test MAC address */
  409. _emac.enetaddr[0] = AUTOMAC0;
  410. _emac.enetaddr[1] = AUTOMAC1;
  411. _emac.enetaddr[2] = AUTOMAC2;
  412. _emac.enetaddr[3] = AUTOMAC3;
  413. _emac.enetaddr[4] = AUTOMAC4;
  414. _emac.enetaddr[5] = AUTOMAC5;
  415. #ifdef RT_USING_DEVICE_OPS
  416. _emac.parent.parent.ops = &smc911x_emac_ops;
  417. #else
  418. _emac.parent.parent.init = smc911x_emac_init;
  419. _emac.parent.parent.open = RT_NULL;
  420. _emac.parent.parent.close = RT_NULL;
  421. _emac.parent.parent.read = RT_NULL;
  422. _emac.parent.parent.write = RT_NULL;
  423. _emac.parent.parent.control = smc911x_emac_control;
  424. #endif
  425. _emac.parent.parent.user_data = RT_NULL;
  426. _emac.parent.eth_rx = smc911x_emac_rx;
  427. _emac.parent.eth_tx = smc911x_emac_tx;
  428. /* register ETH device */
  429. eth_device_init(&(_emac.parent), "e0");
  430. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  431. {
  432. int retval;
  433. struct mii_dev *mdiodev = mdio_alloc();
  434. if (!mdiodev)
  435. return -ENOMEM;
  436. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  437. mdiodev->read = smc911x_miiphy_read;
  438. mdiodev->write = smc911x_miiphy_write;
  439. retval = mdio_register(mdiodev);
  440. if (retval < 0)
  441. return retval;
  442. }
  443. #endif
  444. eth_device_linkchange(&_emac.parent, RT_TRUE);
  445. return 0;
  446. }
  447. INIT_APP_EXPORT(smc911x_emac_hw_init);