drv_eth.h 17 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-07-20 thread-liu the first version
  9. */
  10. #ifndef __DRV_ETH_H__
  11. #define __DRV_ETH_H__
  12. #include <rtthread.h>
  13. #include <rthw.h>
  14. #include <rtdevice.h>
  15. #include <board.h>
  16. #ifdef __cplusplus
  17. extern "C" {
  18. #endif
  19. typedef struct
  20. {
  21. uint32_t Speed; /*!< Sets the Ethernet speed: 10/100/1000 Mbps.
  22. This parameter can be a value of @ref ETH_Speed */
  23. uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
  24. This parameter can be a value of @ref ETH_Duplex_Mode */
  25. } ETH_MACConfigTypeDef;
  26. /**
  27. * @brief Transmit descriptor
  28. **/
  29. typedef struct
  30. {
  31. uint32_t tdes0;
  32. uint32_t tdes1;
  33. uint32_t tdes2;
  34. uint32_t tdes3;
  35. } TxDmaDesc;
  36. /**
  37. * @brief Receive descriptor
  38. **/
  39. typedef struct
  40. {
  41. uint32_t rdes0;
  42. uint32_t rdes1;
  43. uint32_t rdes2;
  44. uint32_t rdes3;
  45. } RxDmaDesc;
  46. #define RTL8211F_PHY_ADDR 1 /* PHY address */
  47. #define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
  48. #define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */
  49. #define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
  50. #define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */
  51. #define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */
  52. /* Register access macros */
  53. #define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
  54. #define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
  55. #define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
  56. #define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
  57. #define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
  58. #define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
  59. #define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
  60. #define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)
  61. #define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
  62. #define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
  63. #define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
  64. #define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
  65. /* Transmit normal descriptor (read format) */
  66. #define ETH_TDES0_BUF1AP 0xFFFFFFFF
  67. #define ETH_TDES1_BUF2AP 0xFFFFFFFF
  68. #define ETH_TDES2_IOC 0x80000000
  69. #define ETH_TDES2_TTSE 0x40000000
  70. #define ETH_TDES2_B2L 0x3FFF0000
  71. #define ETH_TDES2_VTIR 0x0000C000
  72. #define ETH_TDES2_B1L 0x00003FFF
  73. #define ETH_TDES3_OWN 0x80000000
  74. #define ETH_TDES3_CTXT 0x40000000
  75. #define ETH_TDES3_FD 0x20000000
  76. #define ETH_TDES3_LD 0x10000000
  77. #define ETH_TDES3_CPC 0x0C000000
  78. #define ETH_TDES3_SAIC 0x03800000
  79. #define ETH_TDES3_THL 0x00780000
  80. #define ETH_TDES3_TSE 0x00040000
  81. #define ETH_TDES3_CIC 0x00030000
  82. #define ETH_TDES3_FL 0x00007FFF
  83. /* Transmit normal descriptor (write-back format) */
  84. #define ETH_TDES0_TTSL 0xFFFFFFFF
  85. #define ETH_TDES1_TTSH 0xFFFFFFFF
  86. #define ETH_TDES3_OWN 0x80000000
  87. #define ETH_TDES3_CTXT 0x40000000
  88. #define ETH_TDES3_FD 0x20000000
  89. #define ETH_TDES3_LD 0x10000000
  90. #define ETH_TDES3_TTSS 0x00020000
  91. #define ETH_TDES3_ES 0x00008000
  92. #define ETH_TDES3_JT 0x00004000
  93. #define ETH_TDES3_FF 0x00002000
  94. #define ETH_TDES3_PCE 0x00001000
  95. #define ETH_TDES3_LOC 0x00000800
  96. #define ETH_TDES3_NC 0x00000400
  97. #define ETH_TDES3_LC 0x00000200
  98. #define ETH_TDES3_EC 0x00000100
  99. #define ETH_TDES3_CC 0x000000F0
  100. #define ETH_TDES3_ED 0x00000008
  101. #define ETH_TDES3_UF 0x00000004
  102. #define ETH_TDES3_DB 0x00000002
  103. #define ETH_TDES3_IHE 0x00000001
  104. /* Transmit context descriptor */
  105. #define ETH_TDES0_TTSL 0xFFFFFFFF
  106. #define ETH_TDES1_TTSH 0xFFFFFFFF
  107. #define ETH_TDES2_IVT 0xFFFF0000
  108. #define ETH_TDES2_MSS 0x00003FFF
  109. #define ETH_TDES3_OWN 0x80000000
  110. #define ETH_TDES3_CTXT 0x40000000
  111. #define ETH_TDES3_OSTC 0x08000000
  112. #define ETH_TDES3_TCMSSV 0x04000000
  113. #define ETH_TDES3_CDE 0x00800000
  114. #define ETH_TDES3_IVLTV 0x00020000
  115. #define ETH_TDES3_VLTV 0x00010000
  116. #define ETH_TDES3_VT 0x0000FFFF
  117. /* Receive normal descriptor (read format) */
  118. #define ETH_RDES0_BUF1AP 0xFFFFFFFF
  119. #define ETH_RDES2_BUF2AP 0xFFFFFFFF
  120. #define ETH_RDES3_OWN 0x80000000
  121. #define ETH_RDES3_IOC 0x40000000
  122. #define ETH_RDES3_BUF2V 0x02000000
  123. #define ETH_RDES3_BUF1V 0x01000000
  124. /* Receive normal descriptor (write-back format) */
  125. #define ETH_RDES0_IVT 0xFFFF0000
  126. #define ETH_RDES0_OVT 0x0000FFFF
  127. #define ETH_RDES1_OPC 0xFFFF0000
  128. #define ETH_RDES1_TD 0x00008000
  129. #define ETH_RDES1_TSA 0x00004000
  130. #define ETH_RDES1_PV 0x00002000
  131. #define ETH_RDES1_PFT 0x00001000
  132. #define ETH_RDES1_PMT 0x00000F00
  133. #define ETH_RDES1_IPCE 0x00000080
  134. #define ETH_RDES1_IPCB 0x00000040
  135. #define ETH_RDES1_IPV6 0x00000020
  136. #define ETH_RDES1_IPV4 0x00000010
  137. #define ETH_RDES1_IPHE 0x00000008
  138. #define ETH_RDES1_PT 0x00000007
  139. #define ETH_RDES2_L3L4FM 0xE0000000
  140. #define ETH_RDES2_L4FM 0x10000000
  141. #define ETH_RDES2_L3FM 0x08000000
  142. #define ETH_RDES2_MADRM 0x07F80000
  143. #define ETH_RDES2_HF 0x00040000
  144. #define ETH_RDES2_DAF 0x00020000
  145. #define ETH_RDES2_SAF 0x00010000
  146. #define ETH_RDES2_VF 0x00008000
  147. #define ETH_RDES2_ARPRN 0x00000400
  148. #define ETH_RDES3_OWN 0x80000000
  149. #define ETH_RDES3_CTXT 0x40000000
  150. #define ETH_RDES3_FD 0x20000000
  151. #define ETH_RDES3_LD 0x10000000
  152. #define ETH_RDES3_RS2V 0x08000000
  153. #define ETH_RDES3_RS1V 0x04000000
  154. #define ETH_RDES3_RS0V 0x02000000
  155. #define ETH_RDES3_CE 0x01000000
  156. #define ETH_RDES3_GP 0x00800000
  157. #define ETH_RDES3_RWT 0x00400000
  158. #define ETH_RDES3_OE 0x00200000
  159. #define ETH_RDES3_RE 0x00100000
  160. #define ETH_RDES3_DE 0x00080000
  161. #define ETH_RDES3_LT 0x00070000
  162. #define ETH_RDES3_ES 0x00008000
  163. #define ETH_RDES3_PL 0x00007FFF
  164. /* Receive context descriptor */
  165. #define ETH_RDES0_RTSL 0xFFFFFFFF
  166. #define ETH_RDES1_RTSH 0xFFFFFFFF
  167. #define ETH_RDES3_OWN 0x80000000
  168. #define ETH_RDES3_CTXT 0x40000000
  169. #define RTL8211F_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */
  170. #define RTL8211F_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */
  171. #define RTL8211F_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */
  172. #define RTL8211F_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */
  173. #define RTL8211F_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */
  174. #define RTL8211F_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */
  175. #define RTL8211F_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/
  176. #define RTL8211F_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/
  177. #define RTL8211F_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */
  178. #define RTL8211F_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */
  179. #define RTL8211F_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */
  180. #define RTL8211F_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */
  181. #define RTL8211F_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */
  182. #define RTL8211F_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */
  183. #define RTL8211F_LCR ((uint16_t)0x0010U) /* LED Control Register. */
  184. #define RTL8211F_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */
  185. #define RTL8211F_PHYSCR ((uint16_t)0x0014U) /* PHY Special Cofig Register */
  186. #define RTL8211F_PHYCR1 ((uint16_t)0x0018U) /* PHY Specific Control Register 1. */
  187. #define RTL8211F_PHYCR2 ((uint16_t)0x0019U) /* PHY Specific Control Register 2. */
  188. #define RTL8211F_PHYSR ((uint16_t)0x001AU) /* PHY Specific Status Register. */
  189. #define RTL8211F_INSR ((uint16_t)0x001DU) /* Interrupt Status Register. */
  190. #define RTL8211F_PAGSR ((uint16_t)0x001FU) /* Page Select Register. */
  191. /* Basic Mode Control register */
  192. #define RTL8211F_BMCR_RESET 0x8000
  193. #define RTL8211F_BMCR_LOOPBACK 0x4000
  194. #define RTL8211F_BMCR_SPEED_SEL_LSB 0x2000
  195. #define RTL8211F_BMCR_AN_EN 0x1000
  196. #define RTL8211F_BMCR_POWER_DOWN 0x0800
  197. #define RTL8211F_BMCR_ISOLATE 0x0400
  198. #define RTL8211F_BMCR_RESTART_AN 0x0200
  199. #define RTL8211F_BMCR_DUPLEX_MODE 0x0100
  200. #define RTL8211F_BMCR_COL_TEST 0x0080
  201. #define RTL8211F_BMCR_SPEED_SEL_MSB 0x0040
  202. #define RTL8211F_BMCR_UNI_DIR_EN 0x0020
  203. /* Basic Mode Status register */
  204. #define RTL8211F_BMSR_100BT4 0x8000
  205. #define RTL8211F_BMSR_100BTX_FD 0x4000
  206. #define RTL8211F_BMSR_100BTX_HD 0x2000
  207. #define RTL8211F_BMSR_10BT_FD 0x1000
  208. #define RTL8211F_BMSR_10BT_HD 0x0800
  209. #define RTL8211F_BMSR_100BT2_FD 0x0400
  210. #define RTL8211F_BMSR_100BT2_HD 0x0200
  211. #define RTL8211F_BMSR_EXTENDED_STATUS 0x0100
  212. #define RTL8211F_BMSR_UNI_DIR_CAPABLE 0x0080
  213. #define RTL8211F_BMSR_PREAMBLE_SUPPR 0x0040
  214. #define RTL8211F_BMSR_AN_COMPLETE 0x0020
  215. #define RTL8211F_BMSR_REMOTE_FAULT 0x0010
  216. #define RTL8211F_BMSR_AN_CAPABLE 0x0008
  217. #define RTL8211F_BMSR_LINK_STATUS 0x0004
  218. #define RTL8211F_BMSR_JABBER_DETECT 0x0002
  219. #define RTL8211F_BMSR_EXTENDED_CAPABLE 0x0001
  220. /* PHY Identifier 1 register */
  221. #define RTL8211F_PHYID1_OUI_MSB 0xFFFF
  222. #define RTL8211F_PHYID1_OUI_MSB_DEFAULT 0x001C
  223. /* PHY Identifier 2 register */
  224. #define RTL8211F_PHYID2_OUI_LSB 0xFC00
  225. #define RTL8211F_PHYID2_OUI_LSB_DEFAULT 0xC800
  226. #define RTL8211F_PHYID2_MODEL_NUM 0x03F0
  227. #define RTL8211F_PHYID2_MODEL_NUM_DEFAULT 0x0110
  228. #define RTL8211F_PHYID2_REVISION_NUM 0x000F
  229. #define RTL8211F_PHYID2_REVISION_NUM_DEFAULT 0x0006
  230. /* Auto-Negotiation Advertisement register */
  231. #define RTL8211F_ANAR_NEXT_PAGE 0x8000
  232. #define RTL8211F_ANAR_REMOTE_FAULT 0x2000
  233. #define RTL8211F_ANAR_ASYM_PAUSE 0x0800
  234. #define RTL8211F_ANAR_PAUSE 0x0400
  235. #define RTL8211F_ANAR_100BT4 0x0200
  236. #define RTL8211F_ANAR_100BTX_FD 0x0100
  237. #define RTL8211F_ANAR_100BTX_HD 0x0080
  238. #define RTL8211F_ANAR_10BT_FD 0x0040
  239. #define RTL8211F_ANAR_10BT_HD 0x0020
  240. #define RTL8211F_ANAR_SELECTOR 0x001F
  241. #define RTL8211F_ANAR_SELECTOR_DEFAULT 0x0001
  242. /* Auto-Negotiation Link Partner Ability register */
  243. #define RTL8211F_ANLPAR_NEXT_PAGE 0x8000
  244. #define RTL8211F_ANLPAR_ACK 0x4000
  245. #define RTL8211F_ANLPAR_REMOTE_FAULT 0x2000
  246. #define RTL8211F_ANLPAR_ASYM_PAUSE 0x0800
  247. #define RTL8211F_ANLPAR_PAUSE 0x0400
  248. #define RTL8211F_ANLPAR_100BT4 0x0200
  249. #define RTL8211F_ANLPAR_100BTX_FD 0x0100
  250. #define RTL8211F_ANLPAR_100BTX_HD 0x0080
  251. #define RTL8211F_ANLPAR_10BT_FD 0x0040
  252. #define RTL8211F_ANLPAR_10BT_HD 0x0020
  253. #define RTL8211F_ANLPAR_SELECTOR 0x001F
  254. #define RTL8211F_ANLPAR_SELECTOR_DEFAULT 0x0001
  255. /* Auto-Negotiation Expansion register */
  256. #define RTL8211F_ANER_RX_NP_LOCATION_ABLE 0x0040
  257. #define RTL8211F_ANER_RX_NP_LOCATION 0x0020
  258. #define RTL8211F_ANER_PAR_DETECT_FAULT 0x0010
  259. #define RTL8211F_ANER_LP_NEXT_PAGE_ABLE 0x0008
  260. #define RTL8211F_ANER_NEXT_PAGE_ABLE 0x0004
  261. #define RTL8211F_ANER_PAGE_RECEIVED 0x0002
  262. #define RTL8211F_ANER_LP_AN_ABLE 0x0001
  263. /* Auto-Negotiation Next Page Transmit register */
  264. #define RTL8211F_ANNPTR_NEXT_PAGE 0x8000
  265. #define RTL8211F_ANNPTR_MSG_PAGE 0x2000
  266. #define RTL8211F_ANNPTR_ACK2 0x1000
  267. #define RTL8211F_ANNPTR_TOGGLE 0x0800
  268. #define RTL8211F_ANNPTR_MESSAGE 0x07FF
  269. /* Auto-Negotiation Next Page Receive register */
  270. #define RTL8211F_ANNPRR_NEXT_PAGE 0x8000
  271. #define RTL8211F_ANNPRR_ACK 0x4000
  272. #define RTL8211F_ANNPRR_MSG_PAGE 0x2000
  273. #define RTL8211F_ANNPRR_ACK2 0x1000
  274. #define RTL8211F_ANNPRR_TOGGLE 0x0800
  275. #define RTL8211F_ANNPRR_MESSAGE 0x07FF
  276. /* 1000Base-T Control register */
  277. #define RTL8211F_GBCR_TEST_MODE 0xE000
  278. #define RTL8211F_GBCR_MS_MAN_CONF_EN 0x1000
  279. #define RTL8211F_GBCR_MS_MAN_CONF_VAL 0x0800
  280. #define RTL8211F_GBCR_PORT_TYPE 0x0400
  281. #define RTL8211F_GBCR_1000BT_FD 0x0200
  282. /* 1000Base-T Status register */
  283. #define RTL8211F_GBSR_MS_CONF_FAULT 0x8000
  284. #define RTL8211F_GBSR_MS_CONF_RES 0x4000
  285. #define RTL8211F_GBSR_LOCAL_RECEIVER_STATUS 0x2000
  286. #define RTL8211F_GBSR_REMOTE_RECEIVER_STATUS 0x1000
  287. #define RTL8211F_GBSR_LP_1000BT_FD 0x0800
  288. #define RTL8211F_GBSR_LP_1000BT_HD 0x0400
  289. #define RTL8211F_GBSR_IDLE_ERR_COUNT 0x00FF
  290. /* MMD Access Control register */
  291. #define RTL8211F_MMDACR_FUNC 0xC000
  292. #define RTL8211F_MMDACR_FUNC_ADDR 0x0000
  293. #define RTL8211F_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
  294. #define RTL8211F_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
  295. #define RTL8211F_MMDACR_FUNC_DATA_POST_INC_W 0xC000
  296. #define RTL8211F_MMDACR_DEVAD 0x001F
  297. /* 1000Base-T Extended Status register */
  298. #define RTL8211F_GBESR_1000BX_FD 0x8000
  299. #define RTL8211F_GBESR_1000BX_HD 0x4000
  300. #define RTL8211F_GBESR_1000BT_FD 0x2000
  301. #define RTL8211F_GBESR_1000BT_HD 0x1000
  302. /* Interrupt Enable register */
  303. #define RTL8211F_INER_JABBER 0x0400
  304. #define RTL8211F_INER_ALDPS_STATE 0x0200
  305. #define RTL8211F_INER_PME 0x0080
  306. #define RTL8211F_INER_PHY_REG_ACCESS 0x0020
  307. #define RTL8211F_INER_LINK_STATUS 0x0010
  308. #define RTL8211F_INER_AN_COMPLETE 0x0008
  309. #define RTL8211F_INER_PAGE_RECEIVED 0x0004
  310. #define RTL8211F_INER_AN_ERROR 0x0001
  311. /* PHY Specific Control 1 register */
  312. #define RTL8211F_PHYCR1_PHYAD_0_EN 0x2000
  313. #define RTL8211F_PHYCR1_MDI_MODE_MANUAL_CONFIG 0x0200
  314. #define RTL8211F_PHYCR1_MDI_MODE 0x0100
  315. #define RTL8211F_PHYCR1_TX_CRS_EN 0x0080
  316. #define RTL8211F_PHYCR1_PHYAD_NON_ZERO_DETECT 0x0040
  317. #define RTL8211F_PHYCR1_PREAMBLE_CHECK_EN 0x0010
  318. #define RTL8211F_PHYCR1_JABBER_DETECT_EN 0x0008
  319. #define RTL8211F_PHYCR1_ALDPS_EN 0x0004
  320. /* PHY Specific Control 2 register */
  321. #define RTL8211F_PHYCR2_CLKOUT_FREQ_SEL 0x0800
  322. #define RTL8211F_PHYCR2_CLKOUT_SSC_EN 0x0080
  323. #define RTL8211F_PHYCR2_RXC_SSC_EN 0x0008
  324. #define RTL8211F_PHYCR2_RXC_EN 0x0002
  325. #define RTL8211F_PHYCR2_CLKOUT_EN 0x0001
  326. /* PHY Specific Status register */
  327. #define RTL8211F_PHYSR_ALDPS_STATE 0x4000
  328. #define RTL8211F_PHYSR_MDI_PLUG 0x2000
  329. #define RTL8211F_PHYSR_NWAY_EN 0x1000
  330. #define RTL8211F_PHYSR_MASTER_MODE 0x0800
  331. #define RTL8211F_PHYSR_EEE_CAPABLE 0x0100
  332. #define RTL8211F_PHYSR_RX_FLOW_EN 0x0080
  333. #define RTL8211F_PHYSR_TX_FLOW_EN 0x0040
  334. #define RTL8211F_PHYSR_SPEED 0x0030
  335. #define RTL8211F_PHYSR_SPEED_10MBPS 0x0000
  336. #define RTL8211F_PHYSR_SPEED_100MBPS 0x0010
  337. #define RTL8211F_PHYSR_SPEED_1000MBPS 0x0020
  338. #define RTL8211F_PHYSR_DUPLEX 0x0008
  339. #define RTL8211F_PHYSR_LINK 0x0004
  340. #define RTL8211F_PHYSR_MDI_CROSSOVER_STATUS 0x0002
  341. #define RTL8211F_PHYSR_JABBER 0x0001
  342. /* Interrupt Status register */
  343. #define RTL8211F_INSR_JABBER 0x0400
  344. #define RTL8211F_INSR_ALDPS_STATE 0x0200
  345. #define RTL8211F_INSR_PME 0x0080
  346. #define RTL8211F_INSR_PHY_REG_ACCESS 0x0020
  347. #define RTL8211F_INSR_LINK_STATUS 0x0010
  348. #define RTL8211F_INSR_AN_COMPLETE 0x0008
  349. #define RTL8211F_INSR_PAGE_RECEIVED 0x0004
  350. #define RTL8211F_INSR_AN_ERROR 0x0001
  351. /* Page Select register */
  352. #define RTL8211F_PAGSR_PAGE_SEL 0x0007
  353. #ifdef __cplusplus
  354. }
  355. #endif
  356. #endif