startup_ARMCM0.s 9.0 KB

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  1. ;/**************************************************************************//**
  2. ; * @file startup_ARMCM0.s
  3. ; * @brief CMSIS Core Device Startup File for
  4. ; * ARMCM0 Device Series
  5. ; * @version V1.08
  6. ; * @date 23. November 2012
  7. ; *
  8. ; * @note
  9. ; *
  10. ; ******************************************************************************/
  11. ;/* Copyright (c) 2011 - 2012 ARM LIMITED
  12. ;
  13. ; All rights reserved.
  14. ; Redistribution and use in source and binary forms, with or without
  15. ; modification, are permitted provided that the following conditions are met:
  16. ; - Redistributions of source code must retain the above copyright
  17. ; notice, this list of conditions and the following disclaimer.
  18. ; - Redistributions in binary form must reproduce the above copyright
  19. ; notice, this list of conditions and the following disclaimer in the
  20. ; documentation and/or other materials provided with the distribution.
  21. ; - Neither the name of ARM nor the names of its contributors may be used
  22. ; to endorse or promote products derived from this software without
  23. ; specific prior written permission.
  24. ; *
  25. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26. ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27. ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28. ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  29. ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30. ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31. ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32. ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33. ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34. ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35. ; POSSIBILITY OF SUCH DAMAGE.
  36. ; ---------------------------------------------------------------------------*/
  37. ;/*
  38. ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  39. ;*/
  40. ; <h> Stack Configuration
  41. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  42. ; </h>
  43. Stack_Size EQU 0x00000400
  44. AREA STACK, NOINIT, READWRITE, ALIGN=3
  45. Stack_Mem SPACE Stack_Size
  46. __initial_sp EQU 0x20008000
  47. ; <h> Heap Configuration
  48. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  49. ; </h>
  50. Heap_Size EQU 0x00000400
  51. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  52. __heap_base
  53. Heap_Mem SPACE Heap_Size
  54. __heap_limit
  55. PRESERVE8
  56. THUMB
  57. ; Vector Table Mapped to Address 0 at Reset
  58. AREA RESET, DATA, READONLY
  59. EXPORT __Vectors
  60. EXPORT __Vectors_End
  61. EXPORT __Vectors_Size
  62. __Vectors DCD __initial_sp ; Top of Stack
  63. DCD Reset_Handler ; Reset Handler
  64. DCD NMI_Handler ; NMI Handler
  65. DCD HardFault_Handler ; Hard Fault Handler
  66. DCD 0 ; Reserved
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD 0 ; Reserved
  72. DCD 0 ; Reserved
  73. DCD SVC_Handler ; SVCall Handler
  74. DCD 0 ; Reserved
  75. DCD 0 ; Reserved
  76. DCD PendSV_Handler ; PendSV Handler
  77. DCD SysTick_Handler ; SysTick Handler
  78. ; External Interrupts
  79. DCD TMR0_IRQHandler ; 0: TMR0
  80. DCD GPIO_IRQHandler ; 1: GPIO
  81. DCD SLAVE_IRQHandler ; 2: SLAVE
  82. DCD SPI0_IRQHandler ; 3: SPI0
  83. DCD BB_IRQHandler ; 4: BB
  84. DCD LLE_IRQHandler ; 5: LLE
  85. DCD USB_IRQHandler ; 6: USB
  86. DCD ETH_IRQHandler ; 7: ETH
  87. DCD TMR1_IRQHandler ; 8: TMR1
  88. DCD TMR2_IRQHandler ; 9: TMR2
  89. DCD UART0_IRQHandler ; 10: UART0
  90. DCD UART1_IRQHandler ; 11: UART1
  91. DCD RTC_IRQHandler ; 12: RTC
  92. DCD ADC_IRQHandler ; 13: ADC
  93. DCD SPI1_IRQHandler ; 14: SPI1
  94. DCD LED_IRQHandler ; 15: LED
  95. DCD TMR3_IRQHandler ; 16: TMR3
  96. DCD UART2_IRQHandler ; 17: UART2
  97. DCD UART3_IRQHandler ; 18: UART3
  98. DCD WDT_IRQHandler ; 19: WDT
  99. __Vectors_End
  100. __Vectors_Size EQU __Vectors_End - __Vectors
  101. AREA |.text|, CODE, READONLY
  102. ; Reset Handler
  103. Reset_Handler PROC
  104. EXPORT Reset_Handler [WEAK]
  105. IMPORT SystemInit
  106. IMPORT __main
  107. ;LDR R0, =0x1007058
  108. ;MOV SP, R0
  109. LDR R0, =SystemInit
  110. BLX R0
  111. LDR R0, =__main
  112. BX R0
  113. ENDP
  114. ; Dummy Exception Handlers (infinite loops which can be modified)
  115. NMI_Handler PROC
  116. EXPORT NMI_Handler [WEAK]
  117. B .
  118. ENDP
  119. HardFault_Handler\
  120. PROC
  121. EXPORT HardFault_Handler [WEAK]
  122. ; B .
  123. ENDP
  124. SVC_Handler PROC
  125. EXPORT SVC_Handler [WEAK]
  126. B .
  127. ENDP
  128. PendSV_Handler PROC
  129. EXPORT PendSV_Handler [WEAK]
  130. B .
  131. ENDP
  132. SysTick_Handler PROC
  133. EXPORT SysTick_Handler [WEAK]
  134. B .
  135. ENDP
  136. Default_Handler PROC
  137. EXPORT TMR0_IRQHandler [WEAK]; 0: TMR0
  138. EXPORT GPIO_IRQHandler [WEAK]; 1: GPIO
  139. EXPORT SLAVE_IRQHandler [WEAK]; 2: SLAVE
  140. EXPORT SPI0_IRQHandler [WEAK]; 3: SPI0
  141. EXPORT BB_IRQHandler [WEAK]; 4: BB
  142. EXPORT LLE_IRQHandler [WEAK]; 5: LLE
  143. EXPORT USB_IRQHandler [WEAK]; 6: USB
  144. EXPORT ETH_IRQHandler [WEAK]; 7: ETH
  145. EXPORT TMR1_IRQHandler [WEAK]; 8: TMR1
  146. EXPORT TMR2_IRQHandler [WEAK]; 9: TMR2
  147. EXPORT UART0_IRQHandler [WEAK]; 10: UART0
  148. EXPORT UART1_IRQHandler [WEAK]; 11: UART1
  149. EXPORT RTC_IRQHandler [WEAK]; 12: RTC
  150. EXPORT ADC_IRQHandler [WEAK]; 13: ADC
  151. EXPORT SPI1_IRQHandler [WEAK]; 14: SPI1
  152. EXPORT LED_IRQHandler [WEAK]; 15: LED
  153. EXPORT TMR3_IRQHandler [WEAK]; 16: TMR3
  154. EXPORT UART2_IRQHandler [WEAK]; 17: UART2
  155. EXPORT UART3_IRQHandler [WEAK]; 18: UART3
  156. EXPORT WDT_IRQHandler [WEAK]; 19: WDT
  157. TMR0_IRQHandler ; 0: TMR0
  158. GPIO_IRQHandler ; 1: GPIO
  159. SLAVE_IRQHandler ; 2: SLAVE
  160. SPI0_IRQHandler ; 3: SPI0
  161. BB_IRQHandler ; 4: BB
  162. LLE_IRQHandler ; 5: LLE
  163. USB_IRQHandler ; 6: USB
  164. ETH_IRQHandler ; 7: ETH
  165. TMR1_IRQHandler ; 8: TMR1
  166. TMR2_IRQHandler ; 9: TMR2
  167. UART0_IRQHandler ; 10: UART0
  168. UART1_IRQHandler ; 11: UART1
  169. RTC_IRQHandler ; 12: RTC
  170. ADC_IRQHandler ; 13: ADC
  171. SPI1_IRQHandler ; 14: SPI1
  172. LED_IRQHandler ; 15: LED
  173. TMR3_IRQHandler ; 16: TMR3
  174. UART2_IRQHandler ; 17: UART2
  175. UART3_IRQHandler ; 18: UART3
  176. WDT_IRQHandler ; 19: WDT
  177. B .
  178. ENDP
  179. ALIGN
  180. ; User Initial Stack & Heap
  181. IF :DEF:__MICROLIB
  182. EXPORT __initial_sp
  183. EXPORT __heap_base
  184. EXPORT __heap_limit
  185. ELSE
  186. IMPORT __use_two_region_memory
  187. EXPORT __user_initial_stackheap
  188. __user_initial_stackheap PROC
  189. LDR R0, = Heap_Mem
  190. LDR R1, =(Stack_Mem + Stack_Size)
  191. LDR R2, = (Heap_Mem + Heap_Size)
  192. LDR R3, = Stack_Mem
  193. BX LR
  194. ENDP
  195. ALIGN
  196. ENDIF
  197. END