hpm_pmp_drv.h 6.6 KB

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  1. /*
  2. * Copyright (c) 2021-2022 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #ifndef HPM_PMP_DRV_H
  8. #define HPM_PMP_DRV_H
  9. #include "hpm_common.h"
  10. /**
  11. * @brief PMP Entry structure
  12. */
  13. typedef struct pmp_entry_struct {
  14. union {
  15. struct {
  16. uint8_t read_access_ctrl: 1;
  17. uint8_t write_access_ctrl: 1;
  18. uint8_t execution_ctrl: 1;
  19. uint8_t addr_matching_mode: 2;
  20. uint8_t reserved: 2;
  21. uint8_t lock: 1;
  22. };
  23. uint8_t val;
  24. } pmp_cfg;
  25. uint8_t reserved0[3];
  26. uint32_t pmp_addr;
  27. union {
  28. struct {
  29. uint8_t entry_addr_matching_mode: 2;
  30. uint8_t mem_type_attribute: 4;
  31. uint8_t automic_mem_operation_ctrl: 1;
  32. uint8_t reserved: 1;
  33. };
  34. uint8_t val;
  35. } pma_cfg;
  36. uint8_t reserved1[3];
  37. uint32_t pma_addr;
  38. } pmp_entry_t;
  39. /**
  40. * @brief PMP Configuration definitions
  41. */
  42. #define READ_EN (1U)
  43. #define READ_DIS (0U)
  44. #define WRITE_EN (1U)
  45. #define WRITE_DIS (0U)
  46. #define EXECUTE_EN (1U)
  47. #define EXECUTE_DIS (0U)
  48. #define ADDR_MATCH_MODE_OFF (0U)
  49. #define ADDR_MATCH_TOR (1U)
  50. #define ADDR_MATCH_NAPOT (3U)
  51. #define REG_LOCK (1U)
  52. #define REG_UNLOCK (0U)
  53. /**
  54. * @brief PMA Configuration definitions
  55. */
  56. #define MEM_TYPE_DEV_NON_BUF (0U)
  57. #define MEM_TYPE_DEV_BUF (1U)
  58. #define MEM_TYPE_MEM_NON_CACHE_NON_BUF (2U)
  59. #define MEM_TYPE_MEM_NON_CACHE_BUF (3U)
  60. #define MEM_TYPE_MEM_WT_NO_ALLOC (4U)
  61. #define MEM_TYPE_MEM_WT_READ_ALLOC (5U)
  62. #define MEM_TYPE_MEM_WB_NO_ALLOC (8U)
  63. #define MEM_TYPE_MEM_WB_READ_ALLOC (9U)
  64. #define MEM_TYPE_MEM_WB_WRITE_ALLOC (10U)
  65. #define MEM_TYPE_MEM_WB_READ_WRITE_ALLOC (11U)
  66. #define MEM_TYPE_EMPTY_HOLE (15U)
  67. #define AMO_EN (0U)
  68. #define AMO_DIS (1U)
  69. /**
  70. * @brief PMP Configuration
  71. * @param r - READ Access control, valid value: READ_EN, READ_DIS
  72. * @param w - Write access control, valid value: WRITE_EN, WRITE_DIS
  73. * @param x - Instruction Execution control, valid value: EXECUTE_EN, EXECUTE_DIS
  74. * @param m - Address matching mode, valid value:
  75. * ADDR_MATCH_MODE_OFF - Null region
  76. * ADDR_MATCH_TOR - Top of range. For pmp_addr0, any address < pmp_addr0 matches, for other regions,
  77. * any address which meets ( pmp_addr[i-1] <= addr < pmp_addr) matches.
  78. * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region, minimal size must be 8 bytes
  79. * @param l - Write lock and permission enforcement bit for Machine mode, valid value: REG_LOCK, REG_UNLOCK
  80. */
  81. #define PMP_CFG(r, w, x, m, l) ((r) | ((w) << 1) | ((x) << 2) | ((m) << 3) | ((l) << 7))
  82. /**
  83. * @brief PMA Configuration
  84. * @param m - Entry address matching mode, valid value:
  85. * ADDR_MATCH_MODE_OFF - This PMA entry is disabled
  86. * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region, the granularity is 4K bytes
  87. * @param t - Memory type attributes, valid value:
  88. * MEM_TYPE_DEV_NON_BUF - Device, Non-bufferable
  89. * MEM_TYPE_DEV_BUF - Device, bufferable
  90. * MEM_TYPE_MEM_NON_CACHE_NON_BUF - Memory, Non-cacheable, Non-bufferable
  91. * MEM_TYPE_MEM_NON_CACHE_BUF - Memory, Non-cacheable, bufferable
  92. * MEM_TYPE_MEM_WT_NO_ALLOC - Memory, Write-through, No-allocate
  93. * MEM_TYPE_MEM_WT_READ_ALLOC - Memory, Write-through, read-allocate
  94. * MEM_TYPE_MEM_WB_NO_ALLOC - Memory, Write-back, No-allocate
  95. * MEM_TYPE_MEM_WB_READ_ALLOC - Memory, Write-back, Read-allocate
  96. * MEM_TYPE_MEM_WB_READ_WRITE_ALLOC - Memory, Write-back, Write-Allocate, Read-Allocate
  97. * MEM_TYPE_EMPTY_HOLE - Empty hole, nothing exists
  98. *
  99. * @param n - Indicate Whether Atomic Memory Operation instructions are not supported in this region, valid value:
  100. * AMO_EN - Atomic Memory Operations are supported
  101. * AMO_DIS - Atomic Memory Operations are not supported
  102. */
  103. #define PMA_CFG(m, t, n) ((m) | ((t) << 2) | ((n) << 6))
  104. /**
  105. * @brief Format Top Address Region
  106. */
  107. #define PMP_TOR_ADDR(addr) ((addr) >> 2)
  108. /**
  109. * @brief Format PMP Natural Aligned Region
  110. * @param x - start address
  111. * @param n - power-of-2 aligned length
  112. */
  113. #define PMP_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | (((uint32_t)(n)-1U) >> 3))
  114. /**
  115. * @brief Format PMA Natural Aligned Region
  116. * @param x - start address
  117. * @param n - power-of-2 aligned length
  118. */
  119. #define PMA_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | ((((uint32_t)(n)-1U) >> 3)))
  120. #ifdef __cplusplus
  121. extern "C" {
  122. #endif
  123. /**
  124. * @brief Write PMP Configuration to corresponding PMP_CFG register
  125. * @param value PMP configuration
  126. * @param idx PMP entry index, valid value is 0-15
  127. */
  128. void write_pmp_cfg(uint32_t value, uint32_t idx);
  129. /**
  130. * @brief Write PMA Configuration to corresponding PMA_CFG register
  131. * @param value PMA configuration
  132. * @param idx PMA entry index, valid value is 0-15
  133. */
  134. void write_pma_cfg(uint32_t value, uint32_t idx);
  135. /**
  136. * @brief Read PMP configuration
  137. * @param idx PMP entry index
  138. * @return PMP configuration
  139. */
  140. uint32_t read_pmp_cfg(uint32_t idx);
  141. /**
  142. * @brief Read PMA configuration
  143. * @param idx PMA entry index
  144. * @return PMA configuration
  145. */
  146. uint32_t read_pma_cfg(uint32_t idx);
  147. /**
  148. * @brief Write PMP address to corresponding PMP_ADDR register
  149. * @param value PMP address
  150. * @param idx PMP address entry index, valid value is 0-15
  151. */
  152. void write_pmp_addr(uint32_t value, uint32_t idx);
  153. /**
  154. * @brief Write PMA address to corresponding PMA_ADDR register
  155. * @param value PMA address
  156. * @param idx PMA address entry index, valid value is 0-15
  157. */
  158. void write_pma_addr(uint32_t value, uint32_t idx);
  159. /**
  160. * @brief Read PMP address entry
  161. * @param idx PMP address entry index
  162. * @return PMP address
  163. */
  164. uint32_t read_pmp_addr(uint32_t idx);
  165. /**
  166. * @brief Read PMA address entry
  167. * @param idx PMA address entry index, valid value is 0-15
  168. * @return PMA address
  169. */
  170. uint32_t read_pma_addr(uint32_t idx);
  171. /**
  172. * @brief Configure PMP and PMA for specified PMP/PMA entry
  173. *
  174. * @param[in] entry PMP entry
  175. * @param entry_index PMP/PMA entry index
  176. * @retval status_invalid_argument Invalid Arguments were detected
  177. * @retval status_success Configuration completed without errors
  178. */
  179. hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index);
  180. /**
  181. * @brief Configure PMP and PMA based on the PMP entry list
  182. * @param entry start of the PMP entry list
  183. * @param num_of_entries Number of entries in the PMP entry list
  184. * @retval status_invalid_argument Invalid Arguments were detected
  185. * @retval status_success Configuration completed without errors
  186. */
  187. hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries);
  188. /**
  189. * @brief Disable PMP and PMA
  190. */
  191. void pmp_disable(void);
  192. #ifdef __cplusplus
  193. }
  194. #endif
  195. #endif /* HPM_PMP_DRV_H */