rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h

/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_CONCTL_H
#define HPM_CONCTL_H

typedef struct {
    __RW uint32_t CTRL0;                       /* 0x0:  */
    __R  uint8_t  RESERVED0[4];                /* 0x4 - 0x7: Reserved */
    __RW uint32_t CTRL2;                       /* 0x8:  */
    __RW uint32_t CTRL3;                       /* 0xC:  */
    __RW uint32_t CTRL4;                       /* 0x10:  */
    __RW uint32_t CTRL5;                       /* 0x14:  */
} CONCTL_Type;


/* Bitfield definition for register: CTRL0 */
/*
 * ENET1_RXCLK_DLY_SEL (RW)
 *
 */
#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK (0xF8000UL)
#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT (15U)
#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK)
#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT)

/*
 * ENET1_TXCLK_DLY_SEL (RW)
 *
 */
#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK (0x7C00U)
#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT (10U)
#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK)
#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT)

/*
 * ENET0_RXCLK_DLY_SEL (RW)
 *
 */
#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U)
#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U)
#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK)
#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT)

/*
 * ENET0_TXCLK_DLY_SEL (RW)
 *
 */
#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU)
#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U)
#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK)
#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT)

/* Bitfield definition for register: CTRL2 */
/*
 * ENET0_LPI_IRQ_EN (RW)
 *
 * ENET0 LPI IRQ Enable
 */
#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL)
#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U)
#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK)
#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT)

/*
 * ENET0_REFCLK_OE (RW)
 *
 */
#define CONCTL_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL)
#define CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT (19U)
#define CONCTL_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK)
#define CONCTL_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT)

/*
 * ENET0_PHY_INTF_SEL (RW)
 *
 * 000:Reserved
 * 001:RGMII
 * 100:RMII
 * 111:Reserved
 */
#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK (0xE000U)
#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT (13U)
#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK)
#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT)

/*
 * ENET0_FLOWCTRL (RW)
 *
 */
#define CONCTL_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U)
#define CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT (12U)
#define CONCTL_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK)
#define CONCTL_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT)

/*
 * ENET0_RMII_TXCLK_SEL (RW)
 *
 * default to use internal clk.
 * set from pad， two option here:
 *   internal 50MHz clock out to pad then in;
 *   use external clock;
 */
#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U)
#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U)
#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK)
#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT)

/* Bitfield definition for register: CTRL3 */
/*
 * ENET1_LPI_IRQ_EN (RW)
 *
 * ENET1 LPI Interrupt Enable
 */
#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK (0x20000000UL)
#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT (29U)
#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK)
#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT)

/*
 * ENET1_REFCLK_OE (RW)
 *
 */
#define CONCTL_CTRL3_ENET1_REFCLK_OE_MASK (0x80000UL)
#define CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT (19U)
#define CONCTL_CTRL3_ENET1_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK)
#define CONCTL_CTRL3_ENET1_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT)

/*
 * ENET1_PHY_INTF_SEL (RW)
 *
 */
#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK (0xE000U)
#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT (13U)
#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK)
#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT)

/*
 * ENET1_FLOWCTRL (RW)
 *
 */
#define CONCTL_CTRL3_ENET1_FLOWCTRL_MASK (0x1000U)
#define CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT (12U)
#define CONCTL_CTRL3_ENET1_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK)
#define CONCTL_CTRL3_ENET1_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT)

/*
 * ENET1_RMII_TXCLK_SEL (RW)
 *
 */
#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK (0x400U)
#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT (10U)
#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK)
#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT)

/* Bitfield definition for register: CTRL4 */
/*
 * SDXC0_SYS_IRQ_EN (RW)
 *
 * system irq enable
 */
#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK (0x80000000UL)
#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT (31U)
#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK)
#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT)

/*
 * SDXC0_WKP_IRQ_EN (RW)
 *
 * wakeup irq enable
 */
#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK (0x40000000UL)
#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT (30U)
#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK)
#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT)

/*
 * SDXC0_CARDCLK_INV_EN (RW)
 *
 * card clock inverter enable
 */
#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK (0x10000000UL)
#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT (28U)
#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK)
#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT)

/*
 * SDXC0_GPR_TUNING_CARD_CLK_SEL (RW)
 *
 * for card clock DLL, default 0
 */
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT)

/*
 * SDXC0_GPR_TUNING_STROBE_SEL (RW)
 *
 * for strobe DLL, default 7taps(1ns)
 */
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT (18U)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK)
#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT)

/*
 * SDXC0_GPR_STROBE_IN_ENABLE (RW)
 *
 * enable strobe clock, maybe used when update strobe DLL
 */
#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK (0x20000UL)
#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT (17U)
#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK)
#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT)

/*
 * SDXC0_GPR_CCLK_RX_DLY_SW_SEL (RW)
 *
 */
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)

/*
 * SDXC0_GPR_CCLK_RX_DLY_SW_FORCE (RW)
 *
 * force use sw DLL config
 */
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)

/* Bitfield definition for register: CTRL5 */
/*
 * SDXC1_SYS_IRQ_EN (RW)
 *
 * system irq enable
 */
#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK (0x80000000UL)
#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT (31U)
#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK)
#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT)

/*
 * SDXC1_WKP_IRQ_EN (RW)
 *
 * wakeup irq enable
 */
#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK (0x40000000UL)
#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT (30U)
#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK)
#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT)

/*
 * SDXC1_CARDCLK_INV_EN (RW)
 *
 * card clock inverter enable
 */
#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK (0x10000000UL)
#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT (28U)
#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK)
#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT)

/*
 * SDXC1_GPR_TUNING_CARD_CLK_SEL (RW)
 *
 */
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT)

/*
 * SDXC1_GPR_TUNING_STROBE_SEL (RW)
 *
 */
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT (18U)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK)
#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT)

/*
 * SDXC1_GPR_STROBE_IN_ENABLE (RW)
 *
 */
#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK (0x20000UL)
#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT (17U)
#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK)
#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT)

/*
 * SDXC1_GPR_CCLK_RX_DLY_SW_SEL (RW)
 *
 */
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)

/*
 * SDXC1_GPR_CCLK_RX_DLY_SW_FORCE (RW)
 *
 */
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)




#endif /* HPM_CONCTL_H */