link.sct 3.1 KB

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  1. #! armcc -E
  2. /*
  3. ** ###################################################################
  4. ** Processors: MIMXRT1052CVJ5B
  5. ** MIMXRT1052CVL5B
  6. ** MIMXRT1052DVJ6B
  7. ** MIMXRT1052DVL6B
  8. **
  9. ** Compiler: Keil ARM C/C++ Compiler
  10. ** Reference manual: IMXRT1050RM Rev.1, 03/2018
  11. ** Version: rev. 1.0, 2018-09-21
  12. ** Build: b180921
  13. **
  14. ** Abstract:
  15. ** Linker file for the Keil ARM C/C++ Compiler
  16. **
  17. ** Copyright 2016 Freescale Semiconductor, Inc.
  18. ** Copyright 2016-2018 NXP
  19. ** All rights reserved.
  20. **
  21. ** SPDX-License-Identifier: BSD-3-Clause
  22. **
  23. ** http: www.nxp.com
  24. ** mail: support@nxp.com
  25. **
  26. ** ###################################################################
  27. */
  28. #define m_flash_config_start 0x60000000
  29. #define m_flash_config_size 0x00001000
  30. #define m_ivt_start 0x60001000
  31. #define m_ivt_size 0x00001000
  32. #define m_interrupts_start 0x60002000
  33. #define m_interrupts_size 0x00000400
  34. #define m_text_start 0x60002400
  35. #define m_text_size 0x01FFDC00
  36. #define m_data_start 0x20000000
  37. #define m_data_size 0x00020000
  38. #define m_data2_start 0x20200000
  39. #define m_data2_size 0x00040000
  40. /* Sizes */
  41. #if (defined(__stack_size__))
  42. #define Stack_Size __stack_size__
  43. #else
  44. #define Stack_Size 0x0400
  45. #endif
  46. #if (defined(__heap_size__))
  47. #define Heap_Size __heap_size__
  48. #else
  49. #define Heap_Size 0x0400
  50. #endif
  51. #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
  52. #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
  53. LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
  54. RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
  55. * (.boot_hdr.conf, +FIRST)
  56. }
  57. RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
  58. * (.boot_hdr.ivt, +FIRST)
  59. * (.boot_hdr.boot_data)
  60. * (.boot_hdr.dcd_data)
  61. }
  62. #else
  63. LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
  64. #endif
  65. VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
  66. * (RESET,+FIRST)
  67. }
  68. ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
  69. * (InRoot$$Sections)
  70. .ANY (+RO)
  71. }
  72. RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
  73. .ANY (+RW +ZI)
  74. * (NonCacheable.init)
  75. * (NonCacheable)
  76. }
  77. ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
  78. }
  79. ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
  80. RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
  81. }