drv_spi.c 6.9 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-15 Magicoe The first version for LPC55S6x
  9. */
  10. #include "rtdevice.h"
  11. #include "fsl_common.h"
  12. #include "fsl_iocon.h"
  13. #include "fsl_spi.h"
  14. #include "fsl_spi_dma.h"
  15. enum
  16. {
  17. #ifdef BSP_USING_SPI3
  18. SPI3_INDEX,
  19. #endif
  20. #ifdef BSP_USING_SPI8
  21. SPI8_INDEX,
  22. #endif
  23. };
  24. struct lpc_spi
  25. {
  26. struct rt_spi_bus parent;
  27. SPI_Type *SPIx;
  28. clock_attach_id_t clock_attach_id;
  29. clock_ip_name_t clock_name;
  30. DMA_Type *DMAx;
  31. uint8_t tx_dma_chl;
  32. uint8_t rx_dma_chl;
  33. dma_handle_t dma_tx_handle;
  34. dma_handle_t dma_rx_handle;
  35. spi_dma_handle_t spi_dma_handle;
  36. rt_sem_t sem;
  37. char *device_name;
  38. };
  39. static struct lpc_spi lpc_obj[] =
  40. {
  41. #ifdef BSP_USING_SPI3
  42. {
  43. .SPIx = SPI3,
  44. .clock_attach_id = kMAIN_CLK_to_FLEXCOMM3,
  45. .clock_name = kCLOCK_FlexComm3,
  46. .device_name = "spi3",
  47. .DMAx = DMA0,
  48. .tx_dma_chl = 9,
  49. .rx_dma_chl = 8,
  50. },
  51. #endif
  52. #ifdef BSP_USING_SPI8
  53. {
  54. .SPIx = SPI8,
  55. .clock_attach_id = kMAIN_CLK_to_HSLSPI,
  56. .clock_name = kCLOCK_Hs_Lspi,
  57. .device_name = "spi8",
  58. .DMAx = DMA0,
  59. .tx_dma_chl = 3,
  60. .rx_dma_chl = 2,
  61. },
  62. #endif
  63. };
  64. static uint32_t lpc_get_spi_freq(SPI_Type *base)
  65. {
  66. uint32_t freq = 0;
  67. if(base == SPI3)
  68. {
  69. freq = CLOCK_GetFlexCommClkFreq(kCLOCK_FlexComm3);
  70. }
  71. if(base == SPI8)
  72. {
  73. freq = CLOCK_GetFlexCommClkFreq(kCLOCK_Hs_Lspi);
  74. }
  75. return freq;
  76. }
  77. static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
  78. {
  79. spi_master_config_t masterConfig = {0};
  80. SPI_MasterGetDefaultConfig(&masterConfig);
  81. if(cfg->data_width != 8 && cfg->data_width != 16)
  82. {
  83. cfg->data_width = 8;
  84. }
  85. masterConfig.baudRate_Bps = cfg->max_hz;
  86. if(cfg->data_width == 8)
  87. {
  88. masterConfig.dataWidth = kSPI_Data8Bits;
  89. }
  90. else if(cfg->data_width == 16)
  91. {
  92. masterConfig.dataWidth = kSPI_Data16Bits;
  93. }
  94. if(cfg->mode & RT_SPI_MSB)
  95. {
  96. masterConfig.direction = kSPI_MsbFirst;
  97. }
  98. else
  99. {
  100. masterConfig.direction = kSPI_LsbFirst;
  101. }
  102. if(cfg->mode & RT_SPI_CPHA)
  103. {
  104. masterConfig.phase = kSPI_ClockPhaseSecondEdge;
  105. }
  106. else
  107. {
  108. masterConfig.phase = kSPI_ClockPhaseFirstEdge;
  109. }
  110. if(cfg->mode & RT_SPI_CPOL)
  111. {
  112. masterConfig.polarity = kSPI_ClockPolarityActiveLow;
  113. }
  114. else
  115. {
  116. masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
  117. }
  118. SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base));
  119. return RT_EOK;
  120. }
  121. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  122. {
  123. rt_err_t ret = RT_EOK;
  124. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  125. ret = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  126. return ret;
  127. }
  128. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  129. {
  130. rt_err_t ret = RT_EOK;
  131. struct lpc_spi *spi = rt_container_of(device->bus, struct lpc_spi, parent);
  132. ret = lpc_spi_init(spi->SPIx, cfg);
  133. return ret;
  134. }
  135. static void SPI_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
  136. {
  137. struct lpc_spi *spi = (struct lpc_spi*)userData;
  138. rt_sem_release(spi->sem);
  139. }
  140. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  141. {
  142. int i;
  143. spi_transfer_t transfer = {0};
  144. RT_ASSERT(device != RT_NULL);
  145. RT_ASSERT(device->bus != RT_NULL);
  146. struct lpc_spi *spi = rt_container_of(device->bus, struct lpc_spi, parent);
  147. if(message->cs_take && (device->cs_pin != PIN_NONE))
  148. {
  149. rt_pin_write(device->cs_pin, PIN_LOW);
  150. }
  151. transfer.dataSize = message->length;
  152. transfer.rxData = (uint8_t *)(message->recv_buf);
  153. transfer.txData = (uint8_t *)(message->send_buf);
  154. transfer.configFlags = kSPI_FrameAssert;
  155. // if(message->length < MAX_DMA_TRANSFER_SIZE)
  156. if(0)
  157. {
  158. SPI_MasterTransferBlocking(spi->SPIx, &transfer);
  159. }
  160. else
  161. {
  162. uint32_t block, remain;
  163. block = message->length / DMA_MAX_TRANSFER_COUNT;
  164. remain = message->length % DMA_MAX_TRANSFER_COUNT;
  165. for(i=0; i<block; i++)
  166. {
  167. transfer.dataSize = DMA_MAX_TRANSFER_COUNT;
  168. if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
  169. if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
  170. SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
  171. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  172. }
  173. if(remain)
  174. {
  175. transfer.dataSize = remain;
  176. if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
  177. if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
  178. SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
  179. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  180. }
  181. }
  182. if(message->cs_release && (device->cs_pin != PIN_NONE))
  183. {
  184. rt_pin_write(device->cs_pin, PIN_HIGH);
  185. }
  186. return message->length;
  187. }
  188. static struct rt_spi_ops lpc_spi_ops =
  189. {
  190. .configure = spi_configure,
  191. .xfer = spixfer
  192. };
  193. int rt_hw_spi_init(void)
  194. {
  195. int i;
  196. for(i=0; i<ARRAY_SIZE(lpc_obj); i++)
  197. {
  198. CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
  199. lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
  200. lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
  201. DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  202. DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  203. DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, kDMA_ChannelPriority3);
  204. DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, kDMA_ChannelPriority2);
  205. DMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  206. DMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  207. SPI_MasterTransferCreateHandleDMA(lpc_obj[i].SPIx, &lpc_obj[i].spi_dma_handle, SPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_tx_handle, &lpc_obj[i].dma_rx_handle);
  208. rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].device_name, &lpc_spi_ops);
  209. }
  210. return RT_EOK;
  211. }
  212. INIT_DEVICE_EXPORT(rt_hw_spi_init);