cpu.c 1.5 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2011-09-15 Bernard first version
  9. * 2019-07-28 zdzn add smp support
  10. */
  11. #include <rthw.h>
  12. #include <rtthread.h>
  13. #include <board.h>
  14. #include "cp15.h"
  15. int rt_hw_cpu_id(void)
  16. {
  17. int cpu_id;
  18. __asm__ volatile (
  19. "mrc p15, 0, %0, c0, c0, 5"
  20. :"=r"(cpu_id)
  21. );
  22. cpu_id &= 0xf;
  23. return cpu_id;
  24. };
  25. #ifdef RT_USING_SMP
  26. void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
  27. {
  28. lock->slock = 0;
  29. }
  30. void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
  31. {
  32. unsigned long tmp;
  33. unsigned long newval;
  34. rt_hw_spinlock_t lockval;
  35. __asm__ __volatile__(
  36. "pld [%0]"
  37. ::"r"(&lock->slock)
  38. );
  39. __asm__ __volatile__(
  40. "1: ldrex %0, [%3]\n"
  41. " add %1, %0, %4\n"
  42. " strex %2, %1, [%3]\n"
  43. " teq %2, #0\n"
  44. " bne 1b"
  45. : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
  46. : "r" (&lock->slock), "I" (1 << 16)
  47. : "cc");
  48. while (lockval.tickets.next != lockval.tickets.owner)
  49. {
  50. __WFE();
  51. lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
  52. }
  53. __DMB();
  54. }
  55. void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
  56. {
  57. __DMB();
  58. lock->tickets.owner++;
  59. __DSB();
  60. __SEV();
  61. }
  62. #endif /*RT_USING_SMP*/
  63. /**
  64. * @addtogroup ARM CPU
  65. */
  66. /*@{*/
  67. /*@}*/