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bsp
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raspberry-pi
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raspi4-32
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driver
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drv_uart.h

drv_uart.h 4.9 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2006-2021, RT-Thread Development Team
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  *
    6. 

  6.  * Change Logs:
    7. 

  7.  * Date           Author         Notes
    8. 

  8.  * 2020-04-16     bigmagic       first version
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef DRV_UART_H__
    12. 

  12. #define DRV_UART_H__
    13. 

  13. 

  14. // register's bit
    15. 

  15. #define PL011_FR_RI          (1 << 8)
    16. 

  16. #define PL011_FR_TXFE        (1 << 7)
    17. 

  17. #define PL011_FR_RXFF        (1 << 6)
    18. 

  18. #define PL011_FR_TXFF        (1 << 5)
    19. 

  19. #define PL011_FR_RXFE        (1 << 4)
    20. 

  20. #define PL011_FR_BUSY        (1 << 3)
    21. 

  21. #define PL011_FR_DCD         (1 << 2)
    22. 

  22. #define PL011_FR_DSR         (1 << 1)
    23. 

  23. #define PL011_FR_CTS         (1 << 0)
    24. 

  24. 

  25. #define PL011_LCRH_SPS       (1 << 7)
    26. 

  26. #define PL011_LCRH_WLEN_8    (3 << 5)
    27. 

  27. #define PL011_LCRH_WLEN_7    (2 << 5)
    28. 

  28. #define PL011_LCRH_WLEN_6    (1 << 5)
    29. 

  29. #define PL011_LCRH_WLEN_5    (0 << 5)
    30. 

  30. #define PL011_LCRH_FEN       (1 << 4)
    31. 

  31. #define PL011_LCRH_STP2      (1 << 3)
    32. 

  32. #define PL011_LCRH_EPS       (1 << 2)
    33. 

  33. #define PL011_LCRH_PEN       (1 << 1)
    34. 

  34. #define PL011_LCRH_BRK       (1 << 0)
    35. 

  35. 

  36. #define PL011_CR_CTSEN       (1 << 15)
    37. 

  37. #define PL011_CR_RTSEN       (1 << 14)
    38. 

  38. #define PL011_CR_RTS         (1 << 11)
    39. 

  39. #define PL011_CR_DTR         (1 << 10)
    40. 

  40. #define PL011_CR_RXE         (1 << 9)
    41. 

  41. #define PL011_CR_TXE         (1 << 8)
    42. 

  42. #define PL011_CR_LBE         (1 << 7)
    43. 

  43. #define PL011_CR_SIRLP       (1 << 2)
    44. 

  44. #define PL011_CR_SIREN       (1 << 1)
    45. 

  45. #define PL011_CR_UARTEN      (1 << 0)
    46. 

  46. 

  47. #define PL011_IMSC_TXIM      (1 << 5)
    48. 

  48. #define PL011_IMSC_RXIM      (1 << 4)
    49. 

  49. 

  50. #define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
    51. 

  51. #define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
    52. 

  52. #define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
    53. 

  53. #define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
    54. 

  54. #define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
    55. 

  55. #define PL011_INTERRUPT_TRANSMIT        (1 << 5)
    56. 

  56. #define PL011_INTERRUPT_RECEIVE         (1 << 4)
    57. 

  57. #define PL011_INTERRUPT_nUARTCTS        (1 << 1)
    58. 

  58. 

  59. #define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
    60. 

  60. #define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
    61. 

  61. #define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
    62. 

  62. #define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
    63. 

  63. #define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
    64. 

  64. #define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
    65. 

  65. #define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
    66. 

  66. #define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
    67. 

  67. #define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
    68. 

  68. #define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
    69. 

  69. #define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
    70. 

  70. #define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
    71. 

  71. #define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
    72. 

  72. #define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
    73. 

  73. #define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
    74. 

  74. #define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
    75. 

  75. #define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
    76. 

  76. #define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
    77. 

  77. #define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
    78. 

  78. #define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
    79. 

  79. #define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
    80. 

  80. 

  81. /*
    82. 

  82.  *  Auxiliary
    83. 

  83.  */
    84. 

  84. #define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
    85. 

  85. #define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
    86. 

  86. #define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
    87. 

  87. #define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
    88. 

  88. #define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
    89. 

  89. #define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
    90. 

  90. #define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
    91. 

  91. #define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
    92. 

  92. #define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
    93. 

  93. #define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
    94. 

  94. #define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
    95. 

  95. #define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
    96. 

  96. #define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
    97. 

  97. #define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
    98. 

  98. #define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
    99. 

  99. #define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
    100. 

  100. #define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
    101. 

  101. #define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
    102. 

  102. #define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
    103. 

  103. #define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
    104. 

  104. 

  105. int rt_hw_uart_init(void);
    106. 

  106. 

  107. #endif /* DRV_UART_H__ */
    108.