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@@ -53,24 +53,6 @@
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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#endif /* PHY_USING_LAN8720A */
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-#ifdef PHY_USING_LAN8742A
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-/* The PHY interrupt source flag register. */
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-#define PHY_INTERRUPT_FLAG_REG 0x1DU
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-/* The PHY interrupt mask register. */
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-#define PHY_INTERRUPT_MASK_REG 0x1EU
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-#define PHY_LINK_DOWN_MASK (1<<4)
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-#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
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-
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-/* The PHY status register. */
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-#define PHY_Status_REG 0x1FU
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-#define PHY_10M_MASK (1<<2)
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-#define PHY_100M_MASK (1<<3)
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-#define PHY_FULL_DUPLEX_MASK (1<<4)
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-#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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-#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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-#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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-#endif /* PHY_USING_LAN8742A */
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-
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#ifdef PHY_USING_DM9161CEP
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#define PHY_Status_REG 0x11U
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#define PHY_10M_MASK ((1<<12) || (1<<13))
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@@ -107,4 +89,22 @@
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#define PHY_INT_MASK (1<<5)
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#endif /* PHY_USING_DP83848C */
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+#ifdef PHY_USING_LAN8742A
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+/* The PHY interrupt source flag register. */
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+#define PHY_INTERRUPT_FLAG_REG 0x1DU
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+/* The PHY interrupt mask register. */
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+#define PHY_INTERRUPT_MASK_REG 0x1EU
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+#define PHY_LINK_DOWN_MASK (1<<4)
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+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
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+
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+/* The PHY status register. */
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+#define PHY_Status_REG 0x1FU
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+#define PHY_10M_MASK (1<<2)
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+#define PHY_100M_MASK (1<<3)
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+#define PHY_FULL_DUPLEX_MASK (1<<4)
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+#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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+#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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+#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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+#endif /* PHY_USING_LAN8742A */
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+
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#endif /* __DRV_ETH_H__ */
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