add LPC4330 BSP based on NGX xplorer development board

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/xplorer4330/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/applications/application.c

@@ -0,0 +1,62 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+
+#ifdef RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+#include "board_ngx_xplorer_18304330.h"
+
+static void rt_init_thread_entry(void *parameter)
+{
+    Board_LED_Init();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+    while (1)
+    {
+        Board_LED_Set(0, 1);
+        rt_thread_delay(50);
+        Board_LED_Set(0, 0);
+        rt_thread_delay(50);
+    }
+}
+
+void rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry,
+                           RT_NULL,
+                           2048,
+                           RT_THREAD_PRIORITY_MAX / 3,
+                           20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+}
+
+/*@}*/

bsp/xplorer4330/applications/startup.c

@@ -0,0 +1,91 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2012-12-11     lgnq         modified for LPC4330
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "platform.h"
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define LPC4300_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define LPC4300_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define LPC4300_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128));
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+#ifdef RT_USING_DEVICE
+    /* init all device */
+    rt_device_init_all();
+#endif
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/xplorer4330/drivers/SConscript

@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_SERIAL') == False:
+    SrcRemove(src, 'usart.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/drivers/platform.c

@@ -0,0 +1,64 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-13     lgnq         first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "cmsis.h"
+
+#ifdef RT_USING_SERIAL
+#include "usart.h"
+#endif
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initialize the LPC4330 Xplorer board.
+ */
+void rt_hw_board_init(void)
+{
+    Board_Init();
+
+    /* Configure the SysTick - Generate interrupt @ 100 Hz*/
+    SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100);
+
+#ifdef RT_USING_SERIAL
+    rt_hw_serial_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#endif
+}
+
+/*@}*/

bsp/xplorer4330/drivers/platform.h

@@ -0,0 +1,19 @@
+/*
+ * File      : platform.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+void rt_hw_board_init(void);
+
+#endif

bsp/xplorer4330/drivers/usart.c

@@ -0,0 +1,394 @@
+/*
+ * File      : usart.c
+ * mb9bf506r uart driver
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-30     lgnq         first  version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "usart.h"
+#include "uart_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct serial_ringbuffer uart0_int_rx;
+struct uart_device uart0 =
+{
+    LPC_USART0,
+    USART0_IRQn,
+};
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART0);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial0);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART1)
+/* UART1 device driver structure */
+struct serial_ringbuffer uart1_int_rx;
+struct uart_device uart1 =
+{
+    LPC_UART1,
+    USART1_IRQn,
+};
+struct rt_serial_device serial1;
+
+void UART1_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_UART1);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial1);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART2)
+/* UART2 device driver structure */
+struct serial_ringbuffer uart2_int_rx;
+struct uart_device uart2 =
+{
+    LPC_USART2,
+    USART2_IRQn,
+};
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART2);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial2);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART3)
+/* UART3 device driver structure */
+struct serial_ringbuffer uart3_int_rx;
+struct uart_device uart3 =
+{
+    LPC_USART3,
+    USART3_IRQn,
+};
+struct rt_serial_device serial3;
+
+void UART3_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART3);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial3);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+void uart_pin_setup(void)
+{
+#if defined(RT_USING_UART0)
+    Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);                   /* P6.5 : UART0_TXD */
+    Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);  /* P6.4 : UART0_RXD */
+#endif
+
+#if defined(RT_USING_UART1)
+    Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);                  /* P1.13 : UART1_TXD */
+    Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P1.14 : UART1_RX */
+#endif
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct uart_device *uart;
+    UART_DATABIT_Type   databit;
+    UART_STOPBIT_Type   stopbit;
+    UART_PARITY_Type    parity;
+
+    /* UART FIFO configuration Struct variable */
+    UART_FIFO_CFG_Type UARTFIFOConfigStruct;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    Chip_UART_Init(uart->uart_regs);
+
+    Chip_UART_SetBaud(uart->uart_regs, cfg->baud_rate);
+
+    /* set stop bits */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        stopbit = UART_STOPBIT_1;
+        break;
+    case STOP_BITS_2:
+        stopbit = UART_STOPBIT_2;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    /* set data bits */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        databit = UART_DATABIT_5;
+        break;
+    case DATA_BITS_6:
+        databit = UART_DATABIT_6;
+        break;
+    case DATA_BITS_7:
+        databit = UART_DATABIT_7;
+        break;
+    case DATA_BITS_8:
+        databit = UART_DATABIT_8;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    /* set parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        parity = UART_PARITY_NONE;
+        break;
+    case PARITY_EVEN:
+        parity = UART_PARITY_EVEN;
+        break;
+    case PARITY_ODD:
+        parity = UART_PARITY_ODD;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    Chip_UART_ConfigData(uart->uart_regs, databit, parity, stopbit);
+
+    /* Enable UART Transmit */
+    Chip_UART_TxCmd(uart->uart_regs, ENABLE);
+
+    Chip_UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
+
+    /* Enable DMA mode in UART */
+    UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE;
+    /* Initialize FIFO for UART0 peripheral */
+    Chip_UART_FIFOConfig(uart->uart_regs, &UARTFIFOConfigStruct);
+
+    /* Enable UART Rx interrupt */
+    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RBR, ENABLE);
+    /* Enable UART line status interrupt */
+    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RLS, ENABLE);
+
+    /* Enable Interrupt for UART channel */
+    /* Priority = 1 */
+    NVIC_SetPriority(uart->irq_num, 1);
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_DISABLE_IRQ(uart->irq_num);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ENABLE_IRQ(uart->irq_num);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    /* wait send buffer is empty */
+    while (!(uart->uart_regs->LSR & UART_LSR_THRE))
+        ;
+    /* write to send buffer */
+    uart->uart_regs->THR = c & UART_THR_MASKBIT;
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    struct uart_device *uart;
+    uint8_t ch;
+
+    RT_ASSERT(serial != RT_NULL);
+    
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    /* receive buffer is full */
+    if (uart->uart_regs->LSR & UART_LSR_RDR)
+    {
+        ch = uart->uart_regs->RBR & UART_RBR_MASKBIT;
+
+        return (ch);
+    }
+    else
+        return (-1);
+}
+
+static struct rt_uart_ops uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+void rt_hw_serial_init(void)
+{
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+
+    uart_pin_setup();
+
+#if defined(RT_USING_UART0)
+    serial0.ops    = &uart_ops;
+    serial0.int_rx = &uart0_int_rx;
+    serial0.config = config;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+#endif
+
+#if defined(RT_USING_UART1)
+    serial1.ops    = &uart_ops;
+    serial1.int_rx = &uart1_int_rx;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart1);
+#endif
+
+#if defined(RT_USING_UART2)
+    serial2.ops    = &uart_ops;
+    serial2.int_rx = &uart2_int_rx;
+    serial2.config = config;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2,
+                          "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart2);
+#endif
+
+#if defined(RT_USING_UART3)
+    serial3.ops    = &uart_ops;
+    serial3.int_rx = &uart3_int_rx;
+    serial3.config = config;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3,
+                          "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart3);
+#endif
+}

bsp/xplorer4330/drivers/usart.h

@@ -0,0 +1,39 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rtthread.h>
+
+#include "chip_lpc43xx.h"
+#include "cmsis.h"
+
+/**
+ *  Enable/DISABLE Interrupt Controller
+ */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct uart_device
+{
+    LPC_USART_Type *uart_regs;
+
+    /* irq number */
+    IRQn_Type irq_num;
+};
+
+void rt_hw_serial_init(void);
+
+#endif

bsp/xplorer4330/libraries/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/xplorer4330/libraries/lpc_board/SConscript

@@ -0,0 +1,44 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+#src = Glob('board_common/*.c')
+src  = []
+path = [cwd + '/board_common']
+
+if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330']
+elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850']
+
+group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_board/board_common/Retarget.c

@@ -0,0 +1,253 @@
+/*
+ * @brief	IO redirection support
+ *
+ * This file adds re-direction support to the library for various
+ * projects. It can be configured in one of 3 ways - no redirection,
+ * redirection via a UART, or redirection via semihosting. If DEBUG
+ * is not defined, all printf statements will do nothing with the
+ * output being throw away. If DEBUG is defined, then the choice of
+ * output is selected by the DEBUG_SEMIHOSTING define. If the
+ * DEBUG_SEMIHOSTING is not defined, then output is redirected via
+ * the UART. If DEBUG_SEMIHOSTING is defined, then output will be
+ * attempted to be redirected via semihosting. If the UART method
+ * is used, then the Board_UARTPutChar and Board_UARTGetChar
+ * functions must be defined to be used by this driver and the UART
+ * must already be initialized to the correct settings.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "sys_config.h"
+#include "board.h"
+
+/* Keil (Realview) support */
+#if defined(__CC_ARM)
+
+#include <stdio.h>
+#include <rt_misc.h>
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#define ITM_Port8(n)    (*((volatile unsigned char *) (0xE0000000 + 4 * n)))
+#define ITM_Port16(n)   (*((volatile unsigned short *) (0xE0000000 + 4 * n)))
+#define ITM_Port32(n)   (*((volatile unsigned long *) (0xE0000000 + 4 * n)))
+
+#define DEMCR           (*((volatile unsigned long *) (0xE000EDFC)))
+#define TRCENA          0x01000000
+
+/* Write to SWO */
+void _ttywrch(int ch)
+{
+	if (DEMCR & TRCENA) {
+		while (ITM_Port32(0) == 0) {}
+		ITM_Port8(0) = ch;
+	}
+}
+
+#else
+static INLINE void BoardOutChar(char ch)
+{
+	Board_UARTPutChar(ch);
+}
+
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+struct __FILE {
+	int handle;
+};
+
+FILE __stdout;
+FILE __stdin;
+FILE __stderr;
+
+void *_sys_open(const char *name, int openmode)
+{
+	return 0;
+}
+
+int fputc(int c, FILE *f)
+{
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+	_ttywrch(c);
+#else
+	BoardOutChar((char) c);
+#endif
+#endif
+	return 0;
+}
+
+int fgetc(FILE *f)
+{
+#if defined(DEBUG) && !defined(DEBUG_SEMIHOSTING)
+	return Board_UARTGetChar();
+#else
+	return 0;
+#endif
+}
+
+int ferror(FILE *f)
+{
+	return EOF;
+}
+
+void _sys_exit(int return_code)
+{
+label:  goto label;	/* endless loop */
+}
+
+#endif /* defined (__CC_ARM) */
+
+/* IAR support */
+#if defined(__ICCARM__)
+/*******************
+ *
+ * Copyright 1998-2003 IAR Systems.  All rights reserved.
+ *
+ * $Revision: 30870 $
+ *
+ * This is a template implementation of the "__write" function used by
+ * the standard library.  Replace it with a system-specific
+ * implementation.
+ *
+ * The "__write" function should output "size" number of bytes from
+ * "buffer" in some application-specific way.  It should return the
+ * number of characters written, or _LLIO_ERROR on failure.
+ *
+ * If "buffer" is zero then __write should perform flushing of
+ * internal buffers, if any.  In this case "handle" can be -1 to
+ * indicate that all handles should be flushed.
+ *
+ * The template implementation below assumes that the application
+ * provides the function "MyLowLevelPutchar".  It should return the
+ * character written, or -1 on failure.
+ *
+ ********************/
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__write"
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#error Semihosting support not yet working on IAR
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+/*
+   If the __write implementation uses internal buffering, uncomment
+   the following line to ensure that we are called with "buffer" as 0
+   (i.e. flush) when the application terminates. */
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+#if defined(DEBUG)
+	size_t nChars = 0;
+
+	if (buffer == 0) {
+		/*
+		   This means that we should flush internal buffers.  Since we
+		   don't we just return.  (Remember, "handle" == -1 means that all
+		   handles should be flushed.)
+		 */
+		return 0;
+	}
+
+	/* This template only writes to "standard out" and "standard err",
+	   for all other file handles it returns failure. */
+	if (( handle != _LLIO_STDOUT) && ( handle != _LLIO_STDERR) ) {
+		return _LLIO_ERROR;
+	}
+
+	for ( /* Empty */; size != 0; --size) {
+		Board_UARTPutChar(*buffer++);
+		++nChars;
+	}
+
+	return nChars;
+#else
+	return size;
+#endif /* defined(DEBUG) */
+}
+
+_STD_END
+
+#endif /* defined (__ICCARM__) */
+
+#if defined( __GNUC__ )
+/* Include stdio.h to pull in __REDLIB_INTERFACE_VERSION__ */
+#include <stdio.h>
+
+#if (__REDLIB_INTERFACE_VERSION__ >= 20000)
+/* We are using new Redlib_v2 semihosting interface */
+	#define WRITEFUNC __sys_write
+	#define READFUNC __sys_readc
+#else
+/* We are using original Redlib semihosting interface */
+	#define WRITEFUNC __write
+	#define READFUNC __readc
+#endif
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+/* Do nothing, semihosting is enabled by default in LPCXpresso */
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+#if !defined(DEBUG_SEMIHOSTING)
+int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength)
+{
+#if defined(DEBUG)
+	unsigned int i;
+	for (i = 0; i < iLength; i++) {
+		Board_UARTPutChar(pcBuffer[i]);
+	}
+#endif
+
+	return iLength;
+}
+
+/* Called by bottom level of scanf routine within RedLib C library to read
+   a character. With the default semihosting stub, this would read the character
+   from the debugger console window (which acts as stdin). But this version reads
+   the character from the LPC1768/RDB1768 UART. */
+int READFUNC(void)
+{
+#if defined(DEBUG)
+	char c = Board_UARTGetChar();
+	return (int) c;
+
+#else
+	return (int) -1;
+#endif
+}
+
+#endif /* !defined(DEBUG_SEMIHOSTING) */
+#endif /* defined ( __GNUC__ ) */

bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h

@@ -0,0 +1,176 @@
+/*
+ * @brief Common board API functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_API_H_
+#define __BOARD_API_H_
+
+#include "lpc_types.h"
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_COMMON_API BOARD: Common board functions
+ * @ingroup BOARD_Common
+ * This file contains common board definitions that are shared across
+ * boards and devices. All of these functions do not need to be
+ * impemented for a specific board, but if they are implemented, they
+ * should use this API standard.
+ * @{
+ */
+
+/**
+ * @brief	Set up and initialize all required blocks and functions related to the board hardware.
+ * @return	None
+ */
+void Board_Init(void);
+
+/**
+ * @brief	Initializes board UART for output, required for printf redirection
+ * @return	None
+ */
+void Board_Debug_Init(void);
+
+/**
+ * @brief	Sends a single character on the UART, required for printf redirection
+ * @param	ch	: character to send
+ * @return	None
+ */
+void Board_UARTPutChar(char ch);
+
+/**
+ * @brief	Get a single character from the UART, required for scanf input
+ * @return	EOF if not character was received, or character value
+ */
+int Board_UARTGetChar(void);
+
+/**
+ * @brief	Prints a string to the UART
+ * @param	str	: Terminated string to output
+ * @return	None
+ */
+void Board_UARTPutSTR(char *str);
+
+/**
+ * @brief	Initializes board LED(s)
+ * @return	None
+ */
+void Board_LED_Init(void);
+
+/**
+ * @brief	Sets the state of a board LED to on or off
+ * @param	LEDNumber	: LED number to set state for
+ * @param	State		: true for on, false for off
+ * @return	None
+ */
+void Board_LED_Set(uint8_t LEDNumber, bool State);
+
+/**
+ * @brief	Returns the current state of a board LED
+ * @param	LEDNumber	: LED number to set state for
+ * @return	true if the LED is on, otherwise false
+ */
+bool Board_LED_Test(uint8_t LEDNumber);
+
+/**
+ * @brief	Toggles the current state of a board LED
+ * @param	LEDNumber	: LED number to change state for
+ * @return	None
+ */
+STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
+{
+	Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
+}
+
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Turn on Board LCD Backlight
+ * @param	Intensity	: Backlight intensity (0 = off, >=1 = on)
+ * @return	None
+ * On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
+ * value will turn off or on the backlight. On some boards, a non-0 value will
+ * control backlight intensity via a PWN. For PWM systems, the intensity value
+ * is a percentage value between 0 and 100%.
+ */
+void Board_LCD_Set_Backlight(uint8_t Intensity);
+
+/**
+ * @brief Function prototype for a MS delay function. Board layers or example code may
+ *        define this function as needed.
+ */
+typedef void (*p_msDelay_func_t)(uint32_t);
+
+/* The DEBUG* functions are selected based on system configuration.
+   Code that uses the DEBUG* functions will have their I/O routed to
+   the UART, semihosting, or nowhere. */
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#define DEBUGINIT()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) printf(str)
+#define DEBUGIN() (int) EOF
+
+#else
+#define DEBUGINIT() Board_Debug_Init()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) Board_UARTPutSTR(str)
+#define DEBUGIN() Board_UARTGetChar()
+#endif /* defined(DEBUG_SEMIHOSTING) */
+
+#else
+#define DEBUGINIT()
+#define DEBUGOUT(...)
+#define DEBUGSTR(str)
+#define DEBUGIN() (int) EOF
+#endif /* defined(DEBUG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_API_H_ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h

@@ -0,0 +1,90 @@
+/*
+ * @brief Common PHY functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_PHY_H_
+#define __LPC_PHY_H_
+
+#include "board.h"
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
+ * @ingroup BOARD_Common
+ * The simple PHY function API provides simple non-blocking PHY status
+ * monitoring and initialization support for various Ethernet PHYs.
+ * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
+ * several standard functions from the MAC driver for interfacing to the
+ * PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(),
+ * Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()).
+ *
+ * Once initialized, just preiodically call the lpcPHYStsPoll() function
+ * from the background loop or a thread and monitor the returned status
+ * to determine if the PHY state has changed and the current PHY state.
+ * @{
+ */
+#define PHY_LINK_ERROR     (1 << 0)	/*!< PHY status bit for link error */
+#define PHY_LINK_BUSY      (1 << 1)	/*!< PHY status bit for MII link busy */
+#define PHY_LINK_CHANGED   (1 << 2)	/*!< PHY status bit for changed state (not persistent) */
+#define PHY_LINK_CONNECTED (1 << 3)	/*!< PHY status bit for connected state */
+#define PHY_LINK_SPEED100  (1 << 4)	/*!< PHY status bit for 100Mbps mode */
+#define PHY_LINK_FULLDUPLX (1 << 5)	/*!< PHY status bit for full duplex mode */
+
+/**
+ * @brief	Phy status update state machine
+ * @return	An Or'ed value of PHY_LINK_* statuses
+ * This function can be called at any rate and will poll the the PHY status. Multiple
+ * calls may be needed to determine PHY status.
+ */
+uint32_t lpcPHYStsPoll(void);
+
+/**
+ * @brief	Initialize the PHY
+ * @param	rmii			: Initializes PHY for RMII mode if true, MII if false
+ * @param	pDelayMsFunc	: Delay function (in mS) used for this driver
+ * @return	PHY_LINK_ERROR or 0 on success
+ * This function initializes the PHY. It will block until complete. It will not
+ * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
+ * detect cable insertion.
+ */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC_PHY_H_ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c

@@ -0,0 +1,281 @@
+/*
+ * @brief Mational DP83848 simple PHY driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "lpc_phy.h"
+
+/** @defgroup DP83848_PHY	BOARD: PHY status and control driver for the DP83848
+ * @ingroup BOARD_PHY
+ * Various functions for controlling and monitoring the status of the
+ * DP83848 PHY.
+ * @{
+ */
+
+/** @brief  DP83848 PHY register offsets */
+#define DP8_BMCR_REG        0x0	/*!< Basic Mode Control Register */
+#define DP8_BMSR_REG        0x1	/*!< Basic Mode Status Reg */
+#define DP8_ANADV_REG       0x4	/*!< Auto_Neg Advt Reg  */
+#define DP8_ANLPA_REG       0x5	/*!< Auto_neg Link Partner Ability Reg */
+#define DP8_ANEEXP_REG      0x6	/*!< Auto-neg Expansion Reg  */
+#define DP8_PHY_STAT_REG    0x10/*!< PHY Status Register  */
+#define DP8_PHY_INT_CTL_REG 0x11/*!< PHY Interrupt Control Register */
+#define DP8_PHY_RBR_REG     0x17/*!< PHY RMII and Bypass Register  */
+#define DP8_PHY_STS_REG     0x19/*!< PHY Status Register  */
+
+/* DP83848 Control register definitions */
+#define DP8_RESET          (1 << 15)	/*!< 1= S/W Reset */
+#define DP8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
+#define DP8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
+#define DP8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
+#define DP8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
+#define DP8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
+#define DP8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
+#define DP8_DUPLEX_MODE    (1 << 8)		/*!< 1=Full duplex mode */
+#define DP8_COLLISION_TEST (1 << 7)		/*!< 1=Perform collsion test */
+
+/* DP83848 Status register definitions */
+#define DP8_100BASE_T4     (1 << 15)	/*!< T4 mode */
+#define DP8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
+#define DP8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
+#define DP8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
+#define DP8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
+#define DP8_MF_PREAMB_SUPPR (1 << 6)	/*!< Preamble suppress */
+#define DP8_AUTONEG_COMP   (1 << 5)		/*!< Auto-negotation complete */
+#define DP8_RMT_FAULT      (1 << 4)		/*!< Fault */
+#define DP8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
+#define DP8_LINK_STATUS    (1 << 2)		/*!< 1=Link active */
+#define DP8_JABBER_DETECT  (1 << 1)		/*!< Jabber detect */
+#define DP8_EXTEND_CAPAB   (1 << 0)		/*!< Supports extended capabilities */
+
+/* DP83848 PHY RBR MII dode definitions */
+#define DP8_RBR_RMII_MODE  (1 << 5)		/*!< Use RMII mode */
+
+/* DP83848 PHY status definitions */
+#define DP8_REMOTEFAULT    (1 << 6)		/*!< Remote fault */
+#define DP8_FULLDUPLEX     (1 << 2)		/*!< 1=full duplex */
+#define DP8_SPEED10MBPS    (1 << 1)		/*!< 1=10MBps speed */
+#define DP8_VALID_LINK     (1 << 0)		/*!< 1=Link active */
+
+/* DP83848 PHY ID register definitions */
+#define DP8_PHYID1_OUI     0x2000		/*!< Expected PHY ID1 */
+#define DP8_PHYID2_OUI     0x5c90		/*!< Expected PHY ID2 */
+
+/* DP83848 PHY update flags */
+static uint32_t physts, olddphysts;
+
+/* PHY update counter for state machine */
+static int32_t phyustate;
+
+/* Pointer to delay function used for this driver */
+static p_msDelay_func_t pDelayMs;
+
+/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_write(uint8_t reg, uint16_t data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Write value for register */
+	Chip_ENET_Start_MII_Write(reg, data);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (Chip_ENET_Is_MII_Busy()) {
+			mst--;
+			pDelayMs(1);
+		}
+		else {
+			mst = 0;
+			sts = SUCCESS;
+		}
+	}
+
+	return sts;
+}
+
+/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_read(uint8_t reg, uint16_t *data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Start register read */
+	Chip_ENET_Start_MII_Read(reg);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (!Chip_ENET_Is_MII_Busy()) {
+			mst = 0;
+			*data = Chip_ENET_Read_MII_Data();
+			sts = SUCCESS;
+		}
+		else {
+			mst--;
+			pDelayMs(1);
+		}
+	}
+
+	return sts;
+}
+
+/* Update PHY status from passed value */
+static void lpc_update_phy_sts(uint16_t linksts)
+{
+	/* Update link active status */
+	if (linksts & DP8_VALID_LINK) {
+		physts |= PHY_LINK_CONNECTED;
+	}
+	else {
+		physts &= ~PHY_LINK_CONNECTED;
+	}
+
+	/* Full or half duplex */
+	if (linksts & DP8_FULLDUPLEX) {
+		physts |= PHY_LINK_FULLDUPLX;
+	}
+	else {
+		physts &= ~PHY_LINK_FULLDUPLX;
+	}
+
+	/* Configure 100MBit/10MBit mode. */
+	if (linksts & DP8_SPEED10MBPS) {
+		physts &= ~PHY_LINK_SPEED100;
+	}
+	else {
+		physts |= PHY_LINK_SPEED100;
+	}
+
+	/* If the status has changed, indicate via change flag */
+	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
+		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
+		olddphysts = physts;
+		physts |= PHY_LINK_CHANGED;
+	}
+}
+
+/* Initialize the DP83848 PHY */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
+{
+	uint16_t tmp;
+	int32_t i;
+
+	pDelayMs = pDelayMsFunc;
+
+	/* Initial states for PHY status and state machine */
+	olddphysts = physts = phyustate = 0;
+
+	/* Only first read and write are checked for failure */
+	/* Put the DP83848C in reset mode and wait for completion */
+	if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != SUCCESS) {
+		return ERROR;
+	}
+	i = 400;
+	while (i > 0) {
+		pDelayMs(1);
+		if (lpc_mii_read(DP8_BMCR_REG, &tmp) != SUCCESS) {
+			return ERROR;
+		}
+
+		if (!(tmp & (DP8_RESET | DP8_POWER_DOWN))) {
+			i = -1;
+		}
+		else {
+			i--;
+		}
+	}
+	/* Timeout? */
+	if (i == 0) {
+		return ERROR;
+	}
+
+#if 0
+	/* Setup link based on configuration options */
+#if PHY_USE_AUTONEG == 1
+	tmp = DP8_AUTONEG;
+#else
+	tmp = 0;
+#endif
+#if PHY_USE_100MBS == 1
+	tmp |= DP8_SPEED_SELECT;
+#endif
+#if PHY_USE_FULL_DUPLEX == 1
+	tmp |= DP8_DUPLEX_MODE;
+#endif
+
+#else
+	tmp = DP8_AUTONEG;
+#endif
+
+	lpc_mii_write(DP8_BMCR_REG, tmp);
+
+	/* Enable RMII mode for PHY */
+	if (rmii) {
+		lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
+	}
+
+	/* The link is not set active at this point, but will be detected
+	   later */
+
+	return SUCCESS;
+}
+
+/* Phy status update state machine */
+uint32_t lpcPHYStsPoll(void)
+{
+	switch (phyustate) {
+	default:
+	case 0:
+		/* Read BMSR to clear faults */
+		Chip_ENET_Start_MII_Read(DP8_PHY_STAT_REG);
+		physts &= ~PHY_LINK_CHANGED;
+		physts = physts | PHY_LINK_BUSY;
+		phyustate = 1;
+		break;
+
+	case 1:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Update PHY status */
+			physts &= ~PHY_LINK_BUSY;
+			lpc_update_phy_sts(Chip_ENET_Read_MII_Data());
+			phyustate = 0;
+		}
+		break;
+	}
+
+	return physts;
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c

@@ -0,0 +1,270 @@
+/*
+ * @brief SMSC 87x0 simple PHY driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "lpc_phy.h"
+
+/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
+ * @ingroup BOARD_PHY
+ * Various functions for controlling and monitoring the status of the
+ * SMSC 87x0 PHY.
+ * @{
+ */
+
+/* LAN8720 PHY register offsets */
+#define LAN8_BCR_REG        0x0	/*!< Basic Control Register */
+#define LAN8_BSR_REG        0x1	/*!< Basic Status Reg */
+#define LAN8_PHYID1_REG     0x2	/*!< PHY ID 1 Reg  */
+#define LAN8_PHYID2_REG     0x3	/*!< PHY ID 2 Reg */
+#define LAN8_PHYSPLCTL_REG  0x1F/*!< PHY special control/status Reg */
+
+/* LAN8720 BCR register definitions */
+#define LAN8_RESET          (1 << 15)	/*!< 1= S/W Reset */
+#define LAN8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
+#define LAN8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
+#define LAN8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
+#define LAN8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
+#define LAN8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
+#define LAN8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
+#define LAN8_DUPLEX_MODE    (1 << 8)	/*!< 1=Full duplex mode */
+
+/* LAN8720 BSR register definitions */
+#define LAN8_100BASE_T4     (1 << 15)	/*!< T4 mode */
+#define LAN8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
+#define LAN8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
+#define LAN8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
+#define LAN8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
+#define LAN8_AUTONEG_COMP   (1 << 5)	/*!< Auto-negotation complete */
+#define LAN8_RMT_FAULT      (1 << 4)	/*!< Fault */
+#define LAN8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
+#define LAN8_LINK_STATUS    (1 << 2)	/*!< 1=Link active */
+#define LAN8_JABBER_DETECT  (1 << 1)	/*!< Jabber detect */
+#define LAN8_EXTEND_CAPAB   (1 << 0)	/*!< Supports extended capabilities */
+
+/* LAN8720 PHYSPLCTL status definitions */
+#define LAN8_SPEEDMASK      (7 << 2)	/*!< Speed and duplex mask */
+#define LAN8_SPEED100F      (6 << 2)	/*!< 100BT full duplex */
+#define LAN8_SPEED10F       (5 << 2)	/*!< 10BT full duplex */
+#define LAN8_SPEED100H      (2 << 2)	/*!< 100BT half duplex */
+#define LAN8_SPEED10H       (1 << 2)	/*!< 10BT half duplex */
+
+/* LAN8720 PHY ID 1/2 register definitions */
+#define LAN8_PHYID1_OUI     0x0007		/*!< Expected PHY ID1 */
+#define LAN8_PHYID2_OUI     0xC0F0		/*!< Expected PHY ID2, except last 4 bits */
+
+/* DP83848 PHY update flags */
+static uint32_t physts, olddphysts;
+
+/* PHY update counter for state machine */
+static int32_t phyustate;
+
+/* Pointer to delay function used for this driver */
+static p_msDelay_func_t pDelayMs;
+
+/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_write(uint8_t reg, uint16_t data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Write value for register */
+	Chip_ENET_Start_MII_Write(reg, data);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (Chip_ENET_Is_MII_Busy()) {
+			mst--;
+			pDelayMs(1);
+		}
+		else {
+			mst = 0;
+			sts = SUCCESS;
+		}
+	}
+
+	return sts;
+}
+
+/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_read(uint8_t reg, uint16_t *data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Start register read */
+	Chip_ENET_Start_MII_Read(reg);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (!Chip_ENET_Is_MII_Busy()) {
+			mst = 0;
+			*data = Chip_ENET_Read_MII_Data();
+			sts = SUCCESS;
+		}
+		else {
+			mst--;
+			pDelayMs(1);
+		}
+	}
+
+	return sts;
+}
+
+/* Update PHY status from passed value */
+static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
+{
+	/* Update link active status */
+	if (linksts & LAN8_LINK_STATUS) {
+		physts |= PHY_LINK_CONNECTED;
+	}
+	else {
+		physts &= ~PHY_LINK_CONNECTED;
+	}
+
+	switch (sdsts & LAN8_SPEEDMASK) {
+	case LAN8_SPEED100F:
+	default:
+		physts |= PHY_LINK_SPEED100;
+		physts |= PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED10F:
+		physts &= ~PHY_LINK_SPEED100;
+		physts |= PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED100H:
+		physts |= PHY_LINK_SPEED100;
+		physts &= ~PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED10H:
+		physts &= ~PHY_LINK_SPEED100;
+		physts &= ~PHY_LINK_FULLDUPLX;
+		break;
+	}
+
+	/* If the status has changed, indicate via change flag */
+	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
+		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
+		olddphysts = physts;
+		physts |= PHY_LINK_CHANGED;
+	}
+}
+
+/* Initialize the SMSC 87x0 PHY */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
+{
+	uint16_t tmp;
+	int32_t i;
+
+	pDelayMs = pDelayMsFunc;
+
+	/* Initial states for PHY status and state machine */
+	olddphysts = physts = phyustate = 0;
+
+	/* Only first read and write are checked for failure */
+	/* Put the DP83848C in reset mode and wait for completion */
+	if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
+		return ERROR;
+	}
+	i = 400;
+	while (i > 0) {
+		pDelayMs(1);
+		if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
+			return ERROR;
+		}
+
+		if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
+			i = -1;
+		}
+		else {
+			i--;
+		}
+	}
+	/* Timeout? */
+	if (i == 0) {
+		return ERROR;
+	}
+
+	/* Setup link */
+	lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
+
+	/* The link is not set active at this point, but will be detected
+	   later */
+
+	return SUCCESS;
+}
+
+/* Phy status update state machine */
+uint32_t lpcPHYStsPoll(void)
+{
+	static uint16_t sts;
+
+	switch (phyustate) {
+	default:
+	case 0:
+		/* Read BMSR to clear faults */
+		Chip_ENET_Start_MII_Read(LAN8_BSR_REG);
+		physts &= ~PHY_LINK_CHANGED;
+		physts = physts | PHY_LINK_BUSY;
+		phyustate = 1;
+		break;
+
+	case 1:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Get PHY status with link state */
+			sts = Chip_ENET_Read_MII_Data();
+			Chip_ENET_Start_MII_Read(LAN8_PHYSPLCTL_REG);
+			phyustate = 2;
+		}
+		break;
+
+	case 2:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Update PHY status */
+			physts &= ~PHY_LINK_BUSY;
+			smsc_update_phy_sts(sts, Chip_ENET_Read_MII_Data());
+			phyustate = 0;
+		}
+		break;
+	}
+
+	return physts;
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox

@@ -0,0 +1,62 @@
+/*
+ * @brief LPCOpen 18xx/43xx board support page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards
+ * @ingroup Board_Layer
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/*!
+ * @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms
+ *
+ * <b>Device Support</b><br/>
+ * All LPC18xx and LPC43xx device variants are supported.<br/><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=103">LPC18xx documentation links</a><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=104">LPC43xx documentation links</a><br/><br/>
+ * <b>Board Support</b><br/>
+ * Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported.
+ * Click <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco">here</a> for LPCOpen build procedures and default jumper configuration for supported boards.<br/><br/>
+ * <a href="http://www.hitex.com/index.php?id=3455/">Hitex LPC1857 and LPC4357 evaluation boards </a><br/>
+ * <a href="http://www.keil.com/mcb1800/">Keil MCB1800</a> and <a href="http://www.keil.com/mcb4300/">Keil MCB4300 boards</a><br/>
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC1830-Xplorer_Quick_Start_Guide">NGX LPC1830 Xplorer</a> and 
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC4330-Xplorer_Quick_Start_Guide">NGX LPC4330 Xplorer boards</a><br/>
+ *
+ * <b>Toolchain Support</b><br/>
+ * Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco#Supported_toolchains">build support pages</a>
+ * for information on specific versions of the toolchains tested with the LPCOpen platform.<br/><br/>
+ * <a href="http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/">IAR EWARM</a><br/>
+ * <a href="http://www.keil.com/arm/mdk.asp">ARM MDK-ARM</a><br/>
+ * <a href="http://code-red-tech.com/lpcxpresso">LPCXpresso</a>
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_hitex_eva_18504350.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c

@@ -0,0 +1,898 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+#include "string.h"
+
+/* Include other sources files specific to this board */
+#include "lpc_phy_dp83848.c"
+#include "retarget.c"
+
+/** @ingroup BOARD_HITEX_EVA_18504350
+ * @{
+ */
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Port and bit mapping for LEDs on GPIOs */
+static const uint8_t ledports[] = {4, 7, 7, 7};
+static const uint8_t ledbits[] = {1, 5, 6, 8};
+
+/* TSC2046 control byte definitions */
+#define TSC_START                          (0x01 << 7)
+#define TSC_CHANNEL_X                      (0x05 << 4)		/* differential */
+#define TSC_CHANNEL_Y                      (0x01 << 4)		/* differential */
+#define TSC_CHANNEL_Z1                     (0x03 << 4)		/* differential */
+#define TSC_CHANNEL_Z2                     (0x04 << 4)		/* differential */
+#define TSC_8BIT                           (0x01 << 3)
+#define TSC_12BIT                          (0x00 << 3)
+#define TSC_PD                              0x00
+#define TSC_ADC_ON                          0x01
+#define TSC_REF_ON                          0x02
+#if (TSC2046_CONVERSION_BITS == 12)
+#define TSC_CONVERSION_MODE                 TSC_12BIT
+#else
+#define TSC_CONVERSION_MODE                 TSC_8BIT
+#endif
+
+#define TSC_SER_MODE                       (0x01 << 2)	/* Single-Ended Reference Mode */
+#define TSC_DFR_MODE                       (0x00 << 2)	/* Differential Reference Mode */
+
+#define X_MEASURE      (TSC_START | TSC_CHANNEL_X  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
+#define Y_MEASURE      (TSC_START | TSC_CHANNEL_Y  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
+#define Z1_MEASURE     (TSC_START | TSC_CHANNEL_Z1 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
+#define Z2_MEASURE     (TSC_START | TSC_CHANNEL_Z2 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
+#define PWRDOWN          (TSC_START | TSC_CHANNEL_Y  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_PD)
+
+typedef struct {
+	int16_t ad_left;						/* left margin */
+	int16_t ad_right;						/* right margin */
+	int16_t ad_top;							/* top margin */
+	int16_t ad_bottom;						/* bottom margin */
+	int16_t lcd_width;						/* lcd horizontal size */
+	int16_t lcd_height;						/* lcd vertical size */
+	uint8_t swap_xy;						/* 1: swap x-y coords */
+} TSC2046_Init_Type;
+
+#define DC_CMD          (Chip_GPIO_WritePortBit(0x07, 8, false))
+#define DC_DATA         (Chip_GPIO_WritePortBit(0x07, 8, true))
+
+#define TSC2046_CONVERSION_BITS     12
+
+#if (TSC2046_CONVERSION_BITS == 12)
+#define TSC2046_COORD_MAX           (0xFFF)
+#define TSC2046_DELTA_VARIANCE      (0x50)
+#else
+#define TSC2046_COORD_MAX           (0xFF)
+#define TSC2046_DELTA_VARIANCE      (0x03)
+#endif
+#define COORD_GET_NUM                 (10)
+
+/** Local variables */
+static TSC2046_Init_Type TSC_Config = {
+	3686, 205, 3842, 267, 240, 320, 1
+};
+
+/**
+ * LCD configuration data
+ */
+const LCD_Config_Type EA320x240 = {
+	28,		/* Horizontal back porch in clocks */
+	10,		/* Horizontal front porch in clocks */
+	2,		/* HSYNC pulse width in clocks */
+	240,	/* Pixels per line */
+	2,		/* Vertical back porch in clocks */
+	1,		/* Vertical front porch in clocks */
+	2,		/* VSYNC pulse width in clocks */
+	320,	/* Lines per panel */
+	0,		/* Invert output enable, 1 = invert */
+	1,		/* Invert panel clock, 1 = invert */
+	1,		/* Invert HSYNC, 1 = invert */
+	1,		/* Invert VSYNC, 1 = invert */
+	1,		/* AC bias frequency in clocks (not used) */
+	6,		/* Maximum bits per pixel the display supports */
+	LCD_TFT,		/* LCD panel type */
+	LCD_COLOR_FORMAT_BGR,		/* BGR or RGB */
+	0		/* Dual panel, 1 = dual panel display */
+};
+
+/* UDA1380 Register Address */
+typedef enum {
+	UDA_EVALM_CLK = 0x00,
+	UDA_BUS_CTRL,
+	UDA_POWER_CTRL,
+	UDA_ANALOG_CTRL,
+	UDA_HPAMP_CTRL,
+	UDA_MASTER_VOL_CTRL = 0x10,
+	UDA_MIXER_VOL_CTRL,
+	UDA_MODE_CTRL,
+	UDA_MUTE_CTRL,
+	UDA_MIXER_FILTER_CTRL,
+	UDA_DEC_VOL_CTRL = 0x20,
+	UDA_PGA_CTRL,
+	UDA_ADC_CTRL,
+	UDA_AGC_CTRL,
+	UDA_TOTAL_REG
+} UDA1380_REG;
+
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
+#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
+
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE   (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE   ( 1 << 9 | 2)
+
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE  (2 << 8 | 2)
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE      0x0000
+
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE     0xE4E4			/* Decrease Volume -28dB */
+#define UDA1380_REG_PGA_DEFAULT_VALUE         0x0000
+#define UDA1380_REG_ADC_DEFAULT_VALUE         0x0001		/* Apply 0bB VGA Gain, enable DC Filter */
+#define UDA1380_REG_AGC_DEFAULT_VALUE         0x0000
+
+#define UDA1380_REG_L3_DEFAULT_VALUE          0x0000
+
+/* System Register Data Set */
+static uint16_t UDA_sys_regs_dat[] = {
+	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
+	UDA1380_REG_I2S_DEFAULT_VALUE,
+	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
+	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
+	UDA1380_REG_HEADAMP_DEFAULT_VALUE
+};
+
+/* System Register Data Set */
+static uint16_t UDA_interfil_regs_dat[] = {
+	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
+	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
+	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
+	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
+	UDA1380_REG_MIXSDO_DEFAULT_VALUE
+};
+/* decimator Register Data Set */
+static uint16_t UDA_decimator_regs_dat[] = {
+	UDA1380_REG_DECVOL_DEFAULT_VALUE,
+	UDA1380_REG_PGA_DEFAULT_VALUE,
+	UDA1380_REG_ADC_DEFAULT_VALUE,
+	UDA1380_REG_AGC_DEFAULT_VALUE
+};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Very simple (inaccurate) delay function */
+static void DelayMs(uint32_t ms)
+{
+	uint32_t i;
+	for (i = 0; i < 100 * ms; i++) {}
+}
+
+/* Additional (SPI) pin configuration for LCD interface signals */
+static void lcdPinConfig(void)
+{
+	/* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */
+	Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4);
+	Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4);
+	Chip_GPIO_WriteDirBit(0x6, 10, true);
+	Chip_GPIO_WriteDirBit(0x6, 11, true);
+
+	/* Configure SSP0 pins */
+	/* PF.0 connected to SCL/SCLK */
+	Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0);
+	/* PF.1 connected to nCS */
+	Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2);
+	/* PF.2 connected to SO */
+	Chip_SCU_PinMux(0xF, 2, MD_PLN_FAST, FUNC2);
+	/* PF.3 connected to nSI */
+	Chip_SCU_PinMux(0xF, 3, MD_PLN_FAST, FUNC2);
+
+	/* DC PIN */
+	Chip_SCU_PinMux(0x0E, 8, MD_PUP, FUNC4);
+	Chip_GPIO_WriteDirBit(7, 8, true);
+}
+
+/* Write to a LCD register using SPI */
+static void writeToReg(uint16_t addr, uint16_t data)
+{
+	uint8_t buf[2];
+
+	Chip_GPIO_WritePortBit(0x06, 10, true);
+	Chip_GPIO_WritePortBit(0x06, 11, false);
+
+	DC_CMD;
+
+	buf[0] = 0;
+	buf[1] = (addr & 0xff);
+
+	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
+
+	DC_DATA;
+	buf[0] = (data >> 8);
+	buf[1] = (data & 0xff);
+	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
+
+	DC_CMD;
+
+	buf[0] = (0);
+	buf[1] = (0x22);
+	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
+}
+
+/* Initialize SSD1289 LCD Controller */
+static void ssd1289_init(void)
+{
+	writeToReg(0x00, 0x0001);
+	DelayMs(15);
+	writeToReg(0x03, 0x6E3E);	// 0xAEAC
+	writeToReg(0x0C, 0x0007);
+	writeToReg(0x0D, 0x000E);	// 0x000F
+	writeToReg(0x0E, 0x2C00);	// 0x2900
+	writeToReg(0x1E, 0x00AE);	// 0x00B3
+	DelayMs(15);
+	writeToReg(0x07, 0x0021);
+	DelayMs(50);
+	writeToReg(0x07, 0x0023);
+	DelayMs(50);
+	writeToReg(0x07, 0x0033);
+	DelayMs(50);
+
+	writeToReg(0x01, 0x2B3F);
+	writeToReg(0x02, 0x0600);
+	writeToReg(0x10, 0x0000);
+	DelayMs(15);
+	writeToReg(0x11, 0xC5B0);	// 0x65b0
+	DelayMs(20);
+	writeToReg(0x05, 0x0000);
+	writeToReg(0x06, 0x0000);
+	writeToReg(0x16, 0xEF1C);
+	writeToReg(0x17, 0x0003);
+	writeToReg(0x07, 0x0233);
+	writeToReg(0x0B, 0x5312);
+	writeToReg(0x0F, 0x0000);
+	writeToReg(0x25, 0xE000);
+	DelayMs(20);
+	writeToReg(0x41, 0x0000);
+	writeToReg(0x42, 0x0000);
+	writeToReg(0x48, 0x0000);
+	writeToReg(0x49, 0x013F);
+	writeToReg(0x44, 0xEF00);
+	writeToReg(0x45, 0x0000);
+	writeToReg(0x46, 0x013F);
+	writeToReg(0x4A, 0x0000);
+	writeToReg(0x4B, 0x0000);
+	DelayMs(20);
+	writeToReg(0x30, 0x0707);
+	writeToReg(0x31, 0x0704);
+	writeToReg(0x32, 0x0005);	// 0x0204
+	writeToReg(0x33, 0x0402);	// 0x0201
+	writeToReg(0x34, 0x0203);
+	writeToReg(0x35, 0x0204);
+	writeToReg(0x36, 0x0204);
+	writeToReg(0x37, 0x0401);	// 0x0502
+	writeToReg(0x3A, 0x0302);
+	writeToReg(0x3B, 0x0500);
+	DelayMs(20);
+	writeToReg(0x22, 0x0000);
+}
+
+/* Send/Receive data to/from TSC2046. */
+static void TSC2046_ReadWrite(uint8_t command, uint16_t *data)
+{
+	uint32_t tmp;
+	uint8_t rx_data[2], tx_data[1] = {0x00};
+
+	tx_data[0] = command;
+	Chip_GPIO_WritePortBit(6, 10, false);
+	Chip_GPIO_WritePortBit(6, 11, true);
+
+	Chip_GPIO_WritePortBit(7, 16, false);
+
+	for (tmp = 0x100; tmp; tmp--) {}
+
+	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, tx_data, 1);
+	Chip_SSP_ReadFrames_Blocking(LPC_SSP0, rx_data, 2);
+
+	for (tmp = 0x100; tmp; tmp--) {}
+
+#if (TSC2046_CONVERSION_BITS == 8)
+	*data = (((rx_data[0] << 8) | (rx_data[1])) >> 7) & 0xFF;
+#else
+	*data = (((rx_data[0] << 8) | rx_data[1]) >> 3) & 0xFFF;
+#endif
+	Chip_GPIO_WritePortBit(7, 16, true);
+}
+
+/* Evaluate the coordinates received from TSC. */
+static Status EvalCoord(uint8_t command, uint16_t *coord)
+{
+	uint32_t i;
+	uint16_t Tmp = 0, previousTmp;
+	int16_t diff = 0;
+	*coord = 0;
+	for (i = 0; i < COORD_GET_NUM; i++) {
+		previousTmp = Tmp;
+		TSC2046_ReadWrite(command, &Tmp);
+		if (Tmp > TSC2046_COORD_MAX) {
+			return ERROR;
+		}
+		if (i > 0) {
+			diff = Tmp - previousTmp;
+		}
+		if (diff < 0) {
+			diff = 0 - diff;
+		}
+		if (diff > TSC2046_DELTA_VARIANCE) {
+			return ERROR;
+		}
+		*coord += Tmp;
+	}
+	*coord /= COORD_GET_NUM;
+	return SUCCESS;
+}
+
+/* Convert the coord received from TSC to a value on truly LCD */
+static int16_t TSCCalibrate(int16_t Coord, int16_t MinVal, int16_t MaxVal, int16_t TrueSize)
+{
+	int16_t tmp;
+	int16_t ret;
+	uint8_t convert = 0;
+
+	/* Swap value? */
+	if (MinVal > MaxVal) {
+		tmp = MaxVal;
+		MaxVal = MinVal;
+		MinVal = tmp;
+		convert = 1;
+	}
+
+	ret = (Coord - MinVal) * TrueSize / (MaxVal - MinVal);
+	if (convert) {
+		ret = TrueSize - ret;
+	}
+
+	return ret;
+}
+
+static void delay(uint32_t i) {
+	while (i--) {}
+}
+
+/* Write value to a UDA1380 register */
+static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
+
+	I2C_Config->tx_data[0] = reg;
+	I2C_Config->tx_data[1] = value >> 8;
+	I2C_Config->tx_data[2] = value & 0xFF;
+	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
+	delay(10000);
+}
+
+/* Read value from a UDA1380 register */
+static uint16_t UDA_Reg_read(UDA1380_REG reg) {
+	uint8_t rx_data[2];
+	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
+	return rx_data[0] << 8 | rx_data[1];
+}
+
+/* Initialize UDA1380 CODEC */
+static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint16_t temp;
+	uint8_t  i;
+	/* Reset UDA1380 on board Hitex A4*/
+	/* PE_9: UDA_RST on Hitex A4 */
+	Chip_SCU_PinMux(0x0E, 9, MD_PUP, FUNC4);
+	Chip_GPIO_WriteDirBit(7, 9, true);
+	Chip_GPIO_WritePortBit(7, 9, true);
+	/* delay 1us */
+	delay(100000);
+	Chip_GPIO_WritePortBit(7, 9, false);
+	delay(100000);
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
+		if (temp != UDA_sys_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	/* interfilter regs init */
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
+		if (temp != UDA_interfil_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+	/* decimator regs init */
+	for (i = 0; i < 4; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
+		if (temp != UDA_decimator_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
+		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
+		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
+					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
+					  I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+	}
+	return SUCCESS;
+
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize pin muxing for a UART */
+void Board_UART_Init(LPC_USART_Type *UARTx)
+{
+	if (UARTx == LPC_USART0) {
+		Chip_SCU_PinMux(0xF, 10, MD_PDN, FUNC1);	/* PF.10 : UART0_TXD */
+		Chip_SCU_PinMux(0xF, 11, MD_PLN | MD_EZI | MD_ZI, FUNC1);	/* PF.11 : UART0_RXD */
+	}
+	else if (UARTx == LPC_UART1) {
+		Chip_SCU_PinMux(0xC, 13, MD_PDN, FUNC2);	/* PC.13 : UART1_TXD - pin 1 of SV14 */
+		Chip_SCU_PinMux(0xC, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PC.14 : UART1_RX - pin 2 of SV14 */
+	}
+	else if (UARTx == LPC_USART2) {
+		/* P1.15 : UART2_TXD - pin 11 of SV6, P1.16 : UART2_RXD - pin 3 of SV6 */
+		Chip_SCU_PinMux(0x1, 15, MD_PDN, FUNC1);
+		Chip_SCU_PinMux(0x1, 16, MD_PLN | MD_EZI | MD_ZI, FUNC1);
+	}
+	else if (UARTx == LPC_USART3) {
+		/* P9.3 : UART3_TXD - pin 15 of SV6, P9.4 : UART3_RXD - pin 7 of SV3 */
+		Chip_SCU_PinMux(0x9, 3, MD_PDN, FUNC7);
+		Chip_SCU_PinMux(0x9, 4, MD_PLN | MD_EZI | MD_ZI, FUNC7);
+	}
+}
+
+/* Initialize debug output via UART for board */
+void Board_Debug_Init(void)
+{
+#if defined(DEBUG_UART)
+	Board_UART_Init(DEBUG_UART);
+
+	Chip_UART_Init(DEBUG_UART);
+	Chip_UART_SetBaud(DEBUG_UART, 115200);
+	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
+
+	/* Enable UART Transmit */
+	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
+#endif
+}
+
+/* Sends a character on the UART */
+void Board_UARTPutChar(char ch)
+{
+#if defined(DEBUG_UART)
+	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
+#endif
+}
+
+/* Gets a character from the UART, returns EOF if no character is ready */
+int Board_UARTGetChar(void)
+{
+#if defined(DEBUG_UART)
+	uint8_t data;
+
+	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
+		return (int) data;
+	}
+#endif
+	return EOF;
+}
+
+/* Outputs a string on the debug UART */
+void Board_UARTPutSTR(char *str)
+{
+#if defined(DEBUG_UART)
+	while (*str != '\0') {
+		Board_UARTPutChar(*str++);
+	}
+#endif
+}
+
+/* Initializes board LED(s) */
+void Board_LED_Init()
+{
+	int i;
+
+	/* Set ports as outputs with initial states off */
+	for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) {
+		Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true);
+		Chip_GPIO_WritePortBit(ledports[i], ledbits[i], true);
+	}
+	Chip_GPIO_WritePortBit(ledports[0], ledbits[0], false);
+}
+
+/* Sets the state of a board LED to on or off */
+void Board_LED_Set(uint8_t LEDNumber, bool On)
+{
+	/* Must connect JP3 to see LED0 and JP4 to see LED1 */
+	if (LEDNumber == 0) {
+		On = !On;
+	}
+
+	if (LEDNumber < 4) {
+		Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], !On);
+	}
+}
+
+/* Returns the current state of a board LED */
+bool Board_LED_Test(uint8_t LEDNumber)
+{
+	bool On = false;
+
+	if (LEDNumber < 4) {
+		On = (bool) !Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]);
+
+		if (LEDNumber == 0) {
+			On = ~On;
+		}
+	}
+
+	return On;
+}
+
+/* Initialize button(s) interface on board */
+void Board_Buttons_Init(void)	// FIXME not functional ATM
+{
+	Chip_SCU_PinMux(0xD, 7, MD_PUP | MD_EZI, FUNC4);			// GPIO6[21]
+	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false);	// input
+}
+
+/* Returns button(s) state on board */
+uint32_t Buttons_GetStatus(void)
+{
+	uint8_t ret = NO_BUTTON_PRESSED;
+	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
+		ret |= BUTTONS_BUTTON1;
+	}
+	return ret;
+}
+
+/* Initialize joystick interface on board */
+void Board_Joystick_Init(void)
+{}
+
+/* Returns joystick states on board */
+uint8_t Joystick_GetStatus(void)
+{
+	return NO_BUTTON_PRESSED;
+}
+
+/**
+ * System Clock Frequency (Core Clock)
+ */
+uint32_t SystemCoreClock;
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
+}
+
+/* Returns the MAC address assigned to this board */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr)
+{
+	const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
+
+	memcpy(mcaddr, boardmac, 6);
+}
+
+/* Set up and initialize all required blocks and functions related to the
+   board hardware */
+void Board_Init(void)
+{
+	/* Sets up DEBUG UART */
+	DEBUGINIT();
+
+	/* Updates SystemCoreClock global var with current clock speed */
+	SystemCoreClockUpdate();
+
+	/* Initializes GPIO */
+	Chip_GPIO_Init();
+
+	/* Setup GPIOs for USB demos */
+#if 0 /* FIXME: the following call removed on the Hitex board as it interferes with muxed MII state */
+	//	Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2);			// P9_5 USB1_VBUS_EN, USB1 VBus function
+#endif
+	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	// P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+	Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1);			// P6_3 USB0_PWR_EN, USB0 VBus function
+}
+
+/* Sets up board specific ADC interface */
+void Board_ADC_Init(void)
+{
+	/* Analog function ADC1_2 selected on pin PF_9 */
+	Chip_SCU_ADC_Channel_Config(1, 2);
+}
+
+/* Sets up board specific I2C interface */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C1) {
+		/* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */
+		Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2);
+		Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2);
+	}
+}
+
+/* Initialize the LCD interface */
+void Board_LCD_Init(void)
+{
+	SSP_ConfigFormat ssp_format1;
+	/* Attach main PLL clock to divider A with a divider of 2 */
+	Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2);
+
+	/* Route divider A output to LCD base clock and enable base clock */
+	Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false);
+
+	/* Reset LCD and wait for reset to complete */
+	Chip_RGU_TriggerReset(RGU_LCD_RST);
+	while (Chip_RGU_InReset(RGU_LCD_RST)) {}
+
+	lcdPinConfig();
+	Chip_Clock_Enable(CLK_MX_SSP0);
+	Chip_SSP_Init(LPC_SSP0);
+	Chip_SSP_Set_Master(LPC_SSP0, true);
+	Chip_SSP_Set_BitRate(LPC_SSP0, 1000000);
+
+	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
+	ssp_format1.bits = SSP_BITS_8;
+	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
+
+	Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1);
+	Chip_SSP_Cmd(LPC_SSP0, ENABLE);
+
+	DelayMs(200);
+
+	/* initialize LCD controller */
+	ssd1289_init();
+
+	Chip_SSP_Cmd(LPC_SSP0, DISABLE);
+	Chip_SSP_DeInit(LPC_SSP0);
+}
+
+/* Initialize TSC2046 touchscreen controller */
+void Init_Touch_Controller(void)
+{
+	uint16_t dummy_data;
+	SSP_ConfigFormat ssp_format1;
+
+	/* Configure SSP0 pins*/
+	lcdPinConfig();
+	Chip_SCU_PinMux(0xF, 1, MD_PUP, FUNC4);
+
+	Chip_GPIO_WriteDirBit(7, 16, true);
+
+	Chip_GPIO_WritePortBit(6, 10, false);
+	Chip_GPIO_WritePortBit(6, 11, true);
+
+	Chip_SSP_Init(LPC_SSP0);
+
+	Chip_SSP_Set_Master(LPC_SSP0, true);
+	Chip_SSP_Set_BitRate(LPC_SSP0, 200000);
+
+	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
+	ssp_format1.bits = SSP_BITS_8;
+	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
+
+	Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1);
+	Chip_SSP_Cmd(LPC_SSP0, ENABLE);
+
+	/* Enable Touch Screen Controller */
+	TSC2046_ReadWrite(PWRDOWN, &dummy_data);
+}
+
+/* Get Touch coordinates */
+bool GetTouchPos(int16_t *pX, int16_t *pY)
+{
+	uint16_t tmp;
+	uint16_t x, y, z1, z2, z = 0;
+	Status Sts = SUCCESS;
+
+	TSC2046_ReadWrite(X_MEASURE, &x);
+	TSC2046_ReadWrite(Y_MEASURE, &y);
+	TSC2046_ReadWrite(Z1_MEASURE, &z1);
+	TSC2046_ReadWrite(Z2_MEASURE, &z2);
+
+	if (z1 != 0) {
+		z = x * ((z2 / z1) - 1);
+	}
+	if ((z <= 0) || (z > 35000)) {
+		return false;
+	}
+	/* Get X-Coordinate */
+	Sts = EvalCoord(X_MEASURE, &x);
+
+	if (Sts == ERROR) {
+		return false;
+	}
+	/* Get Y-Coordinate */
+	Sts = EvalCoord(Y_MEASURE, &y);
+	if (Sts == ERROR) {
+		return false;
+	}
+	/* Get Z1-Value */
+	Sts = EvalCoord(Z1_MEASURE, &z1);
+	if (Sts == ERROR) {
+		return false;
+	}
+	/* Get Z2-Value */
+	Sts = EvalCoord(Z2_MEASURE, &z2);
+	if (Sts == ERROR) {
+		return false;
+	}
+
+	z = x * ((z2 / z1) - 1);
+	if ((z <= 0) || (z > 35000)) {
+		return false;
+	}
+	else {
+		/* Swap, adjust to truly size of LCD */
+		if (TSC_Config.swap_xy) {
+			*pY = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_height);
+			*pX = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_width);
+		}
+		else {
+			*pX = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_width);
+			*pY = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_height);
+		}
+	}
+	TSC2046_ReadWrite(PWRDOWN, &tmp);
+
+	return true;
+}
+
+/* Turn on Board LCD Backlight */
+void Board_LCD_Set_Backlight(uint8_t Intensity)
+{
+	bool OnOff = (bool) (Intensity != 0);
+
+	Chip_GPIO_WritePortBit(3, 8, OnOff);
+}
+
+/* Initialize pin muxing for SDMMC interface */
+void Board_SDMMC_Init(void)
+{
+	Chip_SCU_PinMux(0xc, 9, MD_PLN, FUNC7);				/* Pc.9 SDIO power */
+	Chip_SCU_PinMux(0xc, 2, MD_PLN, FUNC7);				/* Pc.2 SDIO LED */
+	Chip_SCU_PinMux(0xf, 10, MD_PLN | MD_EZI, FUNC6);	/* Pf.10 SDIO WP */
+	Chip_SCU_PinMux(0xc, 8, MD_PLN | MD_EZI, FUNC7);	/* Pc.8 SDIO CD */
+	Chip_SCU_PinMux(0xc, 6, MD_PLN_FAST, FUNC7);		/* Pc.6 SDIO D2 */
+	Chip_SCU_PinMux(0xc, 5, MD_PLN_FAST, FUNC7);		/* Pc.5 SDIO D1 */
+	Chip_SCU_PinMux(0xc, 4, MD_PLN_FAST, FUNC7);		/* Pc.4 SDIO D0 */
+	Chip_SCU_PinMux(0xc, 0, MD_PLN | MD_EHS, FUNC7);	/* Pc.0 SDIO clock */
+	Chip_SCU_PinMux(0xc, 10, MD_PLN_FAST, FUNC7);		/* Pc.10 SDIO command */
+	Chip_SCU_PinMux(0xc, 7, MD_PLN_FAST, FUNC7);		/* Pc.7 SDIO D3 */
+}
+
+/* Initialize pin muxing for SSP interface */
+void Board_SSP_Init(LPC_SSP_Type *SSPx)
+{
+	if (SSPx == LPC_SSP0) {
+		/* Set up clock and muxing for SSP0 interface */
+		// #if !defined(HITEX_LCD_TERM)
+		/* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */
+		Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4);
+		Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4);
+		Chip_GPIO_WriteDirBit(0x6, 10, true);
+		Chip_GPIO_WriteDirBit(0x6, 11, true);
+		// #endif
+		/* PF.0 connected to SCL/SCLK	func2=SSP0 SCK0 */
+		Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0);
+		/* PF.1 connected to nCS		func2=SSP0 SSEL0 */
+		Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2);
+		/* PF.2 connected to SO			func2=SSP0 MISO0 */
+		Chip_SCU_PinMux(0xF, 2, MD_PLN | MD_EZI | MD_ZI, FUNC2);
+		/* PF.3 connected to nSI		func2=SSP0 MOSI0 */
+		Chip_SCU_PinMux(0xF, 3, MD_PLN | MD_EZI | MD_ZI, FUNC2);
+
+		Chip_Clock_Enable(CLK_MX_SSP0);
+	}
+	else if (SSPx == LPC_SSP1) {
+		/* Set up clock and muxing for SSP1 interface */
+		/* P1.19 connected to SCL/SCLK	func1=SSP1 SCK1 */
+		Chip_SCU_PinMux(0x1, 19, MD_PLN_FAST, FUNC1);
+		/* P1.20 connected to nCS		func1=SSP1 SSEL1 */
+		Chip_SCU_PinMux(0x1, 20, MD_PLN_FAST, FUNC1);
+		/* P0.0 connected to SO			func1=SSP1 MISO1 */
+		Chip_SCU_PinMux(0x0, 0, MD_PLN | MD_EZI | MD_ZI, FUNC1);
+		/* P0.1 connected to nSI		func2=SSP1 MOSI1 */
+		Chip_SCU_PinMux(0x0, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1);
+
+		Chip_Clock_Enable(CLK_MX_SSP1);
+	}
+}
+
+/* Initialize I2S interface for the board and UDA1380 */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint8_t uda1380_tx_data_buf[3];
+	Chip_I2S_Audio_Format_Type I2S_Config;
+	I2C_M_SETUP_Type I2C_Config;
+	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
+	I2C_Config.retransmissions_max = 5;
+	I2C_Config.tx_length = 3;
+	I2C_Config.tx_data = uda1380_tx_data_buf;
+	I2C_Config.rx_length = 0;
+	I2C_Config.rx_data = NULL;
+
+	/* Initialize I2C to the UDA1380 CODEC */
+	Chip_I2C_Init(LPC_I2C0);
+	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
+
+	I2S_Config.SampleRate = 48000;
+	I2S_Config.ChannelNumber = 2;	// 1 is mono, 2 is stereo
+	I2S_Config.WordWidth =  16;	// 8, 16 or 32 bits
+	Chip_I2S_Init(LPC_I2S0);
+	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
+	/* Enable Slave I2C operation */
+	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
+	/* Init UDA1380 CODEC */
+	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
+}
+
+/* FIXME */
+void Serial_CreateStream(void *Stream)
+{
+	// implement later
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h

@@ -0,0 +1,244 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_HITEX_EVA_18504350_H_
+#define __BOARD_HITEX_EVA_18504350_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_HITEX_EVA_18504350 LPC1850 and LPC4350 Hitex EVA board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_HITEX_EVA_18504350_OPTIONS BOARD: LPC1850 and LPC4350 Hitex EVA board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * USE_RMII:<br/>
+ *  - When defined, the system will be configured for RMII mode for Ethernet<br/>
+ *  - When not defined, the system will be configured for MII mode for Ethernet<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for Hitex boards, BOARD_HITEX_EVA_18504350 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * HITEX board defintion, can be used in examples for board specific code
+ */
+#define BOARD_HITEX_EVA_18504350
+
+/* For USBLIB examples */
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+#define BUTTONS_BUTTON1     0x01
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM   6
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM    21
+
+#define I2CDEV_PCA9502_ADDR     (0x9A >> 1)
+#define PCA9502_REG_IODIR       0x0A
+#define PCA9502_REG_IOSTATE     0x0B
+#define PCA9502_REG_IOINTENA    0x0C
+#define PCA9502_REG_IOCONTROL   0x0E
+#define PCA9502_REG_ADDR(x)     (((x) & 0x0F) << 3)
+
+/**
+ * Address of I2C device (UDA1380 CODEC) on board
+ */
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+/**
+ * Default location of LCD buffer is in DRAM
+ */
+#define FRAMEBUFFER_ADDR        0x28000000
+
+/**
+ * LCD configuration data
+ */
+extern const LCD_Config_Type EA320x240;
+
+/**
+ * Default LCD configuration data for examples
+ */
+#define BOARD_LCD EA320x240
+
+/**
+ * CODEC audio input sources
+ */
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize button(s) interface on board
+ * @return	Nothing
+ */
+void Board_Buttons_Init(void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus(void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	Nothing
+ */
+void Board_Joystick_Init(void);
+
+/**
+ * @brief	Returns joystick states on board
+ * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
+ */
+uint8_t Joystick_GetStatus(void);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Sets up board specific ADC interface
+ * @return	Nothing
+ */
+void Board_ADC_Init(void);
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initialize the LCD interface
+ * @return	Nothing
+ */
+void Board_LCD_Init(void);
+
+/**
+ * @brief	Initialize TSC2046 touchscreen controller
+ * @return	Nothing
+ */
+void Init_Touch_Controller(void);
+
+/**
+ * @brief	Get Touch coordinates
+ * @param	pX	: Pointer to x-Coord to populate
+ * @param	pY	: Pointer to y-Coord to populate
+ * @return	Nothing
+ */
+bool GetTouchPos(int16_t *pX, int16_t *pY);
+
+/**
+ * @brief	Initialize pin muxing for SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Initialize pin muxing for SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Initialize I2S interface for the board and UDA1380
+ * @param	I2Sx			: Pointer to I2S register interface used on this board
+ * @param	audio_in_sel	: Audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+/**
+ * @brief	FIXME
+ * @param	Stream	: FIXME
+ * @return	Nothing
+ */
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_HITEX_EVA_18504350_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c

@@ -0,0 +1,455 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_HITEX_EVA_18504350_SYSINIT LPC1850 and LPC4350 Hitex EVA board System Init code
+ * @ingroup BOARD_HITEX_EVA_18504350
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the Hitex EVA boards includes clock setup, default pin muxing, and
+ * memory configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1850 and LPC4350 Hitex EVA setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *   Sets up the external memory controller signals<BR>
+ *  Memory:<BR>
+ *   Sets up DRAM, static RAM, and NOR FLASH.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+#if defined(USE_RMII)
+	/* RMII pin group */
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+#else
+	/* MII pin group */
+	{0x1, 19, (MD_PLN | MD_EZI),                   FUNC0},
+	{0x0, 1,  (MD_PLN),                            FUNC6},
+	{0x1, 18, (MD_PLN),                            FUNC3},
+	{0x1, 20, (MD_PLN),                            FUNC3},
+	{0x1, 17, (MD_PLN | MD_EZI),                   FUNC3},
+	{0xC, 1,  (MD_PLN),                            FUNC3},
+	{0x1, 16, (MD_PLN | MD_EZI),                   FUNC7},
+	{0x1, 15, (MD_PLN | MD_EZI),                   FUNC3},
+	{0x0, 0,  (MD_PLN | MD_EZI),                   FUNC2},
+	{0x9, 4,  (MD_PLN),                            FUNC5},
+	{0x9, 5,  (MD_PLN),                            FUNC5},
+	{0xC, 0,  (MD_PLN | MD_EZI),                   FUNC3},
+	{0x9, 0,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 1,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 6,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 3,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 2,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0xC, 8,  (MD_PLN | MD_EZI),                   FUNC4},
+#endif
+	/* External data lines D0 .. D15 */
+	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	/* Address lines A0 .. A23 */
+	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* EMC control signals */
+	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
+	{0x6, 6,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
+	/* LCD interface, 24bpp */
+	{0x7, 7,  MD_PUP,                              FUNC3},
+	{0x4, 7,  MD_PUP,                              FUNC0},
+	{0x4, 5,  MD_PUP,                              FUNC2},
+	{0x4, 6,  MD_PUP,                              FUNC2},
+	{0x7, 6,  MD_PUP,                              FUNC3},
+	{0x4, 1,  MD_PUP,                              FUNC2},
+	{0x4, 4,  MD_PUP,                              FUNC2},
+	{0x4, 2,  MD_PUP,                              FUNC2},
+	{0x8, 7,  MD_PUP,                              FUNC3},
+	{0x8, 6,  MD_PUP,                              FUNC3},
+	{0x8, 5,  MD_PUP,                              FUNC3},
+	{0x8, 4,  MD_PUP,                              FUNC3},
+	{0x7, 5,  MD_PUP,                              FUNC3},
+	{0x4, 8,  MD_PUP,                              FUNC2},
+	{0x4, 10, MD_PUP,                              FUNC2},
+	{0x4, 9,  MD_PUP,                              FUNC2},
+	{0x8, 3,  MD_PUP,                              FUNC3},
+	{0xB, 6,  MD_PUP,                              FUNC2},
+	{0xB, 5,  MD_PUP,                              FUNC2},
+	{0xB, 4,  MD_PUP,                              FUNC2},
+	{0x7, 4,  MD_PUP,                              FUNC3},
+	{0x7, 2,  MD_PUP,                              FUNC3},
+	{0x7, 1,  MD_PUP,                              FUNC3},
+	{0xB, 3,  MD_PUP,                              FUNC2},
+	{0xB, 2,  MD_PUP,                              FUNC2},
+	{0xB, 1,  MD_PUP,                              FUNC2},
+	{0xB, 0,  MD_PUP,                              FUNC2},
+	{0x7, 0,  MD_PUP,                              FUNC3},
+	{0x4, 4,  MD_PUP,                              FUNC0},
+	{0x7, 3,  MD_PUP,                              FUNC0},
+	{0x4, 1,  MD_PUP,                              FUNC0},
+	/* Board LEDs */
+	{0x8, 1,  MD_PDN,                              FUNC0},
+	{0xE, 6,  MD_PDN,                              FUNC4},	/* GPIO7.6, green */
+	{0xE, 8,  MD_PDN,                              FUNC4},	/* GPIO7.8, blue */
+	{0xE, 5,  MD_PDN,                              FUNC4},	/* GPIO7.5, red */
+	/* Board ADC */
+	{0xF, 9,  MD_PLN,                              FUNC7},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* EMC clock delay */
+#define CLK0_DELAY 7
+
+/* Hitex SDRAM timing and chip Config */
+STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = {
+	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
+	0x01,	/* Command Delayed */
+	EMC_NANOSECOND(20),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(63),
+	EMC_CLOCK(0x05),
+	EMC_CLOCK(0x05),
+	EMC_CLOCK(0x04),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(14),
+	EMC_CLOCK(0x02),
+	{
+		{
+			EMC_ADDRESS_DYCS0,	/* Hitex Board uses DYCS0 for SDRAM */
+			3,	/* RAS */
+
+			EMC_DYN_MODE_WBMODE_PROGRAMMED |
+			EMC_DYN_MODE_OPMODE_STANDARD |
+			EMC_DYN_MODE_CAS_3 |
+			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
+			EMC_DYN_MODE_BURST_LEN_8,
+
+			EMC_DYN_CONFIG_DATA_BUS_16 |
+			EMC_DYN_CONFIG_LPSDRAM |
+			EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
+			EMC_DYN_CONFIG_MD_SDRAM
+		},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0}
+	}
+};
+
+/* Hitex Static RAM timing and chip Config */
+STATIC const IP_EMC_STATIC_CONFIG_Type IS62WV25616_config = {
+	2,
+	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(30),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(55),
+	EMC_NANOSECOND(55),
+	EMC_NANOSECOND(55)
+};
+
+/* Hitex NorFlash timing and chip Config */
+STATIC const IP_EMC_STATIC_CONFIG_Type SST39VF320_config = {
+	0,
+	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(35),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(40),
+	EMC_CLOCK(4)
+};
+
+/* Setup external memories */
+STATIC void SystemSetupMemory(void)
+{
+	/* Setup EMC Delays */
+	/* Move all clock delays together */
+	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
+
+	/* Setup EMC Clock Divider for divide by 2 */
+	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
+	LPC_CREG->CREG6 |= (1 << 16);
+	Chip_Clock_Enable(CLK_MX_EMC);
+
+	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
+	Chip_EMC_Init(1, 0, 0);
+	/* Init EMC Dynamic Controller */
+	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
+	/* Init EMC Static Controller CS2 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
+	/* Init EMC Static Controller CS0 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
+
+	/* Enable Buffer for External Flash */
+	LPC_EMC->STATICCONFIG0 |= 1 << 19;
+}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ *			SystemInit() is called prior to the application and sets up system
+ *			clocking, memory, and any resources needed prior to the application
+ *			starting.
+ * @return	none
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_keil_mcb_18574357.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c

@@ -0,0 +1,841 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+#include "string.h"
+
+/* Keil board uses 83848 PHY and retarget */
+#include "lpc_phy_dp83848.c"
+#include "retarget.c"
+
+/** @ingroup BOARD_KEIL_MCB_18574357
+ * @{
+ */
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+/* Port and bit mapping for LEDs on GPIOs */
+static const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
+static const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
+
+/** UDA specified variables */
+/* System Register Data Set */
+uint16_t UDA_sys_regs_dat[] = {
+	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
+	UDA1380_REG_I2S_DEFAULT_VALUE,
+	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
+	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
+	UDA1380_REG_HEADAMP_DEFAULT_VALUE
+};
+
+/* System Register Data Set */
+uint16_t UDA_interfil_regs_dat[] = {
+	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
+	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
+	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
+	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
+	UDA1380_REG_MIXSDO_DEFAULT_VALUE
+};
+/* decimator Register Data Set */
+uint16_t UDA_decimator_regs_dat[] = {
+	UDA1380_REG_DECVOL_DEFAULT_VALUE,
+	UDA1380_REG_PGA_DEFAULT_VALUE,
+	UDA1380_REG_ADC_DEFAULT_VALUE,
+	UDA1380_REG_AGC_DEFAULT_VALUE
+};
+
+/** Private definitions for LCD */
+#define LCD_CS(x) ((x) ? (Chip_GPIO_WritePortBit(7, 16, true)) : (Chip_GPIO_WritePortBit(7, 16, false)))
+
+/** Private variables for LCD */
+uint32_t g_isPenDn;
+uint32_t g_isNewPenDn;
+const int32_t ad_left = 3813;
+const int32_t ad_top = 3805;// 237;
+const int32_t ad_right = 360;
+const int32_t ad_bottom = 237;	// 3805;
+
+const LCD_Config_Type MCB4300_LCD = {
+	8,						/*!< Horizontal back porch in clocks */
+	4,						/*!< Horizontal front porch in clocks */
+	4,						/*!< HSYNC pulse width in clocks */
+	240,					/*!< Pixels per line */
+	4,						/*!< Vertical back porch in clocks */
+	3,						/*!< Vertical front porch in clocks */
+	4,						/*!< VSYNC pulse width in clocks */
+	320,					/*!< Lines per panel */
+	0,						/*!< Invert output enable, 1 = invert */
+	1,						/*!< Invert panel clock, 1 = invert */
+	1,						/*!< Invert HSYNC, 1 = invert */
+	1,						/*!< Invert VSYNC, 1 = invert */
+	1,						/*!< AC bias frequency in clocks (not used) */
+	6,						/*!< Maximum bits per pixel the display supports */
+	LCD_TFT,				/*!< LCD panel type */
+	LCD_COLOR_FORMAT_RGB,	/*!< BGR or RGB */
+	0						/*!< Dual panel, 1 = dual panel display */
+};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Very simple (inaccurate) delay function */
+static void delay(uint32_t i) {
+	while (i--) {}
+}
+
+/* Write data to UDA register */
+static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
+
+	I2C_Config->tx_data[0] = reg;
+	I2C_Config->tx_data[1] = value >> 8;
+	I2C_Config->tx_data[2] = value & 0xFF;
+	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
+	delay(10000);
+}
+
+/* Read data from UDA register */
+static uint16_t UDA_Reg_read(UDA1380_REG reg) {
+	uint8_t rx_data[2];
+	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
+	return rx_data[0] << 8 | rx_data[1];
+}
+
+/* Initializes default settings for UDA1380 */
+static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint16_t temp;
+	uint8_t  i;
+	/* Reset UDA1380 on board Keil */
+	Chip_SCU_PinMux(0x8, 0, MD_PUP, FUNC0);
+	Chip_GPIO_WriteDirBit(4, 0, true);
+	Chip_GPIO_WritePortBit(4, 0, true);
+	/* delay 1us */
+	delay(100000);
+	Chip_GPIO_WritePortBit(4, 0, false);
+	delay(100000);
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
+		if (temp != UDA_sys_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	/* interfilter regs init */
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
+		if (temp != UDA_interfil_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+	/* decimator regs init */
+	for (i = 0; i < 4; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
+		if (temp != UDA_decimator_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
+		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
+		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
+					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
+					  I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+	}
+	return SUCCESS;
+
+}
+
+/** Private functions for LCD controller */
+/* Write to LCD controller, with A0 = 0 */
+static void LCD_X_Write00_16(uint16_t c) {
+
+	uint8_t buf[1];
+	LCD_CS(0);
+	buf[0] = 0x70;
+	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);	// Start + WR Register
+	buf[0] = (uint8_t) (c);
+	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
+	LCD_CS(1);
+}
+
+/* Write to LCD controller, with A0 = 1 */
+static void LCD_X_Write01_16(uint16_t c) {
+
+	uint8_t buf[1];
+	LCD_CS(0);
+	buf[0] = 0x72;
+	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);	/* Start + WR Data */
+	buf[0] = (uint8_t) (c >> 8);
+	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
+	buf[0] = (uint8_t) (c);
+	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
+	LCD_CS(1);
+}
+
+/* Write to LCD controller's register */
+static void wr_reg(uint16_t reg, uint16_t dat) {
+	LCD_X_Write00_16(reg);
+	LCD_X_Write01_16(dat);
+}
+
+/* Pin configuration to communicate with LCD Controller */
+static void pinConfig(void)
+{
+	/* (DC) */
+	Chip_GPIO_WriteDirBit(7, 16, true);
+	// Chip_Clock_EnableOpts(sspclk, true, true, 1);
+}
+
+/* Writes a value to the STMPE811 register */
+static uint32_t Board_TSC_WriteReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t value)
+{
+	return Chip_I2C_MasterWriteReg(I2Cx, TSC_I2C_ADDR, regAddr, &value, 1);
+}
+
+/* Reads a value to the STMPE811 register */
+static uint32_t Board_TSC_ReadReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t *value)
+{
+	return Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, regAddr, value, 1);
+}
+
+/* Check if touch is detected or not */
+static bool Board_TSC_TouchDetect(IP_I2C_001_Type *I2Cx)
+{
+	uint8_t  CtrRegVal = 0;
+
+	if (Board_TSC_ReadReg(I2Cx, TSC_CTRL, &CtrRegVal) == 1) {
+		if (CtrRegVal & (1 << 7)) {
+			return true;
+		}
+	}
+	return false;
+}
+
+/* Get the touch coordinates from STMPE811 registers */
+static Status Board_TSC_GetTouchCoord(IP_I2C_001_Type *I2Cx, int16_t *x, int16_t *y)
+{
+	uint8_t fifo_size, tscData[4], i;
+
+	/* Read all samples except the last one */
+	Board_TSC_ReadReg(I2Cx, FIFO_SIZE, &fifo_size);
+	for (i = 0; i < fifo_size; ++i)
+		if (Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4) == 0) {
+			return ERROR;
+		}
+
+	/* Retrieve last taken sample */
+	Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4);
+	*x = (tscData[0] << 4) | ((tscData[1] & 0xF0) >> 4);
+	*y = ((tscData[1] & 0x0F) << 8) | tscData[2];
+
+	/* Clear interrupt flags */
+	Board_TSC_WriteReg(I2Cx, INT_STA, 0x1F);
+
+	return SUCCESS;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
+}
+
+/* Initialize UART pins */
+void Board_UART_Init(LPC_USART_Type *UARTx)
+{
+	if (UARTx == LPC_USART0) {
+		Chip_SCU_PinMux(0x2, 0, MD_PDN, FUNC1);		/* P2.0 : UART0_TXD */
+		Chip_SCU_PinMux(0x2, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1);	/* P2.1 : UART0_RXD */
+	}
+	else if (UARTx == LPC_USART3) {
+		Chip_SCU_PinMux(0x2, 3, MD_PDN, FUNC2);			/* P2.3 : UART3_TXD */
+		Chip_SCU_PinMux(0x2, 4, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P2.4 : UART3_RXD */
+	}
+}
+
+/* Initialize debug output via UART for board */
+void Board_Debug_Init(void)
+{
+#if defined(DEBUG_UART)
+	Board_UART_Init(DEBUG_UART);
+
+	Chip_UART_Init(DEBUG_UART);
+	Chip_UART_SetBaud(DEBUG_UART, 115200);
+	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
+
+	/* Enable UART Transmit */
+	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
+#endif
+}
+
+/* Sends a character on the UART */
+void Board_UARTPutChar(char ch)
+{
+#if defined(DEBUG_UART)
+	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
+#endif
+}
+
+/* Gets a character from the UART, returns EOF if no character is ready */
+int Board_UARTGetChar(void)
+{
+#if defined(DEBUG_UART)
+	uint8_t data;
+
+	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
+		return (int) data;
+	}
+#endif
+	return EOF;
+}
+
+/* Outputs a string on the debug UART */
+void Board_UARTPutSTR(char *str)
+{
+#if defined(DEBUG_UART)
+	while (*str != '\0') {
+		Board_UARTPutChar(*str++);
+	}
+#endif
+}
+
+/* Initializes board LED(s) */
+void Board_LED_Init()
+{
+	int i;
+
+	/* Must make sure J21 is installed to enabled LEDs */
+	/* PD.10 : LED 0 (leftmost) */
+	/* PD.11 : LED 1 */
+	/* PD.12 : LED 2 */
+	/* PD.13 : LED 3 */
+	/* PD.14 : LED 4 */
+	/* P9.0  : LED 5 */
+	/* P9.1  : LED 6 */
+	/* P9.2  : LED 7 (rightmost) */
+	for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) {
+		Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true);
+	}
+}
+
+#ifndef BOARD_LED_TEST_FUNCTION_WORKS
+	/* FIXME: temporary code for toggle LED support only */
+	static uint8_t LEDStates; /* shadow variable for LED states */
+#endif
+
+/* Sets the state of a board LED to on or off */
+void Board_LED_Set(uint8_t LEDNumber, bool On)
+{
+	if (LEDNumber <= 7) {
+		Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], On);
+#ifndef BOARD_LED_TEST_FUNCTION_WORKS
+		if (On) {
+			LEDStates |= (1 << LEDNumber); /* set the state */
+		} else {
+			LEDStates &= ~(1 << LEDNumber); /* clear the state */
+		}
+#endif		
+	}
+}
+
+/* Returns the current state of a board LED */
+bool Board_LED_Test(uint8_t LEDNumber)
+{
+	if (LEDNumber <= 7) {
+#ifndef BOARD_LED_TEST_FUNCTION_WORKS
+	if (LEDStates & (1 << LEDNumber)) { /* LED is on */
+		return true;
+	} else { /* LED is off */
+		return false;
+	}
+#else		
+		return (bool)Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]);
+#endif	
+	}
+	return false;
+}
+
+/* Returns the MAC address assigned to this board */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr)
+{
+	const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
+
+	memcpy(mcaddr, boardmac, 6);
+}
+
+/* Set up and initialize all required blocks and functions related to the
+   board hardware */
+void Board_Init(void)
+{
+	/* Sets up DEBUG UART */
+	DEBUGINIT();
+
+	/* Updates SystemCoreClock global var with current clock speed */
+	SystemCoreClockUpdate();
+
+	/* Initializes GPIO */
+	Chip_GPIO_Init();
+
+	/* Setup GPIOs for USB demos */
+	Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2);			/* P9_5 USB1_VBUS_EN, USB1 VBus function */
+	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	/* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
+	Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1);			/* P6_3 USB0_PWR_EN, USB0 VBus function */
+}
+
+/* Sets up board specific ADC interface */
+void Board_ADC_Init(void)
+{}
+
+/* Sets up board specific I2C interface */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C1) {
+		/* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */
+		Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2);
+		Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2);
+	}
+}
+
+/* Sets up board specific I2S interface and UDA1380 */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint8_t uda1380_tx_data_buf[3];
+	Chip_I2S_Audio_Format_Type I2S_Config;
+	I2C_M_SETUP_Type I2C_Config;
+	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
+	I2C_Config.retransmissions_max = 5;
+	I2C_Config.tx_length = 3;
+	I2C_Config.tx_data = uda1380_tx_data_buf;
+	I2C_Config.rx_length = 0;
+	I2C_Config.rx_data = NULL;
+
+	/* Initialize I2C peripheral ------------------------------------*/
+	/* Init I2C */
+	Chip_I2C_Init(LPC_I2C0);
+	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
+
+	I2S_Config.SampleRate = 48000;
+	I2S_Config.ChannelNumber = 2;	/* 1 is mono, 2 is stereo */
+	I2S_Config.WordWidth =  16;		/* 8, 16 or 32 bits */
+	Chip_I2S_Init(LPC_I2S0);
+	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
+	/* Enable Slave I2C operation */
+	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
+	/* Init UDA1380 CODEC */
+	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
+}
+
+/* Initialize the LCD interface */
+void Board_LCD_Init(void)
+{
+	/* LCD with HX8347-D LCD Controller                                         */
+	SSP_ConfigFormat ssp_format1;
+	/* Attach main PLL clock to divider A with a divider of 2 */
+	Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2);
+
+	/* Route divider A output to LCD base clock and enable base clock */
+	Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false);
+
+	/* Reset LCD and wait for reset to complete */
+	Chip_RGU_TriggerReset(RGU_LCD_RST);
+	while (Chip_RGU_InReset(RGU_LCD_RST)) {}
+
+	/* Set backlight GPIO as an output */
+	Chip_GPIO_WriteDirBit(3, 8, true);
+
+	delay(5);
+
+	pinConfig();
+	// Chip_Clock_EnablePeripheralMax(SSP_ID);
+	/* TBD Externally */
+	Chip_SSP_Init(SSP_ID);
+	//	NVIC_EnableIRQ(SSP_ID);
+	Chip_SSP_Set_Master(SSP_ID, true);
+	Chip_SSP_Set_BitRate(SSP_ID, 1000000);
+
+	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
+	ssp_format1.bits = SSP_BITS_8;
+	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
+
+	Chip_SSP_Set_Format(SSP_ID, &ssp_format1);
+	Chip_SSP_Cmd(SSP_ID, ENABLE);
+
+	delay(200);
+
+	/* Driving ability settings ------------------------------------------------*/
+	wr_reg(0xEA, 0x00);					/* Power control internal used (1)    */
+	wr_reg(0xEB, 0x20);					/* Power control internal used (2)    */
+	wr_reg(0xEC, 0x0C);					/* Source control internal used (1)   */
+	wr_reg(0xED, 0xC7);					/* Source control internal used (2)   */
+	wr_reg(0xE8, 0x38);					/* Source output period Normal mode   */
+	wr_reg(0xE9, 0x10);					/* Source output period Idle mode     */
+	wr_reg(0xF1, 0x01);					/* RGB 18-bit interface ;0x0110       */
+	wr_reg(0xF2, 0x10);
+
+	/* Adjust the Gamma Curve --------------------------------------------------*/
+	wr_reg(0x40, 0x01);
+	wr_reg(0x41, 0x00);
+	wr_reg(0x42, 0x00);
+	wr_reg(0x43, 0x10);
+	wr_reg(0x44, 0x0E);
+	wr_reg(0x45, 0x24);
+	wr_reg(0x46, 0x04);
+	wr_reg(0x47, 0x50);
+	wr_reg(0x48, 0x02);
+	wr_reg(0x49, 0x13);
+	wr_reg(0x4A, 0x19);
+	wr_reg(0x4B, 0x19);
+	wr_reg(0x4C, 0x16);
+
+	wr_reg(0x50, 0x1B);
+	wr_reg(0x51, 0x31);
+	wr_reg(0x52, 0x2F);
+	wr_reg(0x53, 0x3F);
+	wr_reg(0x54, 0x3F);
+	wr_reg(0x55, 0x3E);
+	wr_reg(0x56, 0x2F);
+	wr_reg(0x57, 0x7B);
+	wr_reg(0x58, 0x09);
+	wr_reg(0x59, 0x06);
+	wr_reg(0x5A, 0x06);
+	wr_reg(0x5B, 0x0C);
+	wr_reg(0x5C, 0x1D);
+	wr_reg(0x5D, 0xCC);
+
+	/* Power voltage setting ---------------------------------------------------*/
+	wr_reg(0x1B, 0x1B);
+	wr_reg(0x1A, 0x01);
+	wr_reg(0x24, 0x2F);
+	wr_reg(0x25, 0x57);
+	wr_reg(0x23, 0x88);
+
+	/* Power on setting --------------------------------------------------------*/
+	wr_reg(0x18, 0x36);					/* Internal oscillator frequency adj  */
+	wr_reg(0x19, 0x01);					/* Enable internal oscillator         */
+	wr_reg(0x01, 0x00);					/* Normal mode, no scrool             */
+	wr_reg(0x1F, 0x88);					/* Power control 6 - DDVDH Off        */
+	delay(20);
+	wr_reg(0x1F, 0x82);					/* Power control 6 - Step-up: 3 x VCI */
+	delay(5);
+	wr_reg(0x1F, 0x92);					/* Power control 6 - Step-up: On      */
+	delay(5);
+	wr_reg(0x1F, 0xD2);					/* Power control 6 - VCOML active     */
+	delay(5);
+
+	/* Color selection ---------------------------------------------------------*/
+	wr_reg(0x17, 0x55);					/* RGB, System interface: 16 Bit/Pixel*/
+	wr_reg(0x00, 0x00);					/* Scrolling off, no standby          */
+
+	/* Interface config --------------------------------------------------------*/
+	wr_reg(0x2F, 0x11);					/* LCD Drive: 1-line inversion        */
+	wr_reg(0x31, 0x02);					/* Value for SPI: 0x00, RBG: 0x02     */
+	wr_reg(0x32, 0x00);					/* DPL=0, HSPL=0, VSPL=0, EPL=0       */
+
+	/* Display on setting ------------------------------------------------------*/
+	wr_reg(0x28, 0x38);					/* PT(0,0) active, VGL/VGL            */
+	delay(20);
+	wr_reg(0x28, 0x3C);					/* Display active, VGL/VGL            */
+
+	wr_reg(0x16, 0x00);					/* Mem Access Control (MX/Y/V/L,BGR)  */
+
+	/* Display scrolling settings ----------------------------------------------*/
+	wr_reg(0x0E, 0x00);					/* TFA MSB                            */
+	wr_reg(0x0F, 0x00);					/* TFA LSB                            */
+	wr_reg(0x10, 320 >> 8);				/* VSA MSB                            */
+	wr_reg(0x11, 320 &  0xFF);			/* VSA LSB                            */
+	wr_reg(0x12, 0x00);					/* BFA MSB                            */
+	wr_reg(0x13, 0x00);					/* BFA LSB                            */
+
+}
+
+/* Initializes the STMPE811 touch screen controller */
+void Init_Touch_Controller(void)
+{
+	volatile int32_t i;
+
+	/* Init I2C */
+	Chip_I2C_Init(LPC_I2C0);
+	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
+
+	/* Enable Slave I2C operation */
+	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
+
+	/* Reset Touch-screen controller	    */
+	Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL1, 0x02);
+
+	for (i = 0; i < 200000; i++) {}
+
+	/* Enable TSC and ADC                 */
+	Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL2, 0x0C);
+	/* Enable Touch detect, FIFO          */
+	Board_TSC_WriteReg(LPC_I2C0, INT_EN, 0x07);
+	/* Set sample time , 12-bit mode      */
+	Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL1, 0x69);
+
+	for (i = 0; i < 40000; i++) {}
+
+	/* ADC frequency 3.25 MHz             */
+	Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL2, 0x01);
+	/* Tracking index: 8, operation mode : XY only */
+	Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x22);
+	/* Detect delay 10us Settle time 500us*/
+	Board_TSC_WriteReg(LPC_I2C0, TSC_CFG, 0xC2);
+	/* Threshold for FIFO                 */
+	Board_TSC_WriteReg(LPC_I2C0, FIFO_TH, 0x01);
+	/* FIFO reset                         */
+	Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x01);
+	/* FIFO not reset	                   */
+	Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x00);
+	/* Drive 50 mA typical	              */
+	Board_TSC_WriteReg(LPC_I2C0, TSC_I_DRIVE, 0x01);
+	/* Pins are used for touchscreen	    */
+	Board_TSC_WriteReg(LPC_I2C0, GPIO_ALT_FUNCT, 0x00);
+	/* Enable TSC	                       */
+	Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x01);
+	/* Clear interrupt status	           */
+	Board_TSC_WriteReg(LPC_I2C0, INT_STA, 0xFF);
+}
+
+/* Get touch screen position */
+bool GetTouchPos(int16_t *pX, int16_t *pY)
+{
+	int16_t x, y, rng;
+	if (Board_TSC_TouchDetect(LPC_I2C0)) {
+		Board_TSC_GetTouchCoord(LPC_I2C0, &x, &y);
+		g_isPenDn = 1;
+		g_isNewPenDn = 1;
+
+		/* calibrate X */
+		rng = ad_right - ad_left;
+		if (rng < 0) {
+			rng = -rng;
+		}
+		x -= (ad_right < ad_left) ? ad_right : ad_left;
+		*pX = (x * C_GLCD_H_SIZE) / rng;
+		if (ad_left > ad_right) {
+			*pX = C_GLCD_H_SIZE - *pX;
+		}
+
+		/* calibrate Y */
+		rng = ad_bottom - ad_top;
+		if (rng < 0) {
+			rng = -rng;
+		}
+		y -= (ad_bottom < ad_top) ? ad_bottom : ad_top;
+		*pY = (y * C_GLCD_V_SIZE) / rng;
+		if (ad_top > ad_bottom) {
+			*pY = C_GLCD_V_SIZE - *pY;
+		}
+	}
+	else {
+		g_isPenDn = 0;
+	}
+
+	if (g_isNewPenDn) {
+		g_isNewPenDn = 0;
+		if (*pX < 0) {
+			*pX = -*pX;
+		}
+		if (*pY < 0) {
+			*pY = -*pY;
+		}
+		return true;
+	}
+	return false;
+}
+
+/* Turn on LCD backlight */
+void Board_LCD_Set_Backlight(uint8_t Intensity)
+{
+	bool OnOff = (bool) (Intensity != 0);
+
+	Chip_GPIO_WritePortBit(3, 8, OnOff);
+}
+
+/* Interrupt handler for GPIO0 */
+void GPIO0_IRQHandler(void)
+{
+	static bool On;
+
+	if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
+		Chip_GPIO_IntClear(0, 0);
+		On = (bool) !On;
+		Board_LED_Set(1, On);
+	}
+}
+
+/* Initializes board specific GPIO Interrupt */
+void Board_GPIO_Int_Init()
+{
+	Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0);	/* PF.9 : POTI button */
+	Chip_GPIO_WriteDirBit(7, 23, false);	/* PF.9 -> GPIO7[23] : input */
+	Chip_SCU_GPIOIntPinSel(0, 7, 23);
+	Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE);	/* Configure GPIO0[7] to interrupt pin (SW2 switch) */
+
+	NVIC_EnableIRQ(PIN_INT0_IRQn);	/* enable GPIO interrupt 0 */
+}
+
+/* Initializes SDMMC interface */
+void Board_SDMMC_Init(void)
+{
+	Chip_SCU_PinMux(0xC, 4, MD_PLN_FAST, FUNC7);	/* PC.4 connected to SDIO_D0 */
+	Chip_SCU_PinMux(0xC, 5, MD_PLN_FAST, FUNC7);	/* PC.5 connected to SDIO_D1 */
+	Chip_SCU_PinMux(0xC, 6, MD_PLN_FAST, FUNC7);	/* PC.6 connected to SDIO_D2 */
+	Chip_SCU_PinMux(0xC, 7, MD_PLN_FAST, FUNC7);	/* PC.7 connected to SDIO_D3 */
+
+	Chip_SCU_PinMux(0xC, 8, MD_PLN | MD_EZI, FUNC7);/* PC.4 connected to SDIO_CD */
+	Chip_SCU_PinMux(0xC, 10, MD_PLN_FAST, FUNC7);	/* PC.10 connected to SDIO_CMD */
+	Chip_SCU_PinMux(0xC, 0, MD_PLN | MD_EHS, FUNC7);/* PC.0 connected to SDIO_CLK */
+}
+
+/* Initializes SSP interface */
+void Board_SSP_Init(LPC_SSP_Type *SSPx)
+{
+	if (SSPx == LPC_SSP0) {
+		/* Set up clock and power for SSP0 module */
+		/* Configure SSP0 pins*/
+		Chip_SCU_PinMux(0x3, 3, MD_PLN_FAST, FUNC2);	/* P3.3 connected to SCL/SCLK	func2=SSP0 SCK0 */
+		Chip_SCU_PinMux(0x3, 6, MD_PLN_FAST, FUNC2);	/* P3.6 connected to nCS		func2=SSP0 SSEL0 */
+		Chip_SCU_PinMux(0x3, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P3.7 connected to SO		func2=SSP0 MISO0 */
+		Chip_SCU_PinMux(0x3, 8, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P3.8 connected to nSI	func2=SSP0 MOSI0 */
+
+		Chip_Clock_EnableOpts(CLK_MX_SSP0, true, true, 1);
+	}
+	else if (SSPx == LPC_SSP1) {
+		/* Set up clock and power for SSP1 module */
+		/* Configure SSP1 pins*/
+		Chip_SCU_PinMux(0xF, 4, MD_PLN_FAST, FUNC0);	/* PF.4 connected to SCL/SCLK	func0 = SSP1 SCK1 */
+		Chip_SCU_PinMux(0xF, 5, MD_PLN_FAST, FUNC2);	/* PF.5 connected to nCS		func2 = SSP1 SSEL1 */
+		Chip_SCU_PinMux(0xF, 6, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PF.6 connected to SO			  func2 = SSP1 MISO1 */
+		Chip_SCU_PinMux(0xF, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PF.7 connected to nSI		  func2 = SSP1 MOSI1 */
+
+		Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
+	}
+	else {
+		return;
+	}
+}
+
+/* Initializes board specific buttons */
+void Board_Buttons_Init(void)
+{
+	Chip_SCU_PinMux(0x4,  0, MD_PUP | MD_EZI | MD_ZI, FUNC0);	/* P9.1  : LED 6 */
+	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false);
+}
+
+/* Sets up default states for joystick */
+void Board_Joystick_Init(void)
+{
+	Chip_SCU_PinMux(0xC, 9, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_9  as GPIO6[8] */
+	Chip_SCU_PinMux(0xC, 11, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_11 as GPIO6[10] */
+	Chip_SCU_PinMux(0xC, 12, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_12 as GPIO6[11] */
+	Chip_SCU_PinMux(0xC, 13, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_13 as GPIO6[12] */
+	Chip_SCU_PinMux(0xC, 14, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_14 as GPIO6[13] */
+
+	Chip_GPIO_WriteDirBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM, false);		/* input */
+	Chip_GPIO_WriteDirBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM, false);	/* input */
+	Chip_GPIO_WriteDirBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM, false);	/* input */
+	Chip_GPIO_WriteDirBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM, false);	/* input */
+	Chip_GPIO_WriteDirBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM, false);	/* input */
+}
+
+/* Gets joystick status */
+uint8_t Joystick_GetStatus(void)
+{
+
+	uint8_t ret = NO_BUTTON_PRESSED;
+
+	if (Chip_GPIO_ReadPortBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM) == 0) {
+		ret |= JOY_UP;
+	}
+	else if (Chip_GPIO_ReadPortBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM) == 0) {
+		ret |= JOY_DOWN;
+	}
+	else if (Chip_GPIO_ReadPortBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM) == 0) {
+		ret |= JOY_LEFT;
+	}
+	else if (Chip_GPIO_ReadPortBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM) == 0) {
+		ret |= JOY_RIGHT;
+	}
+	else if (Chip_GPIO_ReadPortBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM) == 0) {
+		ret |= JOY_PRESS;
+	}
+
+	return ret;
+}
+
+/* Gets buttons status */
+uint32_t Buttons_GetStatus(void)
+{
+	uint8_t ret = NO_BUTTON_PRESSED;
+
+	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
+		ret |= BUTTONS_BUTTON1;
+	}
+	return ret;
+}
+
+/* FIXME Should we remove this function? */
+void Serial_CreateStream(void *Stream)
+{
+	// implement later
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h

@@ -0,0 +1,304 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_KEIL_MCB_18574357_H_
+#define __BOARD_KEIL_MCB_18574357_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_KEIL_MCB_18574357 LPC1857 and LPC4357 Keil MCB board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_KEIL_MCB_18574357_OPTIONS BOARD: LPC1857 and LPC4357 Keil MCB board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for Keil boards, BOARD_KEIL_MCB_18574357 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#define BOARD_KEIL_MCB_18574357
+
+#define LED_NUMBER_OF 1
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM			2
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM			0
+#define JOYSTICK_UP_GPIO_PORT_NUM               6
+#define JOYSTICK_UP_GPIO_BIT_NUM                10
+#define JOYSTICK_DOWN_GPIO_PORT_NUM             6
+#define JOYSTICK_DOWN_GPIO_BIT_NUM              11
+#define JOYSTICK_LEFT_GPIO_PORT_NUM             6
+#define JOYSTICK_LEFT_GPIO_BIT_NUM              12
+#define JOYSTICK_RIGHT_GPIO_PORT_NUM            6
+#define JOYSTICK_RIGHT_GPIO_BIT_NUM             13
+#define JOYSTICK_PRESS_GPIO_PORT_NUM            6
+#define JOYSTICK_PRESS_GPIO_BIT_NUM             8
+
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1     0x01
+
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+
+/** UDA1380 register values */
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
+#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
+
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE	(1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE	( 1 << 9 | 2)
+
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE	(2 << 8 | 2)
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE	0x0000
+
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE	0xE4E4			/* Decrease Volume -28dB */
+#define UDA1380_REG_PGA_DEFAULT_VALUE		0x0000
+#define UDA1380_REG_ADC_DEFAULT_VALUE		0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
+#define UDA1380_REG_AGC_DEFAULT_VALUE		0x0000
+
+#define UDA1380_REG_L3_DEFAULT_VALUE		0x0000
+
+/* UDA1380 address */
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+/* UDA1380 Register Address */
+typedef enum {
+	UDA_EVALM_CLK = 0x00,
+	UDA_BUS_CTRL,
+	UDA_POWER_CTRL,
+	UDA_ANALOG_CTRL,
+	UDA_HPAMP_CTRL,
+	UDA_MASTER_VOL_CTRL = 0x10,
+	UDA_MIXER_VOL_CTRL,
+	UDA_MODE_CTRL,
+	UDA_MUTE_CTRL,
+	UDA_MIXER_FILTER_CTRL,
+	UDA_DEC_VOL_CTRL = 0x20,
+	UDA_PGA_CTRL,
+	UDA_ADC_CTRL,
+	UDA_AGC_CTRL,
+	UDA_TOTAL_REG
+} UDA1380_REG;
+
+/* Frame buffer address for lcd */
+#define FRAMEBUFFER_ADDR        0x28000000
+
+extern const LCD_Config_Type MCB4300_LCD;
+#define BOARD_LCD MCB4300_LCD
+
+/** Audio input select structure */
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/** LCD controller definitions */
+#define SSP_ID LPC_SSP0
+#define C_GLCD_H_SIZE   240
+#define C_GLCD_V_SIZE   320
+
+/** Private types/definitions for touch screen controller (STMPE811) */
+
+#define TSC_I2C_ADDR    (0x82 >> 1)	/* Touchscreen 7-bit I2C address */
+
+/** STMPE811 Register addresses */
+#define SYS_CTRL1       0x03
+#define SYS_CTRL2       0x04
+#define INT_CTRL        0x09
+#define INT_EN          0x0A
+#define INT_STA         0x0B
+#define GPIO_ALT_FUNCT  0x17
+#define ADC_CTRL1       0x20
+#define ADC_CTRL2       0x21
+#define TSC_CTRL        0x40
+#define TSC_CFG         0x41
+#define FIFO_TH         0x4A
+#define FIFO_STA        0x4B
+#define FIFO_SIZE       0x4C
+#define DATA_X          0x4D
+#define DATA_Y          0x4F
+#define DATA_Z          0x51
+#define TSC_FRACTION_Z  0x56
+#define TSC_I_DRIVE     0x58
+#define TSC_SHIELD      0x59
+#define DATA_XYZ        0xD7
+
+/**
+ * @brief	Sets up board specific ADC interface
+ * @return	Nothing
+ */
+void Board_ADC_Init(void);
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initializes board specific GPIO Interrupt
+ * @return	Nothing
+ */
+void Board_GPIO_Int_Init(void);
+
+/**
+ * @brief	Sets up board specific SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Sets up board specific SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr	: Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize the LCD interface
+ * @return	Nothing
+ */
+void Board_LCD_Init(void);
+
+/**
+ * @brief	Initializes the STMPE811 touch screen controller
+ * @return	Nothing
+ */
+void Init_Touch_Controller(void);
+
+/**
+ * @brief	Get touch screen position
+ * @param	pX	: pointer to X position
+ * @param	pY	: pointer to Y position
+ * @return	true if touch is detected or false if otherwise
+ */
+bool GetTouchPos(int16_t *pX, int16_t *pY);
+
+/**
+ * @brief	Initializes board specific buttons
+ * @return	Nothing
+ */
+void Board_Buttons_Init (void);
+
+/**
+ * @brief	Initializes board specific joystick
+ * @return	Nothing
+ */
+void Board_Joystick_Init (void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	joystick status: up, down, left or right
+ */
+uint8_t Joystick_GetStatus (void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus(void);
+
+/**
+ * @brief	Sets up board specific I2S interface and UDA1380
+ * @param	I2Sx			: Pointer to I2S interface to initialize
+ * @param	audio_in_sel	: audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+//FIXME Should we remove this function?
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_KEIL_MCB_18574357_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING'
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c

@@ -0,0 +1,433 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_KEIL_MCB_18574357_SYSINIT LPC1857 and LPC4357 Keil MCB board System Init code
+ * @ingroup BOARD_KEIL_MCB_18574357
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the Keil MCB boards includes clock setup, default pin muxing, and
+ * memory configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1857 and LPC4357 Keil MCB setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *   Sets up the external memory controller signals<BR>
+ *  Memory:<BR>
+ *   Sets up DRAM and NOR FLASH.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Setup FLASH acceleration to target clock rate prior to clock switch */
+	Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+	/* RMII pin group */
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+	/* External data lines D0 .. D15 */
+	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* Address lines A0 .. A23 */
+	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* EMC control signals */
+	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
+	{0x6, 6,  MD_PLN_FAST,                         FUNC1},
+	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 6,  MD_PLN_FAST,                         FUNC3},
+	/* Board LEDs */
+	{0xD, 10, (MD_PLN),                            FUNC4},
+	{0xD, 11, (MD_PLN),                            FUNC4},
+	{0xD, 12, (MD_PLN),                            FUNC4},
+	{0xD, 13, (MD_PLN),                            FUNC4},
+	{0xD, 14, (MD_PLN),                            FUNC4},
+	{0x9, 0,  (MD_PLN),                            FUNC0},
+	{0x9, 1,  (MD_PLN),                            FUNC0},
+	{0x9, 2,  (MD_PLN),                            FUNC0},
+	/* SSP0 */
+	{0xF, 0,  (MD_PLN_FAST),                       FUNC0},
+	{0xF, 1,  (MD_PLN_FAST),                       FUNC4},
+	{0xF, 2,  (MD_PLN_FAST),                       FUNC2},
+	{0xF, 3,  (MD_PLN_FAST),                       FUNC2},
+	/* LCD interface, 16bpp */
+	{0x4, 1,  MD_PUP,                              FUNC5},
+	{0x4, 2,  MD_PUP,                              FUNC2},
+	{0x4, 5,  MD_PUP,                              FUNC2},
+	{0x4, 6,  MD_PUP,                              FUNC2},
+	{0x4, 7,  MD_PUP,                              FUNC0},
+	{0x4, 9,  MD_PUP,                              FUNC2},
+	{0x4, 10, MD_PUP,                              FUNC2},
+	{0x7, 0,  MD_PUP,                              FUNC0},
+	{0x7, 6,  MD_PUP,                              FUNC3},
+	{0x8, 3,  MD_PUP,                              FUNC3},
+	{0x8, 4,  MD_PUP,                              FUNC3},
+	{0x8, 5,  MD_PUP,                              FUNC3},
+	{0x8, 6,  MD_PUP,                              FUNC3},
+	{0x8, 7,  MD_PUP,                              FUNC3},
+	{0xB, 0,  MD_PUP,                              FUNC2},
+	{0xB, 1,  MD_PUP,                              FUNC2},
+	{0xB, 2,  MD_PUP,                              FUNC2},
+	{0xB, 3,  MD_PUP,                              FUNC2},
+	{0xB, 4,  MD_PUP,                              FUNC2},
+	{0xB, 5,  MD_PUP,                              FUNC2},
+	{0xB, 6,  MD_PUP,                              FUNC2},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* EMC clock delay */
+#define CLK0_DELAY 7
+
+/* Keil SDRAM timing and chip Config */
+STATIC const IP_EMC_DYN_CONFIG_Type MT48LC4M32_config = {
+	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
+	0x01,	/* Command Delayed */
+	EMC_NANOSECOND(18),
+	EMC_NANOSECOND(42),
+	EMC_NANOSECOND(70),
+	EMC_CLOCK(0x01),
+	EMC_CLOCK(0x05),
+	EMC_NANOSECOND(12),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(12),
+	EMC_CLOCK(0x02),
+	{
+		{
+			EMC_ADDRESS_DYCS0,	/* Keil Board uses DYCS0 for SDRAM */
+			3,	/* RAS */
+
+			EMC_DYN_MODE_WBMODE_PROGRAMMED |
+			EMC_DYN_MODE_OPMODE_STANDARD |
+			EMC_DYN_MODE_CAS_3 |
+			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
+			EMC_DYN_MODE_BURST_LEN_4,
+
+			EMC_DYN_CONFIG_DATA_BUS_32 |
+			EMC_DYN_CONFIG_LPSDRAM |
+			EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
+			EMC_DYN_CONFIG_MD_SDRAM
+		},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0}
+	}
+};
+
+/* Keil NorFlash timing and chip Config */
+/* FIXME : Keil NOR FLASH not yet tested */
+STATIC const IP_EMC_STATIC_CONFIG_Type S29GL64N90_config = {
+	0,
+	EMC_STATIC_CONFIG_MEM_WIDTH_32 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(65),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(35),
+	EMC_CLOCK(4)
+};
+
+/* Setup external memories */
+STATIC void SystemSetupMemory(void)
+{
+	/* Setup EMC Delays */
+	/* Move all clock delays together */
+	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
+
+	/* Setup EMC Clock Divider for divide by 2 */
+	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
+	LPC_CREG->CREG6 |= (1 << 16);
+	Chip_Clock_Enable(CLK_MX_EMC);
+
+	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
+	Chip_EMC_Init(1, 0, 0);
+	/* Init EMC Dynamic Controller */
+	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config);
+	/* Init EMC Static Controller CS0 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config);
+
+	/* Enable Buffer for External Flash */
+	LPC_EMC->STATICCONFIG0 |= 1 << 19;
+}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ *			SystemInit() is called prior to the application and sets up system
+ *			clocking, memory, and any resources needed prior to the application
+ *			starting.
+ * @return	none
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief NGX Xplorer 1830/4330 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_ngx_xplorer_18304330.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c

@@ -0,0 +1,385 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+#include "string.h"
+
+#include "lpc_phy_smsc87x0.c"
+#include "retarget.c"
+
+/** @ingroup BOARD_NGX_XPLORER_18304330
+ * @{
+ */
+
+void Board_UART_Init(LPC_USART_Type *UARTx)
+{
+	if (UARTx == LPC_USART0) {
+		Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);					/* P6.5 : UART0_TXD */
+		Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P6.4 : UART0_RXD */
+	}
+	else if (UARTx == LPC_UART1) {
+		Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);				/* P1.13 : UART1_TXD */
+		Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P1.14 : UART1_RX */
+	}
+}
+
+/* Initialize debug output via UART for board */
+void Board_Debug_Init(void)
+{
+#if defined(DEBUG_UART)
+	Board_UART_Init(DEBUG_UART);
+
+	Chip_UART_Init(DEBUG_UART);
+	Chip_UART_SetBaud(DEBUG_UART, 115200);
+	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
+
+	/* Enable UART Transmit */
+	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
+#endif
+}
+
+/* Sends a character on the UART */
+void Board_UARTPutChar(char ch)
+{
+#if defined(DEBUG_UART)
+	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
+#endif
+}
+
+/* Gets a character from the UART, returns EOF if no character is ready */
+int Board_UARTGetChar(void)
+{
+#if defined(DEBUG_UART)
+	uint8_t data;
+
+	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
+		return (int) data;
+	}
+#endif
+	return EOF;
+}
+
+/* Outputs a string on the debug UART */
+void Board_UARTPutSTR(char *str)
+{
+#if defined(DEBUG_UART)
+	while (*str != '\0') {
+		Board_UARTPutChar(*str++);
+	}
+#endif
+}
+
+void Board_LED_Init()
+{
+	/* P2.12 : LED D2 as output */
+	Chip_GPIO_WriteDirBit(1, 12, true);
+
+	/* P2.11 : LED D3 as output */
+	Chip_GPIO_WriteDirBit(1, 11, true);
+
+	/* Set initial states to off (true to disable) */
+	Chip_GPIO_WritePortBit(1, 12, (bool) true);
+	Chip_GPIO_WritePortBit(1, 11, (bool) true);
+}
+
+void Board_LED_Set(uint8_t LEDNumber, bool On)
+{
+	if (LEDNumber == 0) {
+		Chip_GPIO_WritePortBit(1, 12, (bool) !On);
+	}
+	else if (LEDNumber == 1) {
+		Chip_GPIO_WritePortBit(1, 11, (bool) !On);
+	}
+}
+
+bool Board_LED_Test(uint8_t LEDNumber)
+{
+	if (LEDNumber == 0) {
+		return (bool) !Chip_GPIO_ReadPortBit(1, 12);
+	}
+	else if (LEDNumber == 1) {
+		return (bool) !Chip_GPIO_ReadPortBit(1, 11);
+	}
+
+	return false;
+}
+
+void Board_Buttons_Init(void)	// FIXME not functional ATM
+{
+	Chip_SCU_PinMux(0x2, 7, MD_PUP | MD_EZI | MD_ZI, FUNC0);		// P2_7 as GPIO0[7]
+	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false);	// input
+}
+
+uint32_t Buttons_GetStatus(void)
+{
+	uint8_t ret = NO_BUTTON_PRESSED;
+	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
+		ret |= BUTTONS_BUTTON1;
+	}
+	return ret;
+}
+
+void Board_Joystick_Init(void)
+{}
+
+uint8_t Joystick_GetStatus(void)
+{
+	return NO_BUTTON_PRESSED;
+}
+
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
+}
+
+/* Returns the MAC address assigned to this board */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr)
+{
+	uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
+
+	memcpy(mcaddr, boardmac, 6);
+}
+
+/* Set up and initialize all required blocks and functions related to the
+   board hardware */
+void Board_Init(void)
+{
+	/* Sets up DEBUG UART */
+	DEBUGINIT();
+
+	/* Updates SystemCoreClock global var with current clock speed */
+	SystemCoreClockUpdate();
+
+	/* Initializes GPIO */
+	Chip_GPIO_Init();
+
+	/* Setup GPIOs for USB demos */
+	Chip_SCU_PinMux(0x2, 6, (MD_PUP | MD_EZI), FUNC4);			/* P2_6 USB1_PWR_EN, USB1 VBus function */
+	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	/* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
+	Chip_SCU_PinMux(0x1, 7, (MD_PUP | MD_EZI), FUNC4);			/* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */
+	Chip_GPIO_WriteDirBit(5, 6, true);							/* GPIO5[6] = USB1_PWR_EN */
+	Chip_GPIO_WritePortBit(5, 6, true);							/* GPIO5[6] output high */
+}
+
+void Board_I2C_Init(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C1) {
+		/* Configure pin function for I2C1*/
+		Chip_SCU_PinMux(0x2, 3, MD_ZI | MD_EZI, FUNC1);		/* P2.3 : I2C1_SDA */
+		Chip_SCU_PinMux(0x2, 4, MD_ZI | MD_EZI, FUNC1);		/* P2.4 : I2C1_SCL */
+	}
+}
+
+void GPIO0_IRQHandler(void)
+{
+	static bool On;
+
+	if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
+		Chip_GPIO_IntClear(0, 0);
+		On = (bool) !On;
+		Board_LED_Set(1, On);
+	}
+}
+
+void Board_GPIO_Int_Init()
+{
+	Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0);	/* PF.9 : POTI button */
+	Chip_GPIO_WriteDirBit(7, 23, false);						/* PF.9 -> GPIO7[23] : input */
+	Chip_SCU_GPIOIntPinSel(0, 7, 23);
+	Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE);			/* Configure GPIO0[7] to interrupt pin (SW2 switch) */
+
+	NVIC_EnableIRQ(PIN_INT0_IRQn);	/* enable GPIO interrupt 0 */
+}
+
+void Board_SDMMC_Init(void)
+{
+	Chip_SCU_PinMux(0x1, 9, MD_PLN_FAST, FUNC7);	/* P1.9 connected to SDIO_D0 */
+	Chip_SCU_PinMux(0x1, 10, MD_PLN_FAST, FUNC7);	/* P1.10 connected to SDIO_D1 */
+	Chip_SCU_PinMux(0x1, 11, MD_PLN_FAST, FUNC7);	/* P1.11 connected to SDIO_D2 */
+	Chip_SCU_PinMux(0x1, 12, MD_PLN_FAST, FUNC7);	/* P1.12 connected to SDIO_D3 */
+
+	Chip_SCU_PinMux(PINMUX_CLK, 2, MD_PLN | MD_EZI, FUNC4);	/* CLK2 connected to SDIO_CLK */
+	Chip_SCU_PinMux(0x1, 6, MD_PLN_FAST, FUNC7);	/* P1.6 connected to SDIO_CMD */
+}
+
+void Board_SSP_Init(LPC_SSP_Type *SSPx)
+{
+	if (SSPx == LPC_SSP1) {
+		/* Set up clock and power for SSP1 module */
+		/* Configure SSP1 pins*/
+		/* SCLK comes out pin CLK0 */
+		Chip_SCU_PinMux(PINMUX_CLK, 0, MD_PLN_FAST, FUNC6);		/* CLK0 connected to CLK	func6=SSP1 CLK1  */
+		Chip_SCU_PinMux(0x1, 5, MD_PLN_FAST, FUNC5);			/* P1.5 connected to nCS	func5=SSP1 SSEL1 */
+		Chip_SCU_PinMux(0x1, 3, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.3 connected to SO		func5=SSP1 MISO1 */
+		Chip_SCU_PinMux(0x1, 4, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.4 connected to nSI	func5=SSP1 MOSI1 */
+		Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
+	}
+	else {
+		return;
+	}
+}
+
+/* System Register Data Set */
+uint16_t UDA_sys_regs_dat[] = {
+	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
+	UDA1380_REG_I2S_DEFAULT_VALUE,
+	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
+	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
+	UDA1380_REG_HEADAMP_DEFAULT_VALUE
+};
+
+/* System Register Data Set */
+uint16_t UDA_interfil_regs_dat[] = {
+	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
+	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
+	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
+	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
+	UDA1380_REG_MIXSDO_DEFAULT_VALUE
+};
+/* decimator Register Data Set */
+uint16_t UDA_decimator_regs_dat[] = {
+	UDA1380_REG_DECVOL_DEFAULT_VALUE,
+	UDA1380_REG_PGA_DEFAULT_VALUE,
+	UDA1380_REG_ADC_DEFAULT_VALUE,
+	UDA1380_REG_AGC_DEFAULT_VALUE
+};
+static void delay(uint32_t i) {
+	while (i--) {}
+}
+
+static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
+
+	I2C_Config->tx_data[0] = reg;
+	I2C_Config->tx_data[1] = value >> 8;
+	I2C_Config->tx_data[2] = value & 0xFF;
+	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
+	delay(10000);
+}
+
+static uint16_t UDA_Reg_read(UDA1380_REG reg) {
+	uint8_t rx_data[2];
+	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
+	return rx_data[0] << 8 | rx_data[1];
+}
+
+static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint16_t temp;
+	uint8_t  i;
+	/* Reset UDA1380 on board NGX Xplorer */
+	Chip_SCU_PinMux(0x2, 10, MD_PUP, FUNC0);
+	Chip_GPIO_WriteDirBit(0, 14, true);
+	Chip_GPIO_WritePortBit(0, 14, true);
+	// delay 1us
+	delay(100000);
+	Chip_GPIO_WritePortBit(0, 14, false);
+	delay(100000);
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
+		if (temp != UDA_sys_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	/* interfilter regs init */
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
+		if (temp != UDA_interfil_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+	/* decimator regs init */
+	for (i = 0; i < 4; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
+		if (temp != UDA_decimator_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
+		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
+		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
+					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
+					  I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+	}
+	return SUCCESS;
+
+}
+
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint8_t uda1380_tx_data_buf[3];
+	Chip_I2S_Audio_Format_Type I2S_Config;
+	I2C_M_SETUP_Type I2C_Config;
+	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
+	I2C_Config.retransmissions_max = 5;
+	I2C_Config.tx_length = 3;
+	I2C_Config.tx_data = uda1380_tx_data_buf;
+	I2C_Config.rx_length = 0;
+	I2C_Config.rx_data = NULL;
+
+	/* Initialize I2C peripheral ------------------------------------*/
+	/* Init I2C */
+	Chip_I2C_Init(LPC_I2C0);
+	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
+
+	I2S_Config.SampleRate = 48000;
+	I2S_Config.ChannelNumber = 2;		/* 1 is mono, 2 is stereo */
+	I2S_Config.WordWidth =  16;			/* 8, 16 or 32 bits */
+	Chip_I2S_Init(LPC_I2S0);
+	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
+	/* Enable Slave I2C operation */
+	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
+	/* Init UDA1380 CODEC */
+	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
+
+}
+
+/* FIXME Should we remove this function? */
+void Serial_CreateStream(void *Stream)
+{}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h

@@ -0,0 +1,232 @@
+/*
+ * @brief NGX Xplorer 1830/4330 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_NGX_XPLORER_18304330_H_
+#define __BOARD_NGX_XPLORER_18304330_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_NGX_XPLORER_18304330_OPTIONS BOARD: LPC1830 and LPC4330 NGX Xplorer board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for NGX boards, BOARD_NGX_XPLORER_18304330 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#define BOARD_NGX_XPLORER_18304330
+
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
+#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
+
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE   (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE   ( 1 << 9 | 2)
+
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE  (2 << 8 | 2)
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE      0x0000
+
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE     0xE4E4			/* Decrease Volume -28dB */
+#define UDA1380_REG_PGA_DEFAULT_VALUE         0x0000
+#define UDA1380_REG_ADC_DEFAULT_VALUE         0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
+#define UDA1380_REG_AGC_DEFAULT_VALUE         0x0000
+#define UDA1380_REG_L3_DEFAULT_VALUE          0x0000
+
+/* For USBLIB examples */
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+#define BUTTONS_BUTTON1     0x01
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM   0
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM    7
+#define LED1_GPIO_PORT_NUM              1
+#define LED1_GPIO_BIT_NUM               11
+#define LED2_GPIO_PORT_NUM              1
+#define LED2_GPIO_BIT_NUM               12
+
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/* UDA1380 Register Address */
+typedef enum {
+	UDA_EVALM_CLK = 0x00,
+	UDA_BUS_CTRL,
+	UDA_POWER_CTRL,
+	UDA_ANALOG_CTRL,
+	UDA_HPAMP_CTRL,
+	UDA_MASTER_VOL_CTRL = 0x10,
+	UDA_MIXER_VOL_CTRL,
+	UDA_MODE_CTRL,
+	UDA_MUTE_CTRL,
+	UDA_MIXER_FILTER_CTRL,
+	UDA_DEC_VOL_CTRL = 0x20,
+	UDA_PGA_CTRL,
+	UDA_ADC_CTRL,
+	UDA_AGC_CTRL,
+	UDA_TOTAL_REG
+} UDA1380_REG;
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initializes board specific GPIO Interrupt
+ * @return	Nothing
+ */
+void Board_GPIO_Int_Init(void);
+
+/**
+ * @brief	Initialize pin muxing for SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize pin muxing for SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Initialize button(s) interface on board
+ * @return	Nothing
+ */
+void Board_Buttons_Init(void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	Nothing
+ */
+void Board_Joystick_Init(void);
+
+/**
+ * @brief	Returns joystick states on board
+ * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
+ */
+uint8_t Joystick_GetStatus(void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus (void);
+
+/**
+ * @brief	Initialize I2S interface for the board and UDA1380
+ * @param	I2Sx			: Pointer to I2S register interface used on this board
+ * @param	audio_in_sel	: Audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+/**
+ * @brief	FIXME
+ * @param	Stream	: FIXME
+ * @return	Nothing
+ */
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_NGX_XPLORER_18304330_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c

@@ -0,0 +1,239 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code
+ * @ingroup BOARD_NGX_XPLORER_18304330
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the NGX Xplorer boards includes clock setup and default pin muxing
+ * configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1830 and LPC4330 NGX Xplorer setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *  Memory:<BR>
+ *   There is no memory setup for this board.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, false, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+	/* RMII pin group */
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x2, 0,  (MD_EHS | MD_PLN | MD_ZI),           FUNC7},
+	/* Board LEDs */
+	{0x2, 11, MD_PDN,                              FUNC0},
+	{0x2, 12, MD_PDN,                              FUNC0},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* Nothing to do for the Xplorer board */
+STATIC void SystemSetupMemory(void)
+{}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ * @return	none
+ * SystemInit() is called prior to the application and sets up system
+ * clocking, memory, and any resources needed prior to the application
+ * starting.
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	volatile unsigned int *pSCB_VTOR = (volatile unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_chip/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('chip_18xx_43xx/*.c')
+src += Glob('chip_common/*.c')
+
+path = [cwd + '/chip_18xx_43xx',
+        cwd + '/chip_common']
+
+group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c

@@ -0,0 +1,136 @@
+/*
+ * @brief LPC18xx/43xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "adc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*The channel to be operated on */
+static uint8_t active_channel;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns the clock for the selected ADC */
+static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC)
+{
+	CCU_CLK_T adcclk;
+
+	if (pADC == LPC_ADC0) {
+		adcclk = CLK_APB3_ADC0;
+	}
+	else {
+		adcclk = CLK_APB3_ADC1;
+	}
+
+	return adcclk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC peripheral and the ADC setup structure to default value */
+void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup)
+{
+	CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC);
+
+	/* Enable ADC clocking */
+	Chip_Clock_EnableOpts(adcclk, true, true, 1);
+	ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk);
+
+	ADCSetup->adcRate = 400000;
+	ADCSetup->bitsAccuracy = ADC_10BITS;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Select the mode starting the AD conversion */
+void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption)
+{
+	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
+		IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption);
+	}
+	IP_ADC_SetStartMode(pADC, (uint8_t) mode);
+}
+
+/* Set the ADC Sample rate */
+void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate)
+{
+	ADCSetup->adcRate = rate;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+
+}
+
+/* Set the ADC accuracy bits */
+void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution)
+{
+	ADCSetup->bitsAccuracy = resolution;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Enable or disable the ADC channel on ADC peripheral */
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState)
+{
+	IP_ADC_SetChannelNumber(pADC, channel, NewState);
+	active_channel = channel;
+}
+
+/* Enable burst mode */
+void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
+{
+	IP_ADC_SetStartMode(pADC, ADC_NO_START);
+	IP_ADC_SetBurstMode(pADC, NewState);
+}
+
+/* Read the ADC value and convert it to 8bits value */
+Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data)
+{
+	uint16_t temp;
+	Status rt;
+
+	rt = IP_ADC_Get_Val(pADC, active_channel, &temp);
+	*data = (uint8_t) temp;
+
+	return rt;
+}
+
+/* Set a channel to be read A/D data */
+void Chip_ADC_Active_Channel(uint8_t channel)
+{
+	active_channel = channel;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h

@@ -0,0 +1,240 @@
+/*
+ * @brief LPC18xx/43xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_18XX_43XX_H_
+#define __ADC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** The channels on one ADC peripheral*/
+typedef enum ADC_Channel {
+	ADC_CH0 = 0,	/**< ADC channel 0 */
+	ADC_CH1,		/**< ADC channel 1 */
+	ADC_CH2,		/**< ADC channel 2 */
+	ADC_CH3,		/**< ADC channel 3 */
+	ADC_CH4,		/**< ADC channel 4 */
+	ADC_CH5,		/**< ADC channel 5 */
+	ADC_CH6,		/**< ADC channel 6 */
+	ADC_CH7,		/**< ADC channel 7 */
+} ADC_Channel;
+
+/** The number of bits of accuracy of the result in the LS bits of ADDR*/
+typedef enum ADC_Resolution {
+	ADC_10BITS = 0,		/**< ADC 10 bits */
+	ADC_9BITS,			/**< ADC 9 bits  */
+	ADC_8BITS,			/**< ADC 8 bits  */
+	ADC_7BITS,			/**< ADC 7 bits  */
+	ADC_6BITS,			/**< ADC 6 bits  */
+	ADC_5BITS,			/**< ADC 5 bits  */
+	ADC_4BITS,			/**< ADC 4 bits  */
+	ADC_3BITS,			/**< ADC 3 bits  */
+} ADC_Resolution;
+
+/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
+typedef enum ADC_EdgeCfg {
+	ADC_TRIGGERMODE_RISING = 0,		/**< Trigger event: rising edge */
+	ADC_TRIGGERMODE_FALLING,		/**< Trigger event: falling edge */
+} ADC_EdgeCfg;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum ADC_StartMode {
+	ADC_NO_START = 0,
+	ADC_START_NOW,			/*!< Start conversion now */
+	ADC_START_ON_CTOUT15,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+	ADC_START_ON_CTOUT8,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+	ADC_START_ON_ADCTRIG0,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+	ADC_START_ON_ADCTRIG1,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+	ADC_START_ON_MCOA2		/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_StartMode;
+
+/** Clock setup structure for ADC controller passed to the initialize function */
+typedef struct {
+	uint32_t adcPerClock;	/*!< ADC peripheral Clock */
+	uint32_t adcRate;		/*!< ADC rate */
+	uint8_t  bitsAccuracy;	/*!< ADC bit accuracy */
+} ADC_Clock_Setup_Type;
+
+/**
+ * @brief	Read the ADC value from a channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	data		: Pointer to where to put data
+ * @return	SUCCESS or ERROR if no conversion is ready
+ */
+STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_Type *pADC, uint8_t channel, uint16_t *data)
+{
+	return IP_ADC_Get_Val(pADC, channel, data);
+}
+
+/**
+ * @brief	Read the ADC channel status
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	StatusType	: Status type of ADC_DR_*
+ * @return	SET or RESET
+ */
+STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_Type *pADC, uint8_t channel, uint32_t StatusType)
+{
+	return IP_ADC_GetStatus(pADC, channel, StatusType);
+}
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	SET or RESET
+ */
+STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	IP_ADC_Int_Enable(pADC, channel, NewState);
+}
+
+/**
+ * @brief	Enable/Disable global interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
+{
+	IP_ADC_Int_Enable(pADC, 8, NewState);
+}
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_DeInit(LPC_ADC_Type *pADC)
+{
+	IP_ADC_DeInit(pADC);
+}
+
+/**
+ * @brief	Initialize the ADC peripheral and the ADC setup structure to default value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be set
+ * @return	Nothing
+ * Default setting for ADC is 400kHz - 10bits
+ */
+void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup);
+
+/**
+ * @brief	Select the mode starting the AD conversion
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	mode		: Stating mode, should be :
+ *							- ADC_NO_START				: Must be set for Burst mode
+ *							- ADC_START_NOW				: Start conversion now
+ *							- ADC_START_ON_CTOUT15		: Start conversion when the edge selected by bit 27 occurs on CTOUT_15
+ *							- ADC_START_ON_CTOUT8		: Start conversion when the edge selected by bit 27 occurs on CTOUT_8
+ *							- ADC_START_ON_ADCTRIG0		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
+ *							- ADC_START_ON_ADCTRIG1		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
+ *							- ADC_START_ON_MCOA2		: Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
+ * @param	EdgeOption	: Stating Edge Condition, should be :
+ *							- ADC_TRIGGERMODE_RISING	: Trigger event on rising edge
+ *							- ADC_TRIGGERMODE_FALLING	: Trigger event on falling edge
+ * @return	Nothing
+ */
+void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption);
+
+/**
+ * @brief	Set the ADC Sample rate
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	rate		: Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
+ * @return	Nothing
+ */
+void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate);
+
+/**
+ * @brief	Set the ADC accuracy bits
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	resolution	: The resolution, should be ADC_10BITS -> ADC_3BITS
+ * @return	Nothing
+ */
+void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution);
+
+/**
+ * @brief	Enable or disable the ADC channel on ADC peripheral
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be enable or disable
+ * @param	NewState	: New state, should be:
+ *								- ENABLE
+ *								- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable burst mode
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, should be:
+ *							- ENABLE
+ *							- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState);
+
+/**
+ * @brief	Read the ADC value and convert it to 8bits value
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @param	data	: Storage for data
+ * @return	Status	: ERROR or SUCCESS
+ */
+Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data);
+
+/**
+ * @brief	Set a channel to be read A/D data
+ * @param	channel	: Channel to be active
+ * @return	Nothing
+ */
+void Chip_ADC_Active_Channel(uint8_t channel);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c

@@ -0,0 +1,55 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "atimer_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize Alarm Timer */
+void Chip_ATIMER_Init(uint32_t PresetValue)
+{
+	Chip_ATIMER_UpdatePresetValue(PresetValue);
+	Chip_ATIMER_ClearIntStatus();
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h

@@ -0,0 +1,117 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ATIMER_18XX_43XX_H_
+#define __ATIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize Alarm Timer
+ * @param PresetValue Count of 1 to 1024s for Alarm
+ * @return	None
+ */
+void Chip_ATIMER_Init(uint32_t PresetValue);
+
+/**
+ * @brief	Close ATIMER device
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_DeInit(void)
+{
+	IP_ATIMER_DeInit(LPC_ATIMER);
+}
+
+/**
+ * @brief	Enable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntEnable(void)
+{
+	IP_ATIMER_IntEnable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Disable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntDisable(void)
+{
+	IP_ATIMER_IntDisable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Clear ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_ClearIntStatus(void)
+{
+	IP_ATIMER_ClearIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Set ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_SetIntStatus(void)
+{
+	IP_ATIMER_SetIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Update Preset value
+ * @param	PresetValue	: updated preset value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue)
+{
+	IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue);
+}
+
+/**
+ * @brief	Read value of preset register
+ * @return	Value of capture register
+ */
+STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void)
+{
+	return IP_ATIMER_GetPresetValue(LPC_ATIMER);
+}
+
+/**
+ * @}
+ */
+
+ #endif /* __ATIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h

@@ -0,0 +1,104 @@
+/*
+ * @brief CGU/CCU registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CGUCCU_18XX_43XX_H_
+#define __CGUCCU_18XX_43XX_H_
+
+#include "cmsis.h"
+#include "chip_clocks.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CLOCK_18XX_43XX
+ * @{
+ */
+
+/**
+ * @brief LPC18XX/43XX CGU register block structure
+ */
+typedef struct {							/*!< (@ 0x40050000) CGU Structure          */
+	__I  uint32_t  RESERVED0[5];
+	__IO uint32_t  FREQ_MON;				/*!< (@ 0x40050014) Frequency monitor register */
+	__IO uint32_t  XTAL_OSC_CTRL;			/*!< (@ 0x40050018) Crystal oscillator control register */
+	__I  uint32_t  PLL0USB_STAT;			/*!< (@ 0x4005001C) PLL0 (USB) status register */
+	__IO uint32_t  PLL0USB_CTRL;			/*!< (@ 0x40050020) PLL0 (USB) control register */
+	__IO uint32_t  PLL0USB_MDIV;			/*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+	__IO uint32_t  PLL0USB_NP_DIV;			/*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+	__I  uint32_t  PLL0AUDIO_STAT;			/*!< (@ 0x4005002C) PLL0 (audio) status register */
+	__IO uint32_t  PLL0AUDIO_CTRL;			/*!< (@ 0x40050030) PLL0 (audio) control register */
+	__IO uint32_t  PLL0AUDIO_MDIV;			/*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+	__IO uint32_t  PLL0AUDIO_NP_DIV;		/*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+	__IO uint32_t  PLL0AUDIO_FRAC;			/*!< (@ 0x4005003C) PLL0 (audio)           */
+	__I  uint32_t  PLL1_STAT;				/*!< (@ 0x40050040) PLL1 status register   */
+	__IO uint32_t  PLL1_CTRL;				/*!< (@ 0x40050044) PLL1 control register  */
+	__IO uint32_t  IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
+	__IO uint32_t  BASE_CLK[CLK_BASE_LAST];	/*!< (@ 0x4005005C) Start of base clock registers */
+} LPC_CGU_T;
+
+/**
+ * @brief CCU clock config/status register pair
+ */
+typedef struct {
+	__IO uint32_t  CFG;						/*!< CCU clock configuration register */
+	__I  uint32_t  STAT;					/*!< CCU clock status register */
+} CCU_CFGSTAT_T;
+
+/**
+ * @brief CCU1 register block structure
+ */
+typedef struct {							/*!< (@ 0x40051000) CCU1 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40051000) CCU1 power mode register */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40051004) CCU1 base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU1_LAST];	/*!< (@ 0x40051100) Start of CCU1 clock registers */
+} LPC_CCU1_Type;
+
+/**
+ * @brief CCU2 register block structure
+ */
+typedef struct {							/*!< (@ 0x40052000) CCU2 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40052000) Power mode register    */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40052004) CCU base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST];	/*!< (@ 0x40052100) Start of CCU2 clock registers */
+} LPC_CCU2_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CGUCCU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h

@@ -0,0 +1,44 @@
+/*
+ * @brief Chip inclusion selector file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "sys_config.h"
+
+#if defined(CHIP_LPC18XX)
+#include "chip_lpc18xx.h"
+
+#elif defined(CHIP_LPC43XX)
+#include "chip_lpc43xx.h"
+
+#else
+#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
+#endif
+
+#endif /* __CHIP_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox

@@ -0,0 +1,51 @@
+/*
+ * @brief LPCOpen 18xx/43xx chip group page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers
+ * @ingroup Chip_Drivers
+ * @{
+ */
+
+/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options
+ * Some chip drivers require build-time configuration. Using a build-time
+ * configuration option allows the driver to be smaller and faster. A
+ * build-time option is configured by the use of a definition passed to
+ * the compiler during the build.
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h

@@ -0,0 +1,252 @@
+/*
+ * @brief	LPC18xx/43xx chip clock list used by CGU and CCU drivers
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_CLOCKS_H_
+#define __CHIP_CLOCKS_H_
+
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CLOCK_18XX_43XX
+ * @{
+ */
+
+/**
+ * @brief CGU clock input list
+ * These are possible input clocks for the CGU and can come
+ * from both external (crystal) and internal (PLL) sources. These
+ * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
+ */
+typedef enum {
+	CLKIN_32K,		/*!< External 32KHz input */
+	CLKIN_IRC,		/*!< Internal IRC (12MHz) input */
+	CLKIN_ENET_RX,	/*!< External ENET_RX pin input */
+	CLKIN_ENET_TX,	/*!< External ENET_TX pin input */
+	CLKIN_CLKIN,	/*!< External GPCLKIN pin input */
+	CLKIN_RESERVED1,
+	CLKIN_CRYSTAL,	/*!< External (main) crystal pin input */
+	CLKIN_USBPLL,	/*!< Internal USB PLL input */
+	CLKIN_AUDIOPLL,	/*!< Internal Audio PLL input */
+	CLKIN_MAINPLL,	/*!< Internal Main PLL input */
+	CLKIN_RESERVED2,
+	CLKIN_RESERVED3,
+	CLKIN_IDIVA,	/*!< Internal divider A input */
+	CLKIN_IDIVB,	/*!< Internal divider B input */
+	CLKIN_IDIVC,	/*!< Internal divider C input */
+	CLKIN_IDIVD,	/*!< Internal divider D input */
+	CLKIN_IDIVE,	/*!< Internal divider E input */
+	CLKINPUT_PD		/*!< External 32KHz input */
+} CGU_CLKIN_T;
+
+/**
+ * @brief CGU base clocks
+ * CGU base clocks are clocks that are associated with a single input clock
+ * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
+ * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
+ * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
+ * CLK_PERIPH_SGPIO periphral clocks.
+ */
+typedef enum {
+	CLK_BASE_SAFE,		/*!< Base clock for WDT oscillator, IRC input only */
+	CLK_BASE_USB0,		/*!< Base USB clock for USB0, USB PLL input only */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_PERIPH,	/*!< Base clock for SGPIO */
+#else
+	CLK_BASE_RESERVED1,
+#endif
+	CLK_BASE_USB1,		/*!< Base USB clock for USB1 */
+	CLK_BASE_MX,		/*!< Base clock for CPU core */
+	CLK_BASE_SPIFI,		/*!< Base clock for SPIFI */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_SPI,		/*!< Base clock for SPI */
+#else
+	CLK_BASE_RESERVED2,
+#endif
+	CLK_BASE_PHY_RX,	/*!< Base clock for PHY RX */
+	CLK_BASE_PHY_TX,	/*!< Base clock for PHY TX */
+	CLK_BASE_APB1,		/*!< Base clock for APB1 group */
+	CLK_BASE_APB3,		/*!< Base clock for APB3 group */
+	CLK_BASE_LCD,		/*!< Base clock for LCD pixel clock */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_VADC,		/*!< Base clock for VADC */
+#else
+	CLK_BASE_RESERVED3,
+#endif
+	CLK_BASE_SDIO,		/*!< Base clock for SDIO */
+	CLK_BASE_SSP0,		/*!< Base clock for SSP0 */
+	CLK_BASE_SSP1,		/*!< Base clock for SSP1 */
+	CLK_BASE_UART0,		/*!< Base clock for UART0 */
+	CLK_BASE_UART1,		/*!< Base clock for UART1 */
+	CLK_BASE_UART2,		/*!< Base clock for UART2 */
+	CLK_BASE_UART3,		/*!< Base clock for UART3 */
+	CLK_BASE_OUT,		/*!< Base clock for CLKOUT pin */
+	CLK_BASE_RESERVED4,
+	CLK_BASE_RESERVED5,
+	CLK_BASE_RESERVED6,
+	CLK_BASE_RESERVED7,
+	CLK_BASE_APLL,		/*!< Base clock for audio PLL */
+	CLK_BASE_CGU_OUT0,	/*!< Base clock for CGUOUT0 pin */
+	CLK_BASE_CGU_OUT1,	/*!< Base clock for CGUOUT1 pin */
+	CLK_BASE_LAST,
+	CLK_BASE_NONE = CLK_BASE_LAST
+} CGU_BASE_CLK_T;
+
+/**
+ * @brief CGU dividers
+ * CGU dividers provide an extra clock state where a specific clock can be
+ * divided before being routed to a peripheral group. A divider accepts an
+ * input clock and then divides it. To use the divided clock for a base clock
+ * group, use the divider as the input clock for the base clock (for example,
+ * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
+ */
+typedef enum {
+	CLK_IDIV_A,		/*!< CGU clock divider A */
+	CLK_IDIV_B,		/*!< CGU clock divider B */
+	CLK_IDIV_C,		/*!< CGU clock divider A */
+	CLK_IDIV_D,		/*!< CGU clock divider D */
+	CLK_IDIV_E,		/*!< CGU clock divider E */
+	CLK_IDIV_LAST
+} CGU_IDIV_T;
+
+/**
+ * @brief Peripheral clocks
+ * Peripheral clocks are individual clocks routed to peripherals. Although
+ * multiple peripherals may share a same base clock, each peripheral's clock
+ * can be enabled or disabled individually. Some peripheral clocks also have
+ * additional dividers associated with them.
+ */
+typedef enum {
+	/* CCU1 clocks */
+	CLK_APB3_BUS,		/*!< APB3 bus clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_I2C1,		/*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_DAC,		/*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_ADC0,		/*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_ADC1,		/*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_CAN0,		/*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB1_BUS = 32,	/*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_MOTOCON,	/*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_I2C0,		/*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_I2S,		/*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_CAN1,		/*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_SPIFI = 64,		/*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
+	CLK_MX_BUS = 96,	/*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
+	CLK_MX_SPIFI,		/*!< SPIFI register clock from base clock CLK_BASE_MX */
+	CLK_MX_GPIO,		/*!< GPIO register clock from base clock CLK_BASE_MX */
+	CLK_MX_LCD,			/*!< LCD register clock from base clock CLK_BASE_MX */
+	CLK_MX_ETHERNET,	/*!< ETHERNET register clock from base clock CLK_BASE_MX */
+	CLK_MX_USB0,		/*!< USB0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_EMC,			/*!< EMC clock from base clock CLK_BASE_MX */
+	CLK_MX_SDIO,		/*!< SDIO register clock from base clock CLK_BASE_MX */
+	CLK_MX_DMA,			/*!< DMA register clock from base clock CLK_BASE_MX */
+	CLK_MX_MXCORE,		/*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
+	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
+	CLK_MX_SCT,			/*!< SCT register clock from base clock CLK_BASE_MX */
+	CLK_MX_USB1,		/*!< USB1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_EMC_DIV,		/*!< ENC divider clock from base clock CLK_BASE_MX */
+	CLK_MX_FLASHA,		/*!< FLASHA bank clock from base clock CLK_BASE_MX */
+	CLK_MX_FLASHB,		/*!< FLASHB bank clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+	CLK_M4_M0APP,		/*!< M0 app CPU core clock from base clock CLK_BASE_MX */
+	CLK_MX_VADC,		/*!< VADC clock from base clock CLK_BASE_MX */
+#else
+	CLK_RESERVED1,
+	CLK_RESERVED2,
+#endif
+	CLK_MX_EEPROM,		/*!< EEPROM clock from base clock CLK_BASE_MX */
+	CLK_MX_WWDT = 128,	/*!< WWDT register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART0,		/*!< UART0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART1,		/*!< UART1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_SSP0,		/*!< SSP0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER0,		/*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER1,		/*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_SCU,			/*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_CREG,		/*!< CREG clock from base clock CLK_BASE_MX */
+	CLK_MX_RITIMER = 160,	/*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_UART2,		/*!< UART3 register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART3,		/*!< UART4 register clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER2,		/*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER3,		/*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_SSP1,		/*!< SSP1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_QEI,			/*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+	CLK_PERIPH_BUS = 192,	/*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
+	CLK_RESERVED3,
+	CLK_PERIPH_CORE,	/*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
+	CLK_PERIPH_SGPIO,	/*!< SGPIO clock from base clock CLK_BASE_PERIPH */
+#else
+	CLK_RESERVED3 = 192,
+	CLK_RESERVED3A,
+	CLK_RESERVED4,
+	CLK_RESERVED5,
+#endif
+	CLK_USB0 = 224,			/*!< USB0 clock from base clock CLK_BASE_USB0 */
+	CLK_USB1 = 256,			/*!< USB1 clock from base clock CLK_BASE_USB1 */
+#if defined(CHIP_LPC43XX)
+	CLK_SPI = 288,			/*!< SPI clock from base clock CLK_BASE_SPI */
+	CLK_VADC,				/*!< VADC clock from base clock CLK_BASE_VADC */
+#else
+	CLK_RESERVED7 = 320,
+	CLK_RESERVED8,
+#endif
+	CLK_CCU1_LAST,
+
+	/* CCU2 clocks */
+	CLK_CCU2_START,
+	CLK_APLL = CLK_CCU2_START,	/*!< Audio PLL clock from base clock CLK_BASE_APLL */
+	RESERVED_ALIGNB = CLK_CCU2_START + 31,
+	CLK_APB2_UART3,			/*!< UART3 clock from base clock CLK_BASE_UART3 */
+	RESERVED_ALIGNC = CLK_CCU2_START + 63,
+	CLK_APB2_UART2,			/*!< UART2 clock from base clock CLK_BASE_UART2 */
+	RESERVED_ALIGND = CLK_CCU2_START + 95,
+	CLK_APB0_UART1,			/*!< UART1 clock from base clock CLK_BASE_UART1 */
+	RESERVED_ALIGNE = CLK_CCU2_START + 127,
+	CLK_APB0_UART0,			/*!< UART0 clock from base clock CLK_BASE_UART0 */
+	RESERVED_ALIGNF = CLK_CCU2_START + 159,
+	CLK_APB2_SSP1,			/*!< SSP1 clock from base clock CLK_BASE_SSP1 */
+	RESERVED_ALIGNG = CLK_CCU2_START + 191,
+	CLK_APB0_SSP0,			/*!< SSP0 clock from base clock CLK_BASE_SSP0 */
+	RESERVED_ALIGNH = CLK_CCU2_START + 223,
+	CLK_APB2_SDIO,			/*!< SDIO clock from base clock CLK_BASE_SDIO */
+	CLK_CCU2_LAST
+} CCU_CLK_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_CLOCKS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h

@@ -0,0 +1,240 @@
+/*
+ * @brief LPC18xx basic chip inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC18XX_H_
+#define __CHIP_LPC18XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifndef CORE_M3
+#error CORE_M3 is not defined for the LPC18xx architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC18XX
+#error The LPC18XX Chip include path is used for this build, but
+#error CHIP_LPC18XX is not defined!
+#endif
+
+#include "adc_001.h"
+#include "atimer_001.h"
+#include "ccan_001.h"
+#include "dac_001.h"
+#include "emc_001.h"
+#include "enet_001.h"
+#include "gima_001.h"
+#include "gpdma_001.h"
+#include "gpiogrpint_001.h"
+#include "gpiopinint_001.h"
+#include "gpio_001.h"
+#include "i2c_001.h"
+#include "i2s_001.h"
+#include "lcd_001.h"
+#include "mcpwm_001.h"
+#include "pmc_001.h"
+#include "qei_001.h"
+#include "regfile_001.h"
+#include "ritimer_001.h"
+#include "rtc_001.h"
+#include "sct_001.h"
+#include "sdmmc_001.h"
+#include "ssp_001.h"
+#include "timer_001.h"
+#include "usart_001.h"
+#include "usbhs_001.h"
+#include "wwdt_001.h"
+#include "spifi_001.h"
+#include "rgu_18xx_43xx.h"
+#include "cguccu_18xx_43xx.h"
+
+/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVRT_BASE             0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+/* Normalize types */
+typedef IP_SCT_001_Type LPC_SCT_Type;
+typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
+typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
+typedef IP_EMC_001_Type LPC_EMC_Type;
+typedef IP_USBHS_001_Type LPC_USBHS_Type;
+typedef IP_ENET_001_Type LPC_ENET_Type;
+typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
+typedef IP_REGFILE_001_T LPC_REGFILE_T;
+typedef IP_PMC_001_Type LPC_PMC_Type;
+typedef IP_RTC_001_T LPC_RTC_Type;
+typedef IP_WWDT_001_Type LPC_WWDT_Type;
+typedef IP_USART_001_Type LPC_USART_Type;
+typedef IP_SSP_001_Type LPC_SSP_Type;
+typedef IP_TIMER_001_Type LPC_TIMER_Type;
+typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
+typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
+typedef IP_I2C_001_Type LPC_I2C_Type;
+typedef IP_I2S_001_Type LPC_I2S_Type;
+typedef IP_CCAN_001_Type LPC_CCAN_Type;
+typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
+typedef IP_QEI_001_Type LPC_QEI_Type;
+typedef IP_GIMA_001_Type LPC_GIMA_Type;
+typedef IP_DAC_001_Type LPC_DAC_Type;
+typedef IP_ADC_001_Type LPC_ADC_Type;
+typedef IP_GPIO_001_Type LPC_GPIO_Type;
+typedef IP_LCD_001_Type LPC_LCD_Type;
+
+#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
+#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
+#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
+#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
+#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
+#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
+#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
+#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
+#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
+#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
+#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
+#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
+
+/**
+ * @}
+ */
+
+#include "clock_18xx_43xx.h"
+#include "gpio_18xx_43xx.h"
+#include "uart_18xx_43xx.h"
+#include "gpdma_18xx_43xx.h"
+#include "enet_18xx_43xx.h"
+#include "i2c_18xx_43xx.h"
+#include "i2s_18xx_43xx.h"
+#include "ssp_18xx_43xx.h"
+#include "rtc_18xx_43xx.h"
+#include "evrt_18xx_43xx.h"
+#include "atimer_18xx_43xx.h"
+#include "wwdt_18xx_43xx.h"
+#include "ritimer_18xx_43xx.h"
+#include "emc_18xx_43xx.h"
+#include "lcd_18xx_43xx.h"
+#include "adc_18xx_43xx.h"
+#include "sdmmc_18xx_43xx.h"
+#include "timer_18xx_43xx.h"
+#include "creg_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC18XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h

@@ -0,0 +1,248 @@
+/*
+ * @brief LPC43xx basic chip inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC43XX_H_
+#define __CHIP_LPC43XX_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CORE_M4) && !defined(CORE_M0)
+#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
+#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC43XX
+#error The LPC43XX Chip include path is used for this build, but
+#error CHIP_LPC43XX is not defined!
+#endif
+
+#include "adc_001.h"
+#include "atimer_001.h"
+#include "ccan_001.h"
+#include "dac_001.h"
+#include "emc_001.h"
+#include "enet_001.h"
+#include "gima_001.h"
+#include "gpdma_001.h"
+#include "gpiogrpint_001.h"
+#include "gpiopinint_001.h"
+#include "gpio_001.h"
+#include "i2c_001.h"
+#include "i2s_001.h"
+#include "lcd_001.h"
+#include "mcpwm_001.h"
+#include "pmc_001.h"
+#include "qei_001.h"
+#include "regfile_001.h"
+#include "ritimer_001.h"
+#include "rtc_001.h"
+#include "sct_001.h"
+#include "sdmmc_001.h"
+#include "sgpio_001.h"
+#include "spi_001.h"
+#include "ssp_001.h"
+#include "timer_001.h"
+#include "usart_001.h"
+#include "usbhs_001.h"
+#include "wwdt_001.h"
+#include "spifi_001.h"
+#include "rgu_18xx_43xx.h"
+#include "cguccu_18xx_43xx.h"
+
+/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVRT_BASE             0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+/* Normalize types */
+typedef IP_SCT_001_Type LPC_SCT_Type;
+typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
+typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
+typedef IP_EMC_001_Type LPC_EMC_Type;
+typedef IP_USBHS_001_Type LPC_USBHS_Type;
+typedef IP_ENET_001_Type LPC_ENET_Type;
+typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
+typedef IP_REGFILE_001_T LPC_REGFILE_Type;
+typedef IP_PMC_001_Type LPC_PMC_Type;
+typedef IP_RTC_001_T LPC_RTC_Type;
+typedef IP_WWDT_001_Type LPC_WWDT_Type;
+typedef IP_USART_001_Type LPC_USART_Type;
+typedef IP_SSP_001_Type LPC_SSP_Type;
+typedef IP_TIMER_001_Type LPC_TIMER_Type;
+typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
+typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
+typedef IP_I2C_001_Type LPC_I2C_Type;
+typedef IP_I2S_001_Type LPC_I2S_Type;
+typedef IP_CCAN_001_Type LPC_CCAN_Type;
+typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
+typedef IP_QEI_001_Type LPC_QEI_Type;
+typedef IP_GIMA_001_Type LPC_GIMA_Type;
+typedef IP_DAC_001_Type LPC_DAC_Type;
+typedef IP_ADC_001_Type LPC_ADC_Type;
+typedef IP_GPIO_001_Type LPC_GPIO_Type;
+typedef IP_SPI_001_Type LPC_SPI_Type;
+typedef IP_SGPIO_001_Type LPC_SGPIO_Type;
+typedef IP_LCD_001_Type LPC_LCD_Type;
+
+#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
+#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
+#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
+#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
+#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
+#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
+#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
+#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
+#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
+#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
+#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
+#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
+#define LPC_SPI                   ((IP_SPI_001_Type              *) LPC_SPI_BASE)
+#define LPC_SGPIO                 ((IP_SGPIO_001_Type            *) LPC_SGPIO_BASE)
+
+/**
+ * @}
+ */
+
+#include "clock_18xx_43xx.h"
+#include "gpio_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+#include "uart_18xx_43xx.h"
+#include "gpdma_18xx_43xx.h"
+#include "enet_18xx_43xx.h"
+#include "rgu_18xx_43xx.h"
+#include "i2c_18xx_43xx.h"
+#include "i2s_18xx_43xx.h"
+#include "ssp_18xx_43xx.h"
+#include "rtc_18xx_43xx.h"
+#include "evrt_18xx_43xx.h"
+#include "atimer_18xx_43xx.h"
+#include "wwdt_18xx_43xx.h"
+#include "ritimer_18xx_43xx.h"
+#include "emc_18xx_43xx.h"
+#include "lcd_18xx_43xx.h"
+#include "adc_18xx_43xx.h"
+#include "timer_18xx_43xx.h"
+#include "sdmmc_18xx_43xx.h"
+#include "fpu_init.h"
+#include "creg_18xx_43xx.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c

@@ -0,0 +1,576 @@
+/*
+ * @brief LPC18xx/43xx clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "clock_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Maps a peripheral clock to it's base clock */
+typedef struct {
+	CCU_CLK_T clkstart;
+	CCU_CLK_T clkend;
+	CGU_BASE_CLK_T clkbase;
+} CLK_PERIPH_TO_BASE_T;
+static const CLK_PERIPH_TO_BASE_T periph_to_base[] = {
+	{CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},
+	{CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},
+	{CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},
+	{CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},
+#if 0
+#if defined(CHIP_LPC43XX)
+	{CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
+#endif
+	{CLK_USB0, CLK_USB0, CLK_BASE_USB0},
+	{CLK_USB1, CLK_USB1, CLK_BASE_USB1},
+#if defined(CHIP_LPC43XX)
+	{CLK_SPI, CLK_SPI, CLK_BASE_SPI},
+	{CLK_VADC, CLK_VADC, CLK_BASE_VADC},
+#endif
+	{CLK_APLL, CLK_APLL, CLK_BASE_APLL},
+	{CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},
+	{CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},
+	{CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1},
+	{CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0},
+	{CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},
+	{CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0},
+	{CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},
+	{CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}
+#endif
+};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Test PLL input values for a specific frequency range */
+static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)
+{
+	uint32_t TestHz = TestMult * InputHz;
+
+	if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
+		TestHz = 0;
+	}
+
+	return TestHz;
+}
+
+/* Returns clock rate out of a divider */
+static uint32_t Chip_Clock_GetDivRate(CGU_CLKIN_T clock, CGU_IDIV_T divider)
+{
+	CGU_CLKIN_T input;
+	uint32_t div;
+
+	input = Chip_Clock_GetDividerSource(divider);
+	div = Chip_Clock_GetDividerDivisor(divider);
+	return Chip_Clock_GetClockInputHz(input) / (div + 1);
+}
+
+/* Finds the base clock for the peripheral clock */
+static CGU_BASE_CLK_T Chip_Clock_FindBseClock(CCU_CLK_T clk)
+{
+	CGU_BASE_CLK_T baseclk = CLK_BASE_NONE;
+	int i = 0;
+
+	while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
+		if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
+			baseclk = periph_to_base[i].clkbase;
+		}
+		else {
+			i++;
+		}
+	}
+
+	return baseclk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Enables the crystal oscillator */
+void Chip_Clock_EnableCrystal(void)
+{
+	uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL;
+
+	/* Clear bypass mode */
+	OldCrystalConfig &= (~2);
+	if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) {
+		LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
+	}
+
+	/* Enable crystal oscillator */
+	OldCrystalConfig &= (~1);
+	if (CRYSTAL_MAIN_FREQ_IN >= 20000000) {
+		OldCrystalConfig |= 4;	/* Set high frequency mode */
+
+	}
+	LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
+}
+
+/* Disables the crystal oscillator */
+void IP_Clock_DisableCrystal(void)
+{
+	/* Disable crystal oscillator */
+	LPC_CGU->XTAL_OSC_CTRL &= (~1);
+}
+
+/* Configures the main PLL */
+uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
+{
+	uint32_t freqin = Chip_Clock_GetClockInputHz(Input);
+	uint32_t Mult, LastMult, MultEnd;
+	uint32_t freqout, freqout2;
+
+	if (DesiredHz != 0xFFFFFFFF) {
+		/* Test DesiredHz rounded down */
+		Mult = DesiredHz / freqin;
+		freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
+
+		/* Test DesiredHz rounded up */
+		Mult++;
+		freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
+
+		if (freqout && !freqout2) {	/* rounding up is no good? set first multiplier */
+			Mult--;
+			return Chip_Clock_SetupMainPLLMult(Input, Mult);
+		}
+		if (!freqout && freqout2) {	/* didn't work until rounded up? set 2nd multiplier */
+			return Chip_Clock_SetupMainPLLMult(Input, Mult);
+		}
+
+		if (freqout && freqout2) {	/* either multiplier okay? choose closer one */
+			if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
+				Mult--;
+				return Chip_Clock_SetupMainPLLMult(Input, Mult);
+			}
+			else {
+				return Chip_Clock_SetupMainPLLMult(Input, Mult);
+			}
+		}
+	}
+
+	/* Neither multiplier okay? Try to start at MinHz and increment.
+	   This should find the highest multiplier that is still good */
+	Mult = MinHz / freqin;
+	MultEnd = MaxHz / freqin;
+	LastMult = 0;
+	while (1) {
+		freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
+
+		if (freqout) {
+			LastMult = Mult;
+		}
+
+		if (Mult >= MultEnd) {
+			break;
+		}
+		Mult++;
+	}
+
+	if (LastMult) {
+		return Chip_Clock_SetupMainPLLMult(Input, LastMult);
+	}
+
+	return 0;
+}
+
+/* Directly set the PLL multipler */
+uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult)
+{
+	uint32_t freq = Chip_Clock_GetClockInputHz(Input);
+	uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
+	uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
+
+	freq *= mult;
+	msel = mult - 1;
+
+	PLLReg &= ~(0x1F << 24);/* clear input source bits */
+	PLLReg |= Input << 24;	/* set input source bits to parameter */
+
+	/* Clear other PLL input bits */
+	PLLReg &= ~((1 << 6) |	/* FBSEL */
+				(1 << 1) |	/* BYPASS */
+				(1 << 7) |	/* DIRECT */
+				(0x03 << 8) | (0xFF << 16) | (0x03 << 12));	/* PSEL, MSEL, NSEL- divider ratios */
+
+	if (freq < 156000000) {
+		/* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */
+		while ((2 * (pval) * freq) < 156000000) {
+			psel++;
+			pval *= 2;
+		}
+
+		PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6);	/* dividers + FBSEL */
+	}
+	else if (freq < 320000000) {
+		PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6);	/* dividers + DIRECT + FBSEL */
+	}
+	else {
+		Chip_Clock_DisableMainPLL();
+		return 0;
+	}
+	LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
+
+	return freq;
+}
+
+/* Returns the frequency of the main PLL */
+uint32_t Chip_Clock_GetMainPLLHz(void)
+{
+	uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
+	uint32_t freq = Chip_Clock_GetClockInputHz((CGU_CLKIN_T) ((PLLReg >> 24) & 0xF));
+	uint32_t msel, nsel, psel, direct, fbsel;
+	uint32_t m, n, p;
+	const uint8_t ptab[] = {1, 2, 4, 8};
+
+	/* No lock? */
+	if (!(LPC_CGU->PLL1_STAT & 1)) {
+		return 0;
+	}
+
+	msel = (PLLReg >> 16) & 0xFF;
+	nsel = (PLLReg >> 12) & 0x3;
+	psel = (PLLReg >> 8) & 0x3;
+	direct = (PLLReg >> 7) & 0x1;
+	fbsel = (PLLReg >> 6) & 0x1;
+
+	m = msel + 1;
+	n = nsel + 1;
+	p = ptab[psel];
+
+	if (direct || fbsel) {
+		return m * (freq / n);
+	}
+
+	return (m / (2 * p)) * (freq / n);
+}
+
+/* Disables the main PLL */
+void Chip_Clock_DisableMainPLL(void)
+{
+	/* power down main PLL */
+	LPC_CGU->PLL1_CTRL |= 1;
+}
+
+/* Returns the lock status of the main PLL */
+bool Chip_Clock_MainPLLLocked(void)
+{
+	/* Return true if locked */
+	return (bool) (LPC_CGU->PLL1_STAT & 1);
+}
+
+/* Sets up a CGU clock divider and it's input clock */
+void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor)
+{
+	uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
+
+	Divisor--;
+
+	if (Input != CLKINPUT_PD) {
+		/* Mask off bits that need to changes */
+		reg &= ~((0x1F << 24) | 1 | (0xF << 2));
+
+		/* Enable autoblocking, clear PD, and set clock source & divisor */
+		LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
+	}
+	else {
+		LPC_CGU->IDIV_CTRL[Divider] = reg | 1;	/* Power down this divider */
+	}
+}
+
+/* Gets a CGU clock divider source */
+CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider)
+{
+	uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
+
+	if (reg & 1) {	/* divider is powered down */
+		return CLKINPUT_PD;
+	}
+
+	return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
+}
+
+/* Gets a CGU clock divider divisor */
+uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider)
+{
+	return (CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF);
+}
+
+/* Returns the frequency of the specified input clock source */
+uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input)
+{
+	uint32_t rate = 0;
+
+	switch (input) {
+	case CLKIN_32K:
+		rate = CRYSTAL_32K_FREQ_IN;
+		break;
+
+	case CLKIN_IRC:
+		rate = CGU_IRC_FREQ;
+		break;
+
+	case CLKIN_ENET_RX:
+#if defined(USE_RMII)
+		/* In RMII mode, this clock is not attached */
+#else
+		/* MII mode requires 25MHz clock */
+		rate = 25000000;
+#endif
+		break;
+
+	case CLKIN_ENET_TX:
+#if defined(USE_RMII)
+		/* MII mode requires 50MHz clock */
+		rate = 50000000;
+#else
+		/* MII mode requires 25MHz clock */
+		rate = 25000000;
+#endif
+		break;
+
+	case CLKIN_CLKIN:
+#if defined(EXTERNAL_CLKIN_FREQ_IN)
+		rate = EXTERNAL_CLKIN_FREQ_IN;
+#else
+		/* Assume no clock in if a rate wasn't defined */
+#endif
+		break;
+
+	case CLKIN_CRYSTAL:
+		rate = CRYSTAL_MAIN_FREQ_IN;
+		break;
+
+	case CLKIN_USBPLL:
+		rate = 0; // FIXME
+		break;
+
+	case CLKIN_AUDIOPLL:
+		rate = 0; // FIXME
+		break;
+
+	case CLKIN_MAINPLL:
+		rate = Chip_Clock_GetMainPLLHz();
+		break;
+
+	case CLKIN_IDIVA:
+		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A);
+		break;
+
+	case CLKIN_IDIVB:
+		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B);
+		break;
+
+	case CLKIN_IDIVC:
+		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C);
+		break;
+
+	case CLKIN_IDIVD:
+		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D);
+		break;
+
+	case CLKIN_IDIVE:
+		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E);
+		break;
+
+	case CLKINPUT_PD:
+		rate = 0;
+		break;
+
+	default:
+		break;
+	}
+
+	return rate;
+}
+
+/* Returns the frequency of the specified base clock source */
+uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock)
+{
+	return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock));
+}
+
+/* Sets a CGU Base Clock clock source */
+void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
+{
+	uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
+
+	if (BaseClock < CLK_BASE_NONE) {
+		if (Input != CLKINPUT_PD) {
+			/* Mask off fields we plan to update */
+			reg &= ~((0x1F << 24) | 1 | (1 << 11));
+
+			if (autoblocken) {
+				reg |= (1 << 11);
+			}
+			if (powerdn) {
+				reg |= (1 << 0);
+			}
+
+			/* Set clock source */
+			reg |= (Input << 24);
+
+			LPC_CGU->BASE_CLK[BaseClock] = reg;
+		}
+	}
+	else {
+		LPC_CGU->BASE_CLK[BaseClock] = reg | 1;	/* Power down this base clock */
+	}
+}
+
+/*Enables a base clock source */
+void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock)
+{
+	if (BaseClock < CLK_BASE_NONE) {
+		LPC_CGU->BASE_CLK[BaseClock] &= ~1;
+	}
+}
+
+/* Disables a base clock source */
+void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock)
+{
+	if (BaseClock < CLK_BASE_NONE) {
+		LPC_CGU->BASE_CLK[BaseClock] |= 1;
+	}
+}
+
+/* Gets a CGU Base Clock clock source */
+CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock)
+{
+	uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
+
+	if (BaseClock >= CLK_BASE_NONE) {
+		return CLKINPUT_PD;
+	}
+
+	/* base clock is powered down? */
+	if (reg & 1) {
+		return CLKINPUT_PD;
+	}
+
+	return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
+}
+
+/* Enables a peripheral clock and sets clock states */
+void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
+{
+	uint32_t reg = 1;
+
+	if (autoen) {
+		reg |= (1 << 1);
+	}
+	if (wakeupen) {
+		reg |= (1 << 2);
+	}
+
+	/* Not all clocks support a divider, but we won't check that here. Only
+	   dividers of 1 and 2 are allowed. Assume 1 if not 2 */
+	if (div == 2) {
+		reg |= (1 << 5);
+	}
+
+	/* Setup peripheral clock and start running */
+	if (clk >= CLK_CCU2_START) {
+		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg;
+	}
+	else {
+		LPC_CCU1->CLKCCU[clk].CFG = reg;
+	}
+}
+
+/* Enables a peripheral clock */
+void Chip_Clock_Enable(CCU_CLK_T clk)
+{
+	/* Start peripheral clock running */
+	if (clk >= CLK_CCU2_START) {
+		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1;
+	}
+	else {
+		LPC_CCU1->CLKCCU[clk].CFG |= 1;
+	}
+}
+
+/* Disables a peripheral clock */
+void Chip_Clock_Disable(CCU_CLK_T clk)
+{
+	/* Stop peripheral clock */
+	if (clk >= CLK_CCU2_START) {
+		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1;
+	}
+	else {
+		LPC_CCU1->CLKCCU[clk].CFG &= ~1;
+	}
+}
+
+/* Returns a peripheral clock rate */
+uint32_t Chip_Clock_GetRate(CCU_CLK_T clk)
+{
+	CGU_BASE_CLK_T baseclk;
+	uint32_t reg, div, rate;
+
+	/* Get CCU config register for clock */
+	if (clk >= CLK_CCU2_START) {
+		reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;
+	}
+	else {
+		reg = LPC_CCU1->CLKCCU[clk].CFG;
+	}
+
+	/* Is the clock enabled? */
+	if (reg & 1) {
+		/* Get base clock for this peripheral clock */
+		baseclk = Chip_Clock_FindBseClock(clk);
+
+		/* Get base clock rate */
+		rate = Chip_Clock_GetBaseClocktHz(baseclk);
+
+		/* Get divider for this clock */
+		if (((reg >> 5) & 0x7) == 0) {
+			div = 1;
+		}
+		else {
+			div = 2;/* No other dividers supported */
+
+		}
+		rate = rate / div;
+	}
+	else {
+		rate = 0;
+	}
+
+	return rate;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h

@@ -0,0 +1,238 @@
+/*
+ * @brief LPC18xx/43xx clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CLOCK_18XX_43XX_H_
+#define __CLOCK_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options
+ * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS 
+ * The clock driver has options that configure it's operation at build-time.<br/>
+ * MAX_CLOCK_FREQ:
+ * - This define, when set, identifies the maximumCPU clock rate of the system (change this to alter running CPU speed)
+ * - When this is not defined, The maximum clock rate for the CPU is used
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Internal oscillator frequency */
+#define CGU_IRC_FREQ (12000000)
+
+#ifndef MAX_CLOCK_FREQ
+#if defined(CHIP_LPC43XX)
+#define MAX_CLOCK_FREQ (204000000)
+#else
+#define MAX_CLOCK_FREQ (180000000)
+#endif
+#endif /* MAX_CLOCK_FREQ */
+
+/**
+ * @brief	Enables the crystal oscillator
+ * @return	Nothing
+ */
+void Chip_Clock_EnableCrystal(void);
+
+/**
+ * @brief	Disables the crystal oscillator
+ * @return	Nothing
+ */
+void Chip_Clock_DisableCrystal(void);
+
+/**
+ * @brief   Configures the main PLL
+ * @param   Input		: Which clock input to use as the PLL input
+ * @param   MinHz		: Minimum allowable PLL output frequency
+ * @param   DesiredHz	: Desired PLL output frequency
+ * @param   MaxHz		: Maximum allowable PLL output frequency
+ * @return	Frequency of the PLL in Hz
+ * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz
+ * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if
+ * the PLL is locked.
+ */
+uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
+
+/**
+ * @brief	Directly set the PLL multipler
+ * @param   Input	: Which clock input to use as the PLL input
+ * @param	mult	: How many times to multiply the input clock
+ * @return	Frequency of the PLL in Hz
+ */
+uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult);
+
+/**
+ * @brief   Returns the frequency of the main PLL
+ * @return	Frequency of the PLL in Hz
+ * Returns zero if the main PLL is not running.
+ */
+uint32_t Chip_Clock_GetMainPLLHz(void);
+
+/**
+ * @brief	Disables the main PLL
+ * @return	none
+ * Make sure the main PLL is not needed to clock the part before disabling it.
+ * Saves power if the main PLL is not needed.
+ */
+void Chip_Clock_DisableMainPLL(void);
+
+/**
+ * @brief   Returns the lock status of the main PLL
+ * @return	true if the PLL is locked, otherwise false
+ * The main PLL should be locked prior to using it as a clock input for a base clock.
+ */
+bool Chip_Clock_MainPLLLocked(void);
+
+/**
+ * @brief	Sets up a CGU clock divider and it's input clock
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to configure
+ * @param	Input	: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
+ * @param	Divisor	: value to divide Input clock by
+ * @return	Nothing
+ */
+void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor);
+
+/**
+ * @brief	Gets a CGU clock divider source
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
+ * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
+ */
+CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider);
+
+/**
+ * @brief	Gets a CGU clock divider divisor
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
+ * @return	the divider value for the divider
+ */
+uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider);
+
+/**
+ * @brief	Returns the frequency of the specified input clock source
+ * @param	input	: Which clock input to return the frequency of
+ * @return	Frequency of input source in Hz
+ * This function returns an ideal frequency and not the actual frequency. Returns
+ * zero if the clock source is disabled.
+ */
+uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input);
+
+/**
+ * @brief	Returns the frequency of the specified base clock source
+ * @param	clock	: which base clock to return the frequency of.
+ * @return	Frequency of base source in Hz
+ * This function returns an ideal frequency and not the actual frequency. Returns
+ * zero if the clock source is disabled.
+ */
+uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock);
+
+/**
+ * @brief	Sets a CGU Base Clock clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to set
+ * @param	Input		: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
+ * @param	autoblocken	: Enables autoblocking during frequency change if true
+ * @param	powerdn		: The clock base is setup, but powered down if true
+ * @return	Nothing
+ */
+void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
+
+/**
+ * @brief	Gets a CGU Base Clock clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
+ * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
+ */
+CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Enables a base clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to enable
+ * @return	Nothing
+ */
+void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Disables a base clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to disable
+ * @return	Nothing
+ */
+void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Enables a peripheral clock and sets clock states
+ * @param	clk			: CCU_CLK_T value indicating which clock to enable
+ * @param	autoen		: true to enable autoblocking on a clock rate change, false to disable
+ * @param	wakeupen	: true to enable wakeup mechanism, false to disable
+ * @param	div			: Divider for the clock, must be 1 for most clocks, 2 supported on others
+ * @return	Nothing
+ */
+void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
+
+/**
+ * @brief	Enables a peripheral clock
+ * @param	clk	: CCU_CLK_T value indicating which clock to enable
+ * @return	Nothing
+ */
+void Chip_Clock_Enable(CCU_CLK_T clk);
+
+/**
+ * @brief	Disables a peripheral clock
+ * @param	clk	: CCU_CLK_T value indicating which clock to disable
+ * @return	Nothing
+ */
+void Chip_Clock_Disable(CCU_CLK_T clk);
+
+/**
+ * @brief	Returns a peripheral clock rate
+ * @param	clk	: CCU_CLK_T value indicating which clock to get rate for
+ * @return	0 if the clock is disabled, or the rate of the clock
+ */
+uint32_t Chip_Clock_GetRate(CCU_CLK_T clk);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLOCK_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h

@@ -0,0 +1,355 @@
+/*
+ * @brief Basic CMSIS include file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_H_
+#define __CMSIS_H_
+
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+#if defined(CORE_M4)
+/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions
+ * @{
+ */
+
+#define __CM4_REV              0x0000		/*!< Cortex-M4 Core Revision               */
+#define __MPU_PRESENT             1			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#ifdef CHIP_LPC43XX
+#define __FPU_PRESENT             1			/*!< FPU present or not                    */
+#else
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                       =  -5,/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 =  -4,/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       =  -2,/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      =  -1,/*!<  15  System Tick Timer                */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	M0CORE_IRQn                       =   1,/*!<   1  M0a                              */
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h"						/*!< Cortex-M4 processor and core peripherals */
+
+#elif defined(CORE_M3)
+/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions
+ * @{
+ */
+
+#define __MPU_PRESENT             1			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M3 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer                */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	RESERVED0_IRQn                    =   1,
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	RESERVED3_IRQn                    =  20,
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	RESERVED5_IRQn                    =  31,
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"						/*!< Cortex-M3 processor and core peripherals */
+
+#elif defined(CORE_M0)
+/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
+ * @{
+ */
+
+#define __MPU_PRESENT             0			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          2			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M0 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer           */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	M0_M4CORE_IRQn                        =   1,/*!<   1  M0a                              */
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h"						/*!< Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0, CORE_M3, or CORE_M4
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h

@@ -0,0 +1,181 @@
+/*
+ * @brief LPC18XX/43XX CREG control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CREG_18XX_43XX_H_
+#define __CREG_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief CREG Register Block
+ */
+typedef struct {						/*!< CREG Structure         */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t  CREG0;				/*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
+	__I  uint32_t  RESERVED1[62];
+	__IO uint32_t  MXMEMMAP;			/*!< ARM Cortex-M3/M4 memory mapping */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED2[5];
+#else
+	__I  uint32_t  RESERVED2;
+	__I  uint32_t  CREG1;				/*!< Configuration Register 1 */
+	__I  uint32_t  CREG2;				/*!< Configuration Register 2 */
+	__I  uint32_t  CREG3;				/*!< Configuration Register 3 */
+	__I  uint32_t  CREG4;				/*!< Configuration Register 4 */
+#endif
+	__IO uint32_t  CREG5;				/*!< Chip configuration register 5. Controls JTAG access. */
+	__IO uint32_t  DMAMUX;				/*!< DMA muxing control     */
+	__IO uint32_t  FLASHCFGA;			/*!< Flash accelerator configuration register for flash bank A */
+	__IO uint32_t  FLASHCFGB;			/*!< Flash accelerator configuration register for flash bank B */
+	__IO uint32_t  ETBCFG;				/*!< ETB RAM configuration  */
+	__IO uint32_t  CREG6;				/*!< Chip configuration register 6. */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED4[52];
+#else
+	__IO uint32_t  M4TXEVENT;			/*!< M4 IPC event register */
+	__I  uint32_t  RESERVED4[51];
+#endif
+	__I  uint32_t  CHIPID;				/*!< Part ID                */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED5[191];
+#else
+	__I  uint32_t  RESERVED5[127];
+	__IO uint32_t  M0TXEVENT;			/*!< M0 IPC Event register */
+	__IO uint32_t  M0APPMEMMAP;			/*!< ARM Cortex M0 memory mapping */
+	__I  uint32_t  RESERVED6[62];
+#endif
+	__IO uint32_t  USB0FLADJ;			/*!< USB0 frame length adjust register */
+	__I  uint32_t  RESERVED7[63];
+	__IO uint32_t  USB1FLADJ;			/*!< USB1 frame length adjust register */
+} LPC_CREG_T;
+
+/**
+ * @brief	Identifies whether on-chip flash is present
+ * @return	true if on chip flash is available, otherwise false
+ */
+STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
+{
+	return LPC_CREG->CHIPID != 0x3284E02B;
+}
+
+/**
+ * @brief	Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
+ * @param	Hz	: Current frequency in Hz of the CPU
+ * @return	Nothing
+ * This function should be called with the higher frequency before the clock frequency is
+ * increased and it should be called with the new lower value after the clock frequency is
+ * decreased.
+ */
+STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
+{
+	uint32_t FAValue = Hz / 21510000;
+
+	LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
+	LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
+}
+
+/**
+ * @brief	Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
+ * @param	Enable	: true to enable PHY, false to disable
+ * @return	Nothing
+ * The USB0 PLL & clock should be configured before calling this function. This function
+ * should be called before the USB0 registers are accessed.
+ */
+STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
+{
+	if (Enable) {
+		LPC_CREG->CREG0 &= ~(1 << 5);
+	}
+	else {
+		LPC_CREG->CREG0 |= (1 << 5);
+	}
+}
+
+/**
+ * @brief	Configures the BOD and Reset on LPC18xx/LPC43xx parts.
+ * @param	BODVL	: Brown-Out Detect voltage level (0-3)
+ * @param	BORVL	: Brown-Out Reset voltage level (0-3)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
+{
+	LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
+}
+
+#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
+/**
+ * @brief	Configures base address of image to be run in the Cortex M0 Core.
+ * @param	memaddr	: Address of the image (must be aligned to 4K)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
+{
+	LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
+}
+
+/**
+ * @brief	Clear M4 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM4Event(void)
+{
+	LPC_CREG->M4TXEVENT = 0;
+}
+
+/**
+ * @brief	Clear M0 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM0Event(void)
+{
+	LPC_CREG->M0TXEVENT = 0;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CREG_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c

@@ -0,0 +1,89 @@
+/*
+ * @brief LPC18xx/43xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "emc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Dyanmic memory setup */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27
+	    TODO: just checked but dont mention in UM */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq);
+}
+
+/* Static memory setup */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27 */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h

@@ -0,0 +1,156 @@
+/*
+ * @brief LPC18xx/43xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EMC_18XX_43XX_H_
+#define __EMC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * Dynamic Chip Select Address
+ */
+#define EMC_ADDRESS_DYCS0   (0x28000000)
+#define EMC_ADDRESS_DYCS1   (0x30000000)
+#define EMC_ADDRESS_DYCS2   (0x60000000)
+#define EMC_ADDRESS_DYCS3   (0x70000000)
+
+/**
+ * Static Chip Select Address
+ */
+#define EMC_ADDRESS_CS0     (0x1C000000)
+#define EMC_ADDRESS_CS1     (0x1D000000)
+#define EMC_ADDRESS_CS2     (0x1E000000)
+#define EMC_ADDRESS_CS3     (0x1F000000)
+
+/**
+ * @brief	Dyanmic memory setup
+ * @param	Dynamic_Config	: Pointer to dynamic memory setup data
+ * @return	None
+ */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config);
+
+/**
+ * @brief	Static memory setup
+ * @param	Static_Config	: Pointer to static memory setup data
+ * @return	None
+ */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config);
+
+/**
+ * @brief	Set Deep Sleep Mode for Dynamic Memory Controller
+ * @param	Enable	: 1 = enter DeepSleep Mode, 0 = Normal Mode
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Dynamic_DeepSleepMode(uint32_t Enable)
+{
+	IP_EMC_Dynamic_DeepSleepMode(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Enable Dynamic Memory Controller
+ * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)
+{
+	IP_EMC_Dynamic_Enable(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Mirror CS1 to CS0 and DYCS0
+ * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)
+{
+	IP_EMC_Mirror(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Enable EMC
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)
+{
+	IP_EMC_Enable(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Set EMC LowPower Mode
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)
+{
+	IP_EMC_LowPowerMode(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Initialize EMC
+ * @param	Enable		: 1 = Enable, 0 = Disable
+ * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
+ * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
+{
+	IP_EMC_Init(LPC_EMC, Enable, ClockRatio, EndianMode);
+}
+
+/**
+ * @brief	Set Static Memory Extended Wait in Clock
+ * @param	Wait16Clks	: Number of '16 clock' delay cycles
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
+{
+	IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c

@@ -0,0 +1,82 @@
+/*
+ * @brief LPC18xx/43xx ethernet driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "enet_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Basic Ethernet interface initialization */
+void Chip_ENET_Init(void)
+{
+	LPC_CREG->CREG6 &= ~0x7;
+
+	/* Enable ethernet clock */
+	Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
+
+	/* PHY TX/RX base clock routing is setup as part of SystemInit() */
+
+#if defined(USE_RMII)
+	LPC_CREG->CREG6 |= 0x4;
+#endif
+
+	/* Reset ethernet and wait for reset to complete */
+	Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
+	while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
+
+	/* Reset ethernet peripheral */
+	Chip_ENET_Reset();
+
+	/* Setup MII link divider to /102 and PHY address 1 */
+	Chip_ENET_Setup_MII(4, 1);
+
+	IP_ENET_Init(LPC_ETHERNET);
+}
+
+/* Ethernet interface shutdown */
+void Chip_ENET_DeInit(void)
+{
+	IP_ENET_DeInit(LPC_ETHERNET);
+	Chip_Clock_Disable(CLK_MX_ETHERNET);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h

@@ -0,0 +1,230 @@
+/*
+ * @brief LPC18xx/43xx ethernet driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ENET_18XX_43XX_H_
+#define __ENET_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options
+ * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
+ * The ethernet driver has options that configure it's operation at build-time.<br/>
+ * USE_RMII:
+ * - When defined, the driver will be built for RMII operation.
+ * - When not defined, the driver will be built for MII operation.
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief	Initialize ethernet interface
+ * @return	Nothing
+ * Performs basic initialization of the ethernet interface in a default
+ * state. This is enough to place the interface in a usable state, but
+ * may require more setup outside this function.
+ */
+void Chip_ENET_Init(void);
+
+/**
+ * @brief	De-initialize the ethernet interface
+ * @return	Nothing
+ */
+void Chip_ENET_DeInit(void);
+
+/**
+ * @brief	Resets the ethernet interface
+ * @return	Nothing
+ * Resets the ethernet interface. This should be called prior to
+ * Chip_ENET_Init with a small delay after this call.
+ */
+STATIC INLINE void Chip_ENET_Reset(void)
+{
+	IP_ENET_Reset(LPC_ETHERNET);
+}
+
+/**
+ * @brief	Sets the address of the interface
+ * @param	macAddr	: Pointer to the 6 bytes used for the MAC address
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_SetADDR(const uint8_t *macAddr)
+{
+	IP_ENET_SetADDR(LPC_ETHERNET, macAddr);
+}
+
+/**
+ * @brief	Sets up the PHY link clock divider and PHY address
+ * @param	div		: Divider value, may vary per chip
+ * @param	addr	: PHY address, used with MII read and write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_Setup_MII(uint32_t div, uint8_t addr)
+{
+	IP_ENET_SetupMII(LPC_ETHERNET, div, addr);
+}
+
+/**
+ * @brief	Starts a PHY write via the MII
+ * @param	reg		: PHY register to write
+ * @param	data	: Data to write to PHY register
+ * @return	Nothing
+ * Start a PHY write operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when write is complete.
+ */
+STATIC INLINE void Chip_ENET_Start_MII_Write(uint8_t reg, uint16_t data)
+{
+	IP_ENET_StartMIIWrite(LPC_ETHERNET, reg, data);
+}
+
+/**
+ * @brief	Starts a PHY read via the MII
+ * @param	reg	: PHY register to read
+ * @return	Nothing
+ * Start a PHY read operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when read is complete and calling
+ * IP_ENET_ReadMIIData to get the data.
+ */
+STATIC INLINE void Chip_ENET_Start_MII_Read(uint8_t reg)
+{
+	IP_ENET_StartMIIRead(LPC_ETHERNET, reg);
+}
+
+/**
+ * @brief	Returns MII link (PHY) busy status
+ * @return	Returns true if busy, otherwise false
+ */
+STATIC INLINE bool Chip_ENET_Is_MII_Busy(void)
+{
+	return IP_ENET_IsMIIBusy(LPC_ETHERNET);
+}
+
+/**
+ * @brief	Returns the value read from the PHY
+ * @return	Read value from PHY
+ */
+STATIC INLINE uint16_t Chip_ENET_Read_MII_Data(void)
+{
+	return IP_ENET_ReadMIIData(LPC_ETHERNET);
+}
+
+/**
+ * @brief	Enables or disables ethernet transmit
+ * @param	Enable	: true to enable transmit, false to disable
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_TX_Enable(bool Enable)
+{
+	IP_ENET_TXEnable(LPC_ETHERNET, Enable);
+}
+
+/**
+ * @brief	Enables or disables ethernet packet reception
+ * @param	Enable	: true to enable receive, false to disable
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_RX_Enable(bool Enable)
+{
+	IP_ENET_RXEnable(LPC_ETHERNET, Enable);
+}
+
+/**
+ * @brief	Sets full or half duplex for the interface
+ * @param	full	: true to selected full duplex, false for half
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_Set_Duplex(bool full)
+{
+	IP_ENET_SetDuplex(LPC_ETHERNET, full);
+}
+
+/**
+ * @brief	Sets speed for the interface
+ * @param	speed100	: true to select 100Mbps mode, false for 10Mbps
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_Set_Speed(bool speed100)
+{
+	IP_ENET_SetSpeed(LPC_ETHERNET, speed100);
+}
+
+/**
+ * @brief	Configures the initial ethernet descriptors
+ * @param	pTXDescs	: Pointer to TX descriptor list
+ * @param	pRXDescs	: Pointer to RX descriptor list
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_InitDescriptors(
+	IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs)
+{
+	IP_ENET_InitDescriptors(LPC_ETHERNET, pTXDescs, pRXDescs);
+}
+
+/**
+ * @brief	Starts receive polling of RX descriptors
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_RXStart(void)
+{
+	IP_ENET_RXStart(LPC_ETHERNET);
+}
+
+/**
+ * @brief	Starts transmit polling of TX descriptors
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_TXStart(void)
+{
+	IP_ENET_TXStart(LPC_ETHERNET);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ENET_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c

@@ -0,0 +1,111 @@
+/*
+ * @brief LPC18xx/43xx event router driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "evrt_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the EVRT */
+void Chip_EVRT_Init(void)
+{
+	uint8_t i = 0;
+	// Clear all register to be default
+	LPC_EVRT->HILO      = 0x0000;
+	LPC_EVRT->EDGE      = 0x0000;
+	LPC_EVRT->CLR_EN    = 0xFFFF;
+	do {
+		i++;
+		LPC_EVRT->CLR_STAT  = 0xFFFFF;
+	} while ((LPC_EVRT->STATUS != 0) && (i < 10));
+}
+
+/* Set up the type of interrupt type for a source to EVRT */
+void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)
+{
+	switch (type) {
+	case EVRT_SRC_ACTIVE_LOW_LEVEL:
+		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_HIGH_LEVEL:
+		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_FALLING_EDGE:
+		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_RISING_EDGE:
+		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/* Enable or disable interrupt sources to EVRT */
+void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state)
+{
+	if (state == ENABLE) {
+		LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src);
+	}
+	else {
+		LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src);
+	}
+}
+
+/* Check if a source is sending interrupt to EVRT */
+IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src)
+{
+	if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) {
+		return SET;
+	}
+	else {return RESET; }
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h

@@ -0,0 +1,173 @@
+/*
+ * @brief LPC18xx/43xx event router driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EVRT_18XX_43XX_H_
+#define __EVRT_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Event Router register structure
+ */
+typedef struct {						/*!< EVENTROUTER Structure  */
+	__IO uint32_t HILO;					/*!< Level configuration register */
+	__IO uint32_t EDGE;					/*!< Edge configuration     */
+	__I  uint32_t RESERVED0[1012];
+	__O  uint32_t CLR_EN;				/*!< Event clear enable register */
+	__O  uint32_t SET_EN;				/*!< Event set enable register */
+	__I  uint32_t STATUS;				/*!< Status register        */
+	__I  uint32_t ENABLE;				/*!< Enable register        */
+	__O  uint32_t CLR_STAT;				/*!< Clear register         */
+	__O  uint32_t SET_STAT;				/*!< Set register           */
+} LPC_EVRT_Type;
+
+/**
+ * @brief EVRT input sources
+ */
+typedef enum {
+	EVRT_SRC_WAKEUP0,			/*!< WAKEUP0 event router source		*/
+	EVRT_SRC_WAKEUP1,			/*!< WAKEUP1 event router source		*/
+	EVRT_SRC_WAKEUP2,			/*!< WAKEUP2 event router source		*/
+	EVRT_SRC_WAKEUP3,			/*!< WAKEUP3 event router source		*/
+	EVRT_SRC_ATIMER,			/*!< Alarm timer event router source	*/
+	EVRT_SRC_RTC,				/*!< RTC event router source			*/
+	EVRT_SRC_BOD1,				/*!< BOD event router source			*/
+	EVRT_SRC_WWDT,				/*!< WWDT event router source			*/
+	EVRT_SRC_ETHERNET,			/*!< Ethernet event router source		*/
+	EVRT_SRC_USB0,				/*!< USB0 event router source			*/
+	EVRT_SRC_USB1,				/*!< USB1 event router source			*/
+	EVRT_SRC_SDIO,				/*!< Reserved							*/
+	EVRT_SRC_CCAN,				/*!< C_CAN event router source			*/
+	EVRT_SRC_COMBINE_TIMER2,	/*!< Combined timer 2 event router source	*/
+	EVRT_SRC_COMBINE_TIMER6,	/*!< Combined timer 6 event router source	*/
+	EVRT_SRC_QEI,				/*!< QEI event router source			*/
+	EVRT_SRC_COMBINE_TIMER14,	/*!< Combined timer 14 event router source	*/
+	EVRT_SRC_RESERVED1,			/*!< Reserved                           */
+	EVRT_SRC_RESERVED2,			/*!< Reserved							*/
+	EVRT_SRC_RESET				/*!< Reset event router source			*/
+} Chip_EVRT_SRC_ENUM;
+
+/**
+ * @brief Macro for checking for a valid EVRT source
+ */
+#define PARAM_EVRT_SOURCE(n)    ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1)	\
+								 || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
+								 || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
+								 || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
+								 || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
+								 || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
+								 || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
+								 || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
+								 || (n == EVRT_SRC_RESET)) \
+
+/**
+ * @brief EVRT input state detecting type
+ */
+typedef enum {
+	EVRT_SRC_ACTIVE_LOW_LEVEL,		/*!< Active low level       */
+	EVRT_SRC_ACTIVE_HIGH_LEVEL,		/*!< Active high level		*/
+	EVRT_SRC_ACTIVE_FALLING_EDGE,	/*!< Active falling edge	*/
+	EVRT_SRC_ACTIVE_RISING_EDGE		/*!< Active rising edge		*/
+} EVRT_SRC_ACTIVE_TYPE;
+
+/**
+ * @brief Macro for checking for a valid EVRT state type
+ */
+#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL)	\
+										  || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
+
+/**
+ * @brief	Initialize the EVRT
+ * @return	Nothing
+ */
+void Chip_EVRT_Init (void);
+
+/**
+ * @brief	Set up the type of interrupt type for a source to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @param	type		: EVRT type, should be one of EVRT_SRC_ACTIVE_TYPE type
+ * @return	Nothing
+ */
+void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
+
+/**
+ * @brief	Check if a source is sending interrupt to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @return	true if the interrupt from the source is pending, otherwise false
+ */
+IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src);
+
+/**
+ * @brief	Enable or disable interrupt sources to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @param	state		: ENABLE or DISABLE to enable or disable event router source
+ * @return	Nothing
+ */
+void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
+
+/**
+ * @brief	De-initializes the EVRT peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EVRT_DeInit(void)
+{
+	LPC_EVRT->CLR_EN    = 0xFFFF;
+	LPC_EVRT->CLR_STAT  = 0xFFFF;
+}
+
+/**
+ * @brief	Clear pending interrupt EVRT source
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EVRT_ClrPendIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src)
+{
+	LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EVRT_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c

@@ -0,0 +1,424 @@
+/*
+ * @brief LPC18xx/43xx DMA driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "gpdma_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Channel array to monitor free channel */
+static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS];
+
+/* Optimized Peripheral Source and Destination burst size (18xx,43xx) */
+static const uint8_t GPDMA_LUTPerBurst[] = {
+	GPDMA_BSIZE_4,	/* MEMORY             */
+	GPDMA_BSIZE_1,	/* MAT0.0             */
+	GPDMA_BSIZE_1,	/* UART0 Tx           */
+	GPDMA_BSIZE_1,	/* MAT0.1             */
+	GPDMA_BSIZE_1,	/* UART0 Rx           */
+	GPDMA_BSIZE_1,	/* MAT1.0             */
+	GPDMA_BSIZE_1,	/* UART1 Tx           */
+	GPDMA_BSIZE_1,	/* MAT1.1             */
+	GPDMA_BSIZE_1,	/* UART1 Rx           */
+	GPDMA_BSIZE_1,	/* MAT2.0             */
+	GPDMA_BSIZE_1,	/* UART2 Tx           */
+	GPDMA_BSIZE_1,	/* MAT2.1             */
+	GPDMA_BSIZE_1,	/* UART2 Rx           */
+	GPDMA_BSIZE_1,	/* MAT3.0             */
+	GPDMA_BSIZE_1,	/* UART3 Tx           */
+	0,				/* SCT timer channel 0*/
+	GPDMA_BSIZE_1,	/* MAT3.1             */
+	GPDMA_BSIZE_1,	/* UART3 Rx           */
+	0,				/* SCT timer channel 1*/
+	GPDMA_BSIZE_4,	/* SSP0 Rx            */
+	GPDMA_BSIZE_32,	/* I2S channel 0      */
+	GPDMA_BSIZE_4,	/* SSP0 Tx            */
+	GPDMA_BSIZE_32,	/* I2S channel 1      */
+	GPDMA_BSIZE_4,	/* SSP1 Rx            */
+	GPDMA_BSIZE_4,	/* SSP1 Tx            */
+	GPDMA_BSIZE_4,	/* ADC 0              */
+	GPDMA_BSIZE_4,	/* ADC 1              */
+	GPDMA_BSIZE_1,	/* DAC                */
+	GPDMA_BSIZE_32,	/* I2S channel 0      */
+	GPDMA_BSIZE_32	/* I2S channel 0      */
+};
+
+/* Optimized Peripheral Source and Destination transfer width (18xx,43xx) */
+static const uint8_t GPDMA_LUTPerWid[] = {
+	GPDMA_WIDTH_WORD,	/* MEMORY             */
+	GPDMA_WIDTH_WORD,	/* MAT0.0             */
+	GPDMA_WIDTH_BYTE,	/* UART0 Tx           */
+	GPDMA_WIDTH_WORD,	/* MAT0.1             */
+	GPDMA_WIDTH_BYTE,	/* UART0 Rx           */
+	GPDMA_WIDTH_WORD,	/* MAT1.0             */
+	GPDMA_WIDTH_BYTE,	/* UART1 Tx           */
+	GPDMA_WIDTH_WORD,	/* MAT1.1             */
+	GPDMA_WIDTH_BYTE,	/* UART1 Rx           */
+	GPDMA_WIDTH_WORD,	/* MAT2.0             */
+	GPDMA_WIDTH_BYTE,	/* UART2 Tx           */
+	GPDMA_WIDTH_WORD,	/* MAT2.1             */
+	GPDMA_WIDTH_BYTE,	/* UART2 Rx           */
+	GPDMA_WIDTH_WORD,	/* MAT3.0             */
+	GPDMA_WIDTH_BYTE,	/* UART3 Tx           */
+	0,					/* SCT timer channel 0*/
+	GPDMA_WIDTH_WORD,	/* MAT3.1             */
+	GPDMA_WIDTH_BYTE,	/* UART3 Rx           */
+	0,					/* SCT timer channel 1*/
+	GPDMA_WIDTH_BYTE,	/* SSP0 Rx            */
+	GPDMA_WIDTH_WORD,	/* I2S channel 0      */
+	GPDMA_WIDTH_BYTE,	/* SSP0 Tx            */
+	GPDMA_WIDTH_WORD,	/* I2S channel 1      */
+	GPDMA_WIDTH_BYTE,	/* SSP1 Rx            */
+	GPDMA_WIDTH_BYTE,	/* SSP1 Tx            */
+	GPDMA_WIDTH_WORD,	/* ADC 0              */
+	GPDMA_WIDTH_WORD,	/* ADC 1              */
+	GPDMA_WIDTH_WORD,	/* DAC                */
+	GPDMA_WIDTH_WORD,	/* I2S channel 0      */
+	GPDMA_WIDTH_WORD/* I2S channel 0      */
+};
+
+/* Lookup Table of Connection Type matched with (18xx,43xx) Peripheral Data (FIFO) register base address */
+volatile static const void *GPDMA_LUTPerAddr[] = {
+	NULL,							/* MEMORY             */
+	(&LPC_TIMER0->MR),				/* MAT0.0             */
+	(&LPC_USART0-> /*RBTHDLR.*/ THR),	/* UART0 Tx           */
+	((uint32_t *) &LPC_TIMER0->MR + 1),	/* MAT0.1             */
+	(&LPC_USART0-> /*RBTHDLR.*/ RBR),	/* UART0 Rx           */
+	(&LPC_TIMER1->MR),				/* MAT1.0             */
+	(&LPC_UART1-> /*RBTHDLR.*/ THR),/* UART1 Tx           */
+	((uint32_t *) &LPC_TIMER1->MR + 1),	/* MAT1.1             */
+	(&LPC_UART1-> /*RBTHDLR.*/ RBR),/* UART1 Rx           */
+	(&LPC_TIMER2->MR),				/* MAT2.0             */
+	(&LPC_USART2-> /*RBTHDLR.*/ THR),	/* UART2 Tx           */
+	((uint32_t *) &LPC_TIMER2->MR + 1),	/* MAT2.1             */
+	(&LPC_USART2-> /*RBTHDLR.*/ RBR),	/* UART2 Rx           */
+	(&LPC_TIMER3->MR),				/* MAT3.0             */
+	(&LPC_USART3-> /*RBTHDLR.*/ THR),	/* UART3 Tx           */
+	0,								/* SCT timer channel 0*/
+	((uint32_t *) &LPC_TIMER3->MR + 1),	/* MAT3.1             */
+	(&LPC_USART3-> /*RBTHDLR.*/ RBR),	/* UART3 Rx           */
+	0,								/* SCT timer channel 1*/
+	(&LPC_SSP0->DR),				/* SSP0 Rx            */
+	(&LPC_I2S0->TXFIFO),			/* I2S channel 0      */
+	(&LPC_SSP0->DR),				/* SSP0 Tx            */
+	(&LPC_I2S0->RXFIFO),			/* I2S channel 1      */
+	(&LPC_SSP1->DR),				/* SSP1 Rx            */
+	(&LPC_SSP1->DR),				/* SSP1 Tx            */
+	(&LPC_ADC0->GDR),				/* ADC 0              */
+	(&LPC_ADC1->GDR),				/* ADC 1              */
+	(&LPC_DAC->CR),					/* DAC                */
+	(&LPC_I2S0->TXFIFO),			/* I2S channel 0      */
+	(&LPC_I2S0->RXFIFO)				/* I2S channel 0      */
+};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Control which set of peripherals is connected to the DMA controller */
+static uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)
+{
+	uint8_t function, channel;
+
+	switch (gpdma_peripheral_connection_number) {
+	case GPDMA_CONN_MAT0_0:
+		function = 0;
+		channel = 1;
+		break;
+
+	case GPDMA_CONN_UART0_Tx:
+		function = 1;
+		channel = 1;
+		break;
+
+	case GPDMA_CONN_MAT0_1:
+		function = 0;
+		channel = 2;
+		break;
+
+	case GPDMA_CONN_UART0_Rx:
+		function = 1;
+		channel = 2;
+		break;
+
+	case GPDMA_CONN_MAT1_0:
+		function = 0;
+		channel = 3;
+		break;
+
+	case GPDMA_CONN_UART1_Tx:
+		function = 1;
+		channel = 3;
+		break;
+
+	case GPDMA_CONN_MAT1_1:
+		function = 0;
+		channel = 4;
+		break;
+
+	case GPDMA_CONN_UART1_Rx:
+		function = 1;
+		channel = 4;
+		break;
+
+	case GPDMA_CONN_MAT2_0:
+		function = 0;
+		channel = 5;
+		break;
+
+	case GPDMA_CONN_UART2_Tx:
+		function = 1;
+		channel = 5;
+		break;
+
+	case GPDMA_CONN_MAT2_1:
+		function = 0;
+		channel = 6;
+		break;
+
+	case GPDMA_CONN_UART2_Rx:
+		function = 1;
+		channel = 6;
+		break;
+
+	case GPDMA_CONN_MAT3_0:
+		function = 0;
+		channel = 7;
+		break;
+
+	case GPDMA_CONN_UART3_Tx:
+		function = 1;
+		channel = 7;
+		break;
+
+	case GPDMA_CONN_SCT_0:
+		function = 2;
+		channel = 7;
+		break;
+
+	case GPDMA_CONN_MAT3_1:
+		function = 0;
+		channel = 8;
+		break;
+
+	case GPDMA_CONN_UART3_Rx:
+		function = 1;
+		channel = 8;
+		break;
+
+	case GPDMA_CONN_SCT_1:
+		function = 2;
+		channel = 8;
+		break;
+
+	case GPDMA_CONN_SSP0_Rx:
+		function = 0;
+		channel = 9;
+		break;
+
+	case GPDMA_CONN_I2S_Tx_Channel_0:
+	case GPDMA_CONN_I2S_Rx_Channel_0:
+		function = 1;
+		channel = 9;
+		break;
+
+	case GPDMA_CONN_SSP0_Tx:
+		function = 0;
+		channel = 10;
+		break;
+
+	case GPDMA_CONN_I2S_Tx_Channel_1:
+	case GPDMA_CONN_I2S_Rx_Channel_1:
+		function = 1;
+		channel = 10;
+		break;
+
+	case GPDMA_CONN_SSP1_Rx:
+		function = 0;
+		channel = 11;
+		break;
+
+	case GPDMA_CONN_SSP1_Tx:
+		function = 0;
+		channel = 12;
+		break;
+
+	case GPDMA_CONN_ADC_0:
+		function = 0;
+		channel = 13;
+		break;
+
+	case GPDMA_CONN_ADC_1:
+		function = 0;
+		channel = 14;
+		break;
+
+	case GPDMA_CONN_DAC:
+		function = 0;
+		channel = 15;
+		break;
+
+	default:
+		function = 3;
+		channel = 15;
+		break;
+	}
+	/* Set select function to dmamux register */
+	if (0 != gpdma_peripheral_connection_number) {
+		LPC_CREG->DMAMUX &= ~(0x03 << (2 * channel));
+		LPC_CREG->DMAMUX |= (function << (2 * channel));
+	}
+	return channel;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the GPDMA */
+void Chip_GPDMA_Init(void)
+{
+	uint8_t i;
+	IP_GPDMA_Init(LPC_GPDMA);
+	/* Reset all channels are free */
+	for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++)
+		ChannelHandlerArray[i].ChannelStatus = DISABLE;
+}
+
+/* Stop a stream DMA transfer */
+void Chip_DMA_Stop(uint8_t ChannelNum)
+{
+	IP_GPDMA_ChannelCmd(LPC_GPDMA, (ChannelNum), DISABLE);
+	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
+		/* Clear terminate counter Interrupt pending */
+		Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
+	}
+	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
+		/* Clear terminate counter Interrupt pending */
+		Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
+	}
+	ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE;
+}
+
+/* The GPDMA stream interrupt status checking */
+Status Chip_DMA_Interrupt(uint8_t ChannelNum)
+{
+
+	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INT, ChannelNum)) {
+		/* Check counter terminal status */
+		if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
+			/* Clear terminate counter Interrupt pending */
+			Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
+			return SUCCESS;
+		}
+		/* Check error terminal status */
+		if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
+			/* Clear error counter Interrupt pending */
+
+			Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
+			return ERROR;
+		}
+	}
+	return ERROR;
+}
+
+/* Do a DMA transfer M2M, M2P,P2M or P2P */
+void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size)
+{
+	GPDMA_Channel_CFG_Type GPDMACfg;
+	uint8_t SrcPeripheral = 0, DstPeripheral = 0;
+
+	GPDMACfg.ChannelNum = ChannelNum;
+	GPDMACfg.TransferType = TransferType;
+	GPDMACfg.TransferSize = Size;
+
+	switch (TransferType) {
+	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
+		GPDMACfg.SrcAddr = (uint32_t) src;
+		GPDMACfg.DstAddr = (uint32_t) dst;
+		src = 0; dst = 0;
+		GPDMACfg.TransferWidth = GPDMA_WIDTH_BYTE;
+		break;
+
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
+		GPDMACfg.SrcAddr = (uint32_t) src;
+		src = 0;
+		GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
+		DstPeripheral = DMAMUX_Config(dst);
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
+		GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
+		GPDMACfg.DstAddr = (uint32_t) dst;
+		SrcPeripheral = DMAMUX_Config(src);
+		dst = 0;
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
+		GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
+		GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
+		SrcPeripheral = DMAMUX_Config(src);
+		DstPeripheral = DMAMUX_Config(dst);
+		break;
+
+	default:
+		break;
+	}
+
+	IP_GPDMA_Setup(LPC_GPDMA, &GPDMACfg, (uint32_t) GPDMA_LUTPerBurst[src], (uint32_t) GPDMA_LUTPerBurst[dst],
+				   (uint32_t) GPDMA_LUTPerWid[src], (uint32_t) GPDMA_LUTPerWid[dst], (uint32_t) GPDMA_LUTPerAddr[src],
+				   (uint32_t) GPDMA_LUTPerAddr[dst], SrcPeripheral, DstPeripheral);
+
+	/* Start the Channel */
+	IP_GPDMA_ChannelCmd(LPC_GPDMA, ChannelNum, ENABLE);
+}
+
+/* Get a free GPDMA channel for one DMA connection */
+uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID)
+{
+	uint8_t temp = 0;
+	for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++)
+		if (!Chip_GPDMA_IntGetStatus(GPDMA_STAT_ENABLED_CH,
+									 temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) {
+			ChannelHandlerArray[temp].ChannelStatus = ENABLE;
+			return temp;
+		}
+	return 0;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h

@@ -0,0 +1,167 @@
+/*
+ * @brief LPC18xx/43xx DMA driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPDMA_18XX_43XX_H_
+#define __GPDMA_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** Number of channels on GPDMA */
+#define GPDMA_NUMBER_CHANNELS 8
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_MEMORY           ((0UL))			/**< MEMORY             */
+#define GPDMA_CONN_MAT0_0           ((1UL))			/**< MAT0.0             */
+#define GPDMA_CONN_UART0_Tx         ((2UL))			/**< UART0 Tx           */
+#define GPDMA_CONN_MAT0_1           ((3UL))			/**< MAT0.1             */
+#define GPDMA_CONN_UART0_Rx         ((4UL))			/**< UART0 Rx           */
+#define GPDMA_CONN_MAT1_0           ((5UL))			/**< MAT1.0             */
+#define GPDMA_CONN_UART1_Tx         ((6UL))			/**< UART1 Tx           */
+#define GPDMA_CONN_MAT1_1           ((7UL))			/**< MAT1.1             */
+#define GPDMA_CONN_UART1_Rx         ((8UL))			/**< UART1 Rx           */
+#define GPDMA_CONN_MAT2_0           ((9UL))			/**< MAT2.0             */
+#define GPDMA_CONN_UART2_Tx         ((10UL))		/**< UART2 Tx           */
+#define GPDMA_CONN_MAT2_1           ((11UL))		/**< MAT2.1             */
+#define GPDMA_CONN_UART2_Rx         ((12UL))		/**< UART2 Rx           */
+#define GPDMA_CONN_MAT3_0           ((13UL))		/**< MAT3.0             */
+#define GPDMA_CONN_UART3_Tx         ((14UL))		/**< UART3 Tx           */
+#define GPDMA_CONN_SCT_0            ((15UL))		/**< SCT timer channel 0*/
+#define GPDMA_CONN_MAT3_1           ((16UL))		/**< MAT3.1             */
+#define GPDMA_CONN_UART3_Rx         ((17UL))		/**< UART3 Rx           */
+#define GPDMA_CONN_SCT_1            ((18UL))		/**< SCT timer channel 1*/
+#define GPDMA_CONN_SSP0_Rx          ((19UL))		/**< SSP0 Rx            */
+#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))		/**< I2S channel 0      */
+#define GPDMA_CONN_SSP0_Tx          ((21UL))		/**< SSP0 Tx            */
+#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))		/**< I2S channel 1      */
+#define GPDMA_CONN_SSP1_Rx          ((23UL))		/**< SSP1 Rx            */
+#define GPDMA_CONN_SSP1_Tx          ((24UL))		/**< SSP1 Tx            */
+#define GPDMA_CONN_ADC_0            ((25UL))		/**< ADC 0              */
+#define GPDMA_CONN_ADC_1            ((26UL))		/**< ADC 1              */
+#define GPDMA_CONN_DAC              ((27UL))		/**< DAC                */
+#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL))		/**< I2S channel 0      */
+#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL))		/**< I2S channel 0      */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1   ((0UL))	/**< Burst size = 1 */
+#define GPDMA_BSIZE_4   ((1UL))	/**< Burst size = 4 */
+#define GPDMA_BSIZE_8   ((2UL))	/**< Burst size = 8 */
+#define GPDMA_BSIZE_16  ((3UL))	/**< Burst size = 16 */
+#define GPDMA_BSIZE_32  ((4UL))	/**< Burst size = 32 */
+#define GPDMA_BSIZE_64  ((5UL))	/**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL))	/**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL))	/**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE        ((0UL))	/**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD    ((1UL))	/**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD        ((2UL))	/**< Width = 4 bytes */
+
+/** Flow control definitions */
+#define DMA_CONTROLLER 0		/**< Flow control is DMA controller*/
+#define SRC_PER_CONTROLLER 1	/**< Flow control is Source peripheral controller*/
+#define DST_PER_CONTROLLER 2	/**< Flow control is Destination peripheral controller*/
+
+typedef struct {
+	FunctionalState ChannelStatus;
+} DMA_ChannelHandle_t;
+
+#define Chip_GPDMA_IntGetStatus(type, channel) IP_GPDMA_IntGetStatus(LPC_GPDMA, type, channel)
+
+#define Chip_GPDMA_ClearIntPending(type, channel) IP_GPDMA_ClearIntPending(LPC_GPDMA, type, channel)
+
+#define Chip_GPDMA_ChannelCmd(channelNum, NewState) IP_GPDMA_ChannelCmd(LPC_GPDMA, channelNum, NewState)
+
+/**
+ * @brief	Initialize the GPDMA
+ * @return	Nothing
+ */
+void Chip_GPDMA_Init(void);
+
+/**
+ * @brief	Stop a stream DMA transfer
+ * @param	ChannelNum	:	Channel Number to be closed
+ * @return	Nothing
+ */
+void Chip_DMA_Stop(uint8_t ChannelNum);
+
+/**
+ * @brief	The GPDMA stream interrupt status checking
+ * @param	ChannelNum		:	Channel Number to be checked on interruption
+ * @return	Status:
+ *              - SUCCESS	: DMA transfer success
+ *              - ERROR		: DMA transfer failed
+ */
+Status  Chip_DMA_Interrupt(uint8_t ChannelNum);
+
+/**
+ * @brief	Get a free GPDMA channel for one DMA connection
+ * @param	PeripheralConnection_ID		:	Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
+ * @return	The channel number which is selected
+ */
+uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID);
+
+/**
+ * @brief	Do a DMA transfer M2M, M2P,P2M or P2P
+ * @param	ChannelNum		:	Channel used for transfer
+ * @param	src				:	Address of Memory or PeripheralConnection_ID which is the source
+ * @param	dst				:	Address of Memory or PeripheralConnection_ID which is the destination
+ * @param	TransferType	:	Select the transfer controller and the type of transfer. Should be:
+ *                               - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
+ * @param	Size			:	The number of DMA transfers
+ * @return	Nothing
+ */
+void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPDMA_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c

@@ -0,0 +1,53 @@
+/** @brief LPC18xx/43xx GPIO driver** Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "gpio_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set Direction for a GPIO port */
+void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	if (out) {
+		LPC_GPIO_PORT->DIR[portNum] |= bitValue;
+	}
+	else {
+		LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h

@@ -0,0 +1,308 @@
+/*
+ * @brief LPC18xx/43xx GPIO driver
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_18XX_43XX_H_
+#define __GPIO_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize GPIO block
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_Init(void)
+{
+	IP_GPIO_Init(LPC_GPIO_PORT);
+}
+
+/**
+ * @brief	Set a GPIO port/bit state
+ * @param	Port	: GPIO port to set
+ * @param	Bit		: GPIO bit to set
+ * @param	Setting	: true for high, false for low
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_WritePortBit(uint32_t Port, uint8_t Bit, bool Setting)
+{
+	IP_GPIO_WritePortBit(LPC_GPIO_PORT, Port, Bit, Setting);
+}
+
+/**
+ * @brief	Seta GPIO direction
+ * @param	Port	: GPIO port to set
+ * @param	Bit		: GPIO bit to set
+ * @param	Setting	: true for output, false for input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_WriteDirBit(uint32_t Port, uint8_t Bit, bool Setting)
+{
+	IP_GPIO_WriteDirBit(LPC_GPIO_PORT, Port, Bit, Setting);
+}
+
+/**
+ * @brief	Read a GPIO state
+ * @param	Port	: GPIO port to read
+ * @param	Bit		: GPIO bit to read
+ * @return	true of the GPIO is high, false if low
+ */
+STATIC INLINE bool Chip_GPIO_ReadPortBit(uint32_t Port, uint8_t Bit)
+{
+	return IP_GPIO_ReadPortBit(LPC_GPIO_PORT, Port, Bit);
+}
+
+/**
+ * @brief	Read a GPIO direction (out ot in)
+ * @param	Port	: GPIO port to read
+ * @param	Bit		: GPIO bit to read
+ * @return	true of the GPIO is an output, false if input
+ */
+STATIC INLINE bool Chip_GPIO_ReadDirBit(uint32_t Port, uint8_t Bit)
+{
+	return IP_GPIO_ReadDirBit(LPC_GPIO_PORT, Port, Bit);
+}
+
+/**
+ * @brief	Enable GPIO Interrupt
+ * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
+ * @param	BitValue	: GPIO bit to enable (Not used)
+ * @param	IntMode		: Interrupt mode, should be:
+ *							0: Rising edge interrupt mode
+ *							1: Falling edge interrupt mode
+ *							2: Active-High interrupt mode
+ *							3: Active-Low interrupt mode
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIO_IntCmd(uint8_t PortNum, uint8_t BitValue, Gpio_PinInt_Mode_Enum IntMode)
+{
+	IP_GPIOPININT_IntCmd(LPC_GPIO_PIN_INT, PortNum, IntMode);
+}
+
+/**
+ * @brief	Get GPIO Interrupt Status
+ * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
+ * @param	PinNum		: GPIO pin to check (Not used)
+ * @param	IntMode		: Interrupt mode (Not used)
+ * @return	true if interrupt is pending, otherwise false
+ */
+STATIC INLINE bool Chip_GPIO_IntGetStatus(uint8_t PortNum, uint8_t PinNum, uint8_t IntMode)
+{
+	return IP_GPIOPININT_IntGetStatus(LPC_GPIO_PIN_INT, PortNum);
+}
+
+/**
+ * @brief	Clear GPIO Interrupt (Edge interrupt cases only)
+ * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
+ * @param	BitValue	: GPIO bit to clear (Not used)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIO_IntClear(uint8_t PortNum, uint8_t BitValue)
+{
+	IP_GPIOPININT_IntClear(LPC_GPIO_PIN_INT, PortNum);
+}
+
+/**
+ * @brief	GPIO Group Interrupt Pin Initialization
+ * @param	pGPIOGPINT	: Pointer to GPIOIR register block
+ * @param	PortComb	: GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
+ * @param	PortTrigger	: GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
+{
+	IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger);
+}
+
+/**
+ * @brief	GPIO Group Interrupt Pin Add to Group
+ * @param	pGPIOGPINT	: Pointer to GPIOIR register block
+ * @param	PortNum		: GPIO port number, should be 0 to 7
+ * @param	PinNum		: GPIO pin number, should be 0 to 31
+ * @param	ActiveMode	: GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT,
+								  uint8_t PortNum,
+								  uint8_t PinNum,
+								  bool ActiveMode)
+{
+	IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode);
+}
+
+/**
+ * @brief	GPIO Group Interrupt Pin Remove from Group
+ * @param	pGPIOGPINT	: Pointer to GPIOIR register block
+ * @param	PortNum		: GPIO port number, should be 0 to 7
+ * @param	PinNum		: GPIO pin number, should be 0 to 31
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
+{
+	IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum);
+}
+
+/**
+ * @brief	Get GPIO Group Interrupt Get Status
+ * @param	pGPIOGPINT	: Pointer to GPIOIR register block
+ * @return	true if interrupt is pending, otherwise false
+ */
+STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
+{
+	return IP_GPIOGP_IntGetStatus(pGPIOGPINT);
+}
+
+/**
+ * @brief	Clear GPIO Group Interrupt
+ * @param	pGPIOGPINT	: Pointer to GPIOIR register block
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
+{
+	IP_GPIOGP_IntClear(pGPIOGPINT);
+}
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	portNum		: Port Number
+ * @param	bitValue	: GPIO bit to set
+ * @param	out			: Direction value, 0 = input, !0 = output
+ * @return	None
+ * Bits set to '0' are not altered.
+ */
+void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out);
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	portNum		: Port Number
+ * @param	bitValue	: GPIO bit to set
+ * @param	out			: Direction value, 0 = input, !0 = output
+ * @return	None
+ * Bits set to '0' are not altered.
+ */
+STATIC INLINE void Chip_FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	/* Same with Chip_GPIO_SetDir() */
+	Chip_GPIO_SetDir(portNum, bitValue, out);
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	portNum		: Port number
+ * @param	bitValue	: Bit(s) in the port to set high
+ * @return	None
+ * Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_FIO_SetValue(uint8_t portNum, uint32_t bitValue)
+{
+	/* Same with GPIO_SetValue() */
+	LPC_GPIO_PORT->SET[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	portNum		: Port number
+ * @param	bitValue	: Bit(s) in the port to set low
+ * @return	None
+ * Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
+{
+	/* Same with GPIO_ClearValue() */
+	LPC_GPIO_PORT->CLR[portNum] = bitValue;
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	portNum	: Port number to read
+ * @return	Current value of GPIO port
+ * The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output.
+ */
+STATIC INLINE uint32_t Chip_FIO_ReadValue(uint8_t portNum)
+{
+	/* Same with GPIO_ReadValue() */
+	return LPC_GPIO_PORT->PIN[portNum];
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	portNum		: Port number
+ * @param	bitValue	: Bit(s) in the port to set high
+ * @return	None
+ * Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
+{
+	LPC_GPIO_PORT->SET[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	portNum		: Port number
+ * @param	bitValue	: Bit(s) in the port to set low
+ * @return	None
+ * Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
+{
+	LPC_GPIO_PORT->CLR[portNum] = bitValue;
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	portNum	: Port number to read
+ * @return	Current value of GPIO port
+ * The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output.
+ */
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(uint8_t portNum)
+{
+	return LPC_GPIO_PORT->PIN[portNum];
+}
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c

@@ -0,0 +1,313 @@
+/*
+ * @brief LPC18xx/43xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "i2c_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define MAX_TX_BUFFER_SIZE 10	/* Maximum transmit buffer size in Chip_I2C_MasterWriteReg() function */
+
+static uint32_t i2cClockrate[2];
+static I2C_M_SETUP_Type TransferMCfg;
+static uint8_t p_regAddr;
+static uint8_t tx_buffer[MAX_TX_BUFFER_SIZE];
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Determine clock for uart BASED ON SELECTED uart */
+static CCU_CLK_T Chip_I2C_DetermineClk(LPC_I2C_Type *I2Cx) {
+
+	CCU_CLK_T i2cclk;
+
+	/* Pick clock for uart BASED ON SELECTED uart */
+	if (I2Cx == LPC_I2C0) {
+		i2cclk = CLK_APB1_I2C0;
+	}
+	else {
+		i2cclk = CLK_APB3_I2C1;
+	}
+
+	return i2cclk;
+}
+
+/* Get UART bus number BASED ON SELECTED uart */
+static I2C_ID_Type Chip_I2C_Get_BusNum(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C1) {
+		return I2C1;
+	}
+
+	return I2C0;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the LPC_I2C peripheral with specified parameter */
+void Chip_I2C_Init(LPC_I2C_Type *I2Cx)
+{
+	/* Enable I2C Clocking */
+	//	Chip_Clock_EnableOpts(Chip_I2C_DetermineClk(I2Cx), false, false, 1);
+	Chip_Clock_Enable(Chip_I2C_DetermineClk(I2Cx));
+
+	IP_I2C_Init(I2Cx);
+}
+
+/* De-initializes the I2C peripheral registers to their default reset values */
+void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx)
+{
+	IP_I2C_DeInit(I2Cx);
+
+	/* Disable UART clocking */
+	Chip_Clock_Disable(Chip_I2C_DetermineClk(I2Cx));
+}
+
+/* Set up clock rate for LPC_I2C peripheral */
+void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate)
+{
+	if (I2Cx == LPC_I2C0) {
+		i2cClockrate[0] = clockrate;
+		/* Select weather standard, fast, fast plus mode*/
+		if (clockrate >= 1000000) {	/* Fast mode plus: 1MHz, high speed 3.4MHz */
+			Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS);
+		}
+		else {					/* standard 100KHz, fast 400KHz */
+			Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
+		}
+	}
+	else if (I2Cx == LPC_I2C1) {
+		i2cClockrate[1] = clockrate;
+		/* Check if I2C1 run fast mode*/
+		if (clockrate > 400000) {
+			return;
+		}
+	}
+	else {return; }
+
+	/* Set clock rate */
+	if (clockrate < 1000) {	/* make sure SCLH,SCLL not exceed its 16bit value */
+		return;
+	}
+
+	IP_I2C_SetClockRate(I2Cx, (Chip_Clock_GetRate(Chip_I2C_DetermineClk(I2Cx)) / clockrate));
+}
+
+/* Get current clock rate for LPC_I2C peripheral */
+uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C0) {
+		return i2cClockrate[0];
+	}
+	else if (I2Cx == LPC_I2C1) {
+		return i2cClockrate[1];
+	}
+	return 0;
+}
+
+/* Transmit and Receive data in master mode */
+Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->retransmissions_max = 3;
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_count = 0;
+	TransferCfg->retransmissions_count = 0;
+
+	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* Transmit an array of bytes in Master mode */
+Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->rx_data = NULL;
+	TransferCfg->rx_length = 0;
+	TransferCfg->retransmissions_max = 3;
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_count = 0;
+	TransferCfg->retransmissions_count = 0;
+
+	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* Receive an array of bytes in Master mode */
+Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->tx_data = NULL;
+	TransferCfg->tx_length = 0;
+	TransferCfg->retransmissions_max = 3;
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_count = 0;
+	TransferCfg->retransmissions_count = 0;
+
+	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* Transmit one byte and continue to send an array of bytes
+ * after a repeated start condition is generated in Master mode
+ */
+uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
+								 uint32_t SlaveAddr,
+								 uint8_t regAddr,
+								 uint8_t *buffer,
+								 uint8_t buffer_len)
+{
+	uint8_t i = 0;
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	tx_buffer[0] = regAddr;
+
+	for (i = 0; i < buffer_len; i++)
+		tx_buffer[i + 1] = *(buffer + i);
+
+	TransferMCfg.sl_addr7bit = SlaveAddr;
+	TransferMCfg.tx_data = tx_buffer;
+	TransferMCfg.tx_length = buffer_len + 1;
+	TransferMCfg.rx_data = NULL;
+	TransferMCfg.rx_length = 0;
+	TransferMCfg.retransmissions_max = 3;
+	TransferMCfg.tx_count = 0;
+	TransferMCfg.rx_count = 0;
+	TransferMCfg.retransmissions_count = 0;
+	IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
+
+	return TransferMCfg.tx_count;
+}
+
+/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
+ * This function is useful for communicating with the I2C slave registers
+ */
+uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
+								uint32_t SlaveAddr,
+								uint8_t regAddr,
+								uint8_t *buffer,
+								uint8_t buffer_len)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	p_regAddr = regAddr;
+
+	TransferMCfg.sl_addr7bit = SlaveAddr;
+	TransferMCfg.tx_data = &p_regAddr;
+	TransferMCfg.tx_length = 1;
+	TransferMCfg.rx_data = buffer;
+	TransferMCfg.rx_length = buffer_len;
+	TransferMCfg.retransmissions_max = 3;
+	TransferMCfg.tx_count = 0;
+	TransferMCfg.rx_count = 0;
+	TransferMCfg.retransmissions_count = 0;
+	IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
+
+	return TransferMCfg.rx_count;
+}
+
+/* General Master Interrupt handler for I2C peripheral */
+void Chip_I2C_Interrupt_MasterHandler(LPC_I2C_Type *I2Cx)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	IP_I2C_Interrupt_MasterHandler(I2Cx, I2C_Num);
+}
+
+/* Get status of Master Transfer */
+bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	return IP_I2C_Interrupt_MasterTransferComplete(I2C_Num);
+}
+
+/* Receive and Transmit data in slave mode */
+Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_count = 0;
+
+	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* Transmit an array of bytes in Slave mode */
+Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_data = NULL;
+	TransferCfg->rx_length = 0;
+	TransferCfg->rx_count = 0;
+
+	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* Receive an array of bytes in Slave mode */
+Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	TransferCfg->tx_data = NULL;
+	TransferCfg->tx_length = 0;
+	TransferCfg->tx_count = 0;
+	TransferCfg->rx_count = 0;
+
+	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
+}
+
+/* General Slave Interrupt handler for I2C peripheral */
+void Chip_I2C_Interrupt_SlaveHandler(LPC_I2C_Type *I2Cx)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	IP_I2C_Interrupt_SlaveHandler(I2Cx, I2C_Num);
+}
+
+/* Get status of Slave Transfer */
+bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx)
+{
+	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
+
+	return IP_I2C_Interrupt_SlaveTransferComplete(I2C_Num);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h

@@ -0,0 +1,229 @@
+/*
+ * @brief LPC18xx/43xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef I2C_18XX_43XX_H_
+#define I2C_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initializes the LPC_I2C peripheral with specified parameter.
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Nothing
+ */
+void Chip_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	De-initializes the I2C peripheral registers to their default reset values
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Nothing
+ */
+void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Set up clock rate for LPC_I2C peripheral.
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	clockrate	: Target clock rate value to initialized I2C peripheral (Hz)
+ * @return	Nothing
+ */
+void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate);
+
+/**
+ * @brief	Get current clock rate for LPC_I2C peripheral.
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	the current I2Cx clock rate
+ */
+uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Transmit and Receive data in master mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
+ *                      information about the configuration for master transfer.
+ * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	Transmit an array of bytes in Master mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
+ *                      information about the	configuration for master transfer
+ * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
+ * @return  SUCCESS or ERROR
+ */
+Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	Receive an array of bytes in Master mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
+ *                      information about the configuration for master transfer.
+ * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	Write byte(s) to slave register
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	SlaveAddr	: Slave address in 7-bit mode
+ * @param	regAddr		: Slave register address
+ * @param	buffer		: pointer to data array needed to send
+ * @param	buffer_len	: data length (number of bytes)
+ * @return	Number of bytes sent
+ * Transmit one byte and an array of bytes after a repeated start condition is generated in Master mode.
+ * This function is useful for communicating with the I2C slave registers.
+ */
+uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
+								 uint32_t SlaveAddr,
+								 uint8_t regAddr,
+								 uint8_t *buffer,
+								 uint8_t buffer_len);
+
+/**
+ * @brief	Read slave register content
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	SlaveAddr	: Slave address in 7-bit mode
+ * @param	regAddr		: Slave register address
+ * @param	buffer		: pointer to data array needed to receive
+ * @param	buffer_len	: data length (number of bytes)
+ * @return	Number of bytes received
+ * Transmit one byte and continue to receive an array of bytes after a repeated start condition is
+ * generated in Master mode. This function is useful for communicating with the I2C slave registers.
+ */
+uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
+								uint32_t SlaveAddr,
+								uint8_t regAddr,
+								uint8_t *buffer,
+								uint8_t buffer_len);
+
+/**
+ * @brief	General Master Interrupt handler for I2C peripheral
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Nothing
+ */
+void Chip_I2C_Interrupt_MasterHandler (LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Get status of Master Transfer
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Master transfer status: TRUE (transfer completed) or FALSE (not completed yet)
+ */
+bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Receive and Transmit data in slave mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
+ *                      information about the configuration for master transfer.
+ * @param	Opt			: I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	Transmit an array of bytes in Slave mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
+ *                      information about the configuration for slave transfer.
+ * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	Receive an array of bytes in Slave mode
+ * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
+ *                      information about the configuration for slave transfer.
+ * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+
+/**
+ * @brief	General Slave Interrupt handler for I2C peripheral
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Nothing
+ */
+void Chip_I2C_Interrupt_SlaveHandler (LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Get status of Slave Transfer
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @return	Slave transfer status: TRUE (transfer completed) or FALSE (not completed yet)
+ */
+bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the
+ *                      configuration information for the specified I2C slave address.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2C_SetOwnSlaveAddr(LPC_I2C_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)
+{
+	IP_I2C_SetOwnSlaveAddr(I2Cx, OwnSlaveAddrConfigStruct);
+}
+
+/**
+ * @brief	Enable or disable I2C peripheral's operation
+ * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
+ * @param	Mode	: I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE
+ * @param	NewState: New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2C_Cmd(LPC_I2C_Type *I2Cx, I2C_Mode Mode, FunctionalState NewState)
+{
+	IP_I2C_Cmd(I2Cx, Mode, NewState);
+}
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c

@@ -0,0 +1,138 @@
+/*
+ * @brief LPC18xx/43xx I2S driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "i2s_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure I2S for Audio Format input */
+Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format)
+{
+	uint32_t pClk;
+	uint32_t x, y;
+	uint64_t divider;
+	uint16_t dif;
+	uint16_t x_divide = 0, y_divide = 0;
+	uint32_t N;
+	uint16_t err, ErrorOptimal = 0xFFFF;
+
+	pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S);
+
+	/* divider is a fixed point number with 16 fractional bits */
+	divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
+	/* find N that make x/y <= 1 -> divider <= 2^16 */
+	for (N = 64; N > 0; N--) {
+		if ((divider * N) < (1 << 16)) {
+			break;
+		}
+	}
+	if (N == 0) {
+		return ERROR;
+	}
+	divider *= N;
+	for (y = 255; y > 0; y--) {
+		x = y * divider;
+		if (x & (0xFF000000)) {
+			continue;
+		}
+		dif = x & 0xFFFF;
+		if (dif > 0x8000) {
+			err = 0x10000 - dif;
+		}
+		else {
+			err = dif;
+		}
+		if (err == 0) {
+			y_divide = y;
+			break;
+		}
+		else if (err < ErrorOptimal) {
+			ErrorOptimal = err;
+			y_divide = y;
+		}
+	}
+	x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
+	if (x_divide >= 256) {
+		x_divide = 0xFF;
+	}
+	if (x_divide == 0) {
+		x_divide = 1;
+	}
+	if (audio_format->WordWidth <= 8) {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8);
+	}
+	else if (audio_format->WordWidth <= 16) {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16);
+	}
+	else {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32);
+	}
+	IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
+	IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE);
+	IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1);
+	IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
+	IP_I2S_SetBitRate(I2Sx, TRMode, N - 1);
+	IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide);
+	return SUCCESS;
+}
+
+/* Enable/Disable Interrupt with a specific FIFO depth */
+void Chip_I2S_Int_Cmd(LPC_I2S_Type *I2Sx, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth)
+{
+	IP_I2S_InterruptCmd(I2Sx, TRMode, NewState);
+	IP_I2S_SetFIFODepthIRQ(I2Sx, TRMode, FIFO_Depth);
+}
+
+/* Enable/Disable DMA with a specific FIFO depth */
+void    Chip_I2S_DMA_Cmd(LPC_I2S_Type *I2Sx,
+						uint8_t TRMode,
+						uint8_t DMANum,
+						FunctionalState NewState,
+						uint8_t FIFO_Depth)
+{
+	IP_I2S_SetFIFODepthDMA(I2Sx, TRMode, (IP_I2S_DMARequestNumber_Type) DMANum, FIFO_Depth);
+	IP_I2S_DMACmd(I2Sx, (IP_I2S_DMARequestNumber_Type) DMANum, TRMode, NewState);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h

@@ -0,0 +1,221 @@
+/*
+ * @brief LPC18xx/43xx I2S driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __I2S_18XX_43XX_H_
+#define __I2S_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1
+#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2
+
+/**
+ * @brief I2S Audio Format Structure
+ */
+typedef struct {
+	uint32_t SampleRate;	/*!< Sample Rate */
+	uint8_t ChannelNumber;	/*!< Channel Number - 1 is mono, 2 is stereo */
+	uint8_t WordWidth;		/*!< Word Width - 8, 16 or 32 bits */
+} Chip_I2S_Audio_Format_Type;
+
+/**
+ * @brief	Initialize for I2S
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_Init(LPC_I2S_Type *pI2S)
+{
+	IP_I2S_Init(pI2S);
+}
+
+/**
+ * @brief	Shutdown I2S
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
+ */
+STATIC INLINE void Chip_I2S_DeInit(LPC_I2S_Type *pI2S)
+{
+	IP_I2S_DeInit(pI2S);
+}
+
+/**
+ * @brief	Send a 32-bit data to TXFIFO for transmition
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	data	: Data to be transmited
+ * @return	Nothing
+ * The function writes to TXFIFO without checking any condition.
+ */
+STATIC INLINE void Chip_I2S_Send(LPC_I2S_Type *pI2S, uint32_t data)
+{
+	IP_I2S_Send(pI2S, data);
+}
+
+/**
+ * @brief	Get received data from RXFIFO
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Data received in RXFIFO
+ * The function reads from RXFIFO without checking any condition.
+ */
+STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_Type *pI2S)
+{
+	return IP_I2S_Receive(pI2S);
+}
+
+/**
+ * @brief	Start the I2S
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_Start(LPC_I2S_Type *pI2S, uint8_t TRMode)
+{
+	IP_I2S_Start(pI2S, TRMode);
+}
+
+/**
+ * @brief	Disables accesses on FIFOs, places the transmit channel in mute mode
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_Pause(LPC_I2S_Type *pI2S, uint8_t TRMode)
+{
+	IP_I2S_Pause(pI2S, TRMode);
+}
+
+/**
+ * @brief	Transmit channel sends only zeroes
+ * @param	pI2S		: The base of I2S peripheral on the chip
+ * @param	NewState	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @return	Nothing
+ * The data output from I2S transmit channel is always zeroes
+ */
+STATIC INLINE void Chip_I2S_Mute(LPC_I2S_Type *pI2S, FunctionalState NewState)
+{
+	IP_I2S_Mute(pI2S, NewState);
+}
+
+/**
+ * @brief	Stop I2S asynchronously
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @return	Nothing
+ * Pause, resets the transmit channel and FIFO asynchronously
+ */
+STATIC INLINE void Chip_I2S_Stop(LPC_I2S_Type *pI2S, uint8_t TRMode)
+{
+	IP_I2S_Stop(pI2S, TRMode);
+}
+
+/**
+ * @brief	Set the I2S operating modes
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @param	clksel	: Clock source selection for the receive bit clock divider
+ * @param	fpin	: Receive 4-pin mode selection
+ * @param	mcena	: Enable for the RX_MCLK output
+ * @return	Nothing
+ * In addition to master and slave modes, which are independently configurable for
+ * the transmitter and the receiver, several different clock sources are possible,
+ * including variations that share the clock and/or WS between the transmitter and
+ * receiver. It also allows using I2S with fewer pins, typically four.
+ */
+STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_Type *pI2S,
+										 uint8_t TRMode,
+										 uint32_t clksel,
+										 uint32_t fpin,
+										 uint32_t mcena)
+{
+	IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena);
+}
+
+/**
+ * @brief	Get the current level of the Transmit/Receive FIFO
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
+ * @return	Current level of the Transmit/Receive FIFO
+ */
+STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_Type *pI2S, uint8_t TRMode)
+{
+	return IP_I2S_GetLevel(pI2S, TRMode);
+}
+
+/**
+ * @brief   Configure I2S for Audio Format input
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	TRMode			: Mode Rx/Tx
+ * @param	audio_format	: Audio Format
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2S_Config(LPC_I2S_Type *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format);
+
+/**
+ * @brief   Enable/Disable Interrupt with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	TRMode			: Mode Rx/Tx
+ * @param	NewState		: ENABLE or DISABLE interrupt
+ * @param	FIFO_Depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_Int_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth);
+
+/**
+ * @brief   Enable/Disable DMA with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	TRMode			: Mode Rx/Tx
+ * @param	DMANum			: Should be
+ *								- IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1
+ *								- IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2
+ * @param	NewState		: ENABLE or DISABLE interrupt
+ * @param	FIFO_Depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_DMA_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2S_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c

@@ -0,0 +1,118 @@
+/*
+ * @brief LPC18xx/43xx LCD chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "lcd_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+static LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure Cursor */
+void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync)
+{
+	LCD_Cursor_Size = cursor_size;
+	IP_LCD_Cursor_Config(LPC_LCD, cursor_size, sync);
+}
+
+/* Write Cursor Image into Internal Cursor Image Buffer */
+void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image)
+{
+	int i, j;
+	uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
+
+	/* Check if Cursor Size was configured as 32x32 or 64x64*/
+	if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
+		i = cursor_num * 64;
+		j = i + 64;
+	}
+	else {
+		i = 0;
+		j = 256;
+	}
+	fifoptr = IP_LCD_Cursor_GetImageBufferAddress(LPC_LCD, 0);
+
+	/* Copy Cursor Image content to FIFO */
+	for (; i < j; i++) {
+
+		*fifoptr = *crsr_ptr;
+		crsr_ptr++;
+		fifoptr++;
+	}
+}
+
+/* Load LCD Palette */
+void Chip_LCD_LoadPalette(void *palette) {
+	LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;
+	uint8_t i, *pal_ptr;
+	/* This function supports loading of the color palette from
+	   the C file generated by the bmp2c utility. It expects the
+	   palette to be passed as an array of 32-bit BGR entries having
+	   the following format:
+	   2:0 - Not used
+	   7:3 - Blue
+	   10:8 - Not used
+	   15:11 - Green
+	   18:16 - Not used
+	   23:19 - Red
+	   31:24 - Not used
+	   arg = pointer to input palette table address */
+	ptr_pal_entry = &pal_entry;
+	pal_ptr = (uint8_t *) palette;
+
+	/* 256 entry in the palette table */
+	for (i = 0; i < 256 / 2; i++) {
+		pal_entry.Bl = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gl = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Rl = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+		/* do the most significant halfword of the palette */
+		pal_entry.Bu = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gu = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Ru = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+
+		IP_LCD_Color_LoadPalette(LPC_LCD, (uint32_t *) &ptr_pal_entry, i);
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h

@@ -0,0 +1,216 @@
+/*
+ * @brief LPC18xx/43xx LCD chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LCD_18XX_43XX_H_
+#define __LCD_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize the LCD controller
+ * @param	LCD_ConfigStruct	: Pointer to LCD configuration
+ * @return  LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
+ */
+STATIC INLINE void Chip_LCD_Init(LCD_Config_Type *LCD_ConfigStruct)
+{
+	IP_LCD_Init(LPC_LCD, LCD_ConfigStruct);
+}
+
+/**
+ * @brief	Power the LCD Panel (power pin)
+ * @param	OnOff	: true to power on, false to power off
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Power(FunctionalState OnOff)
+{
+	IP_LCD_Power(LPC_LCD, OnOff);
+}
+
+/**
+ * @brief	Enable/Disable the LCD Controller
+ * @param	EnDis	: true to enable, false to disable
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Enable(FunctionalState EnDis)
+{
+	IP_LCD_Enable(LPC_LCD, EnDis);
+}
+
+/**
+ * @brief	Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
+ *			Buffer for Dual Panel
+ * @param	buffer	: address of buffer
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_SetUPFrameBuffer(void *buffer)
+{
+	IP_LCD_SetUPFrameBuffer(LPC_LCD, buffer);
+}
+
+/**
+ * @brief	Set LCD Lower Panel Frame Buffer for Dual Panel
+ * @param	buffer	: address of buffer
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_SetLPFrameBuffer(void *buffer)
+{
+	IP_LCD_SetLPFrameBuffer(LPC_LCD, buffer);
+}
+
+/**
+ * @brief	Configure Cursor
+ * @param	cursor_size	: specify size of cursor
+ *                  - LCD_CURSOR_32x32	:cursor size is 32x32 pixels
+ *                  - LCD_CURSOR_64x64	:cursor size is 64x64 pixels
+ * @param	sync		: cursor sync mode
+ *                  - TRUE	:cursor sync to the frame sync pulse
+ *                  - FALSE	:cursor async mode
+ * @return	None
+ */
+void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync);
+
+/**
+ * @brief	Enable Cursor
+ * @param	cursor_num	: specify number of cursor is going to be written
+ *							this param must < 4
+ * @param	OnOff		: true to turn on LCD, false to turn off
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_Enable(uint8_t cursor_num, FunctionalState OnOff)
+{
+	IP_LCD_Cursor_Enable(LPC_LCD, cursor_num, OnOff);
+}
+
+/**
+ * @brief	Load Cursor Palette
+ * @param	palette_color	: cursor palette 0 value
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(uint32_t palette_color)
+{
+	IP_LCD_Cursor_LoadPalette0(LPC_LCD, palette_color);
+}
+
+/**
+ * @brief	Load Cursor Palette
+ * @param	palette_color	: cursor palette 1 value
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(uint32_t palette_color)
+{
+	IP_LCD_Cursor_LoadPalette1(LPC_LCD, palette_color);
+}
+
+/**
+ * @brief	Set Cursor Position
+ * @param	x	: horizontal position
+ * @param	y	: vertical position
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_SetPos(uint16_t x, uint16_t y)
+{
+	IP_LCD_Cursor_SetPos(LPC_LCD, x, y);
+}
+
+/**
+ * @brief	Set Cursor Clipping Position
+ * @param	x	: horizontal position, should be in range: 0..63
+ * @param	y	: vertical position, should be in range: 0..63
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_SetClip(uint16_t x, uint16_t y)
+{
+	IP_LCD_Cursor_SetClip(LPC_LCD, x, y);
+}
+
+/**
+ * @brief	Enable Controller Interrupt
+ * @param	ints	: OR'ed interrupt bits to enable
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_EnableInts(uint32_t ints)
+{
+	IP_LCD_EnableInts(LPC_LCD, ints);
+}
+
+/**
+ * @brief	Disable Controller Interrupt
+ * @param	ints	: OR'ed interrupt bits to disable
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_DisableInts(uint32_t ints)
+{
+	IP_LCD_DisableInts(LPC_LCD, ints);
+}
+
+/**
+ * @brief	Clear Controller Interrupt
+ * @param	ints	: OR'ed interrupt bits to clear
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_ClearInts(uint32_t ints)
+{
+	IP_LCD_ClearInts(LPC_LCD, ints);
+}
+
+/**
+ * @brief	Write Cursor Image into Internal Cursor Image Buffer
+ * @param	cursor_num	: Cursor index
+ * @param	Image		: Pointer to image data
+ * @return	None
+ */
+void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image);
+
+/**
+ * @brief	Load LCD Palette
+ * @param	palette	: Address of palette table to load
+ * @return	None
+ */
+void Chip_LCD_LoadPalette(void *palette);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __LCD_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c

@@ -0,0 +1,92 @@
+/*
+ * @brief LPC18xx/43xx Reset Generator Unit driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "rgu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Trigger a peripheral reset for the selected peripheral */
+void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *p;
+
+	/* To trigger reset- write RESET_CTRLx with a 1 bit */
+	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
+
+	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
+	p += ResetNumber / 32;
+
+	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
+	   after 1 clock cycle, so set the bit and return */
+	*p = (1 << (ResetNumber % 32));
+}
+
+/* Clears reset for the selected peripheral */
+void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *p;
+
+	/* To trigger reset- write RESET_CTRLx with a 1 bit */
+	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
+
+	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
+	p += ResetNumber / 32;
+
+	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
+	   after 1 clock cycle, so set the bit and return */
+	*p = 0;
+}
+
+/* Checks the reset status of a peripheral */
+bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *read;
+
+	read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);
+	read += ResetNumber / 32;
+
+	/* Reset not asserted if bit is set */
+	return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h

@@ -0,0 +1,151 @@
+/*
+ * @brief LPC18xx/43xx Reset Generator Unit driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RGU_18XX_43XX_H_
+#define __RGU_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief RGU reset enumerations
+ */
+typedef enum {
+	RGU_CORE_RST,
+	RGU_PERIPH_RST,
+	RGU_MASTER_RST,
+	RGU_WWDT_RST = 4,
+	RGU_CREG_RST,
+	RGU_BUS_RST = 8,
+	RGU_SCU_RST,
+	RGU_M3_RST = 13,
+	RGU_LCD_RST = 16,
+	RGU_USB0_RST,
+	RGU_USB1_RST,
+	RGU_DMA_RST,
+	RGU_SDIO_RST,
+	RGU_EMC_RST,
+	RGU_ETHERNET_RST,
+	RGU_FLASHA_RST = 25,
+	RGU_EEPROM_RST = 27,
+	RGU_GPIO_RST,
+	RGU_FLASHB_RST,
+	RGU_TIMER0_RST = 32,
+	RGU_TIMER1_RST,
+	RGU_TIMER2_RST,
+	RGU_TIMER3_RST,
+	RGU_RITIMER_RST,
+	RGU_SCT_RST,
+	RGU_MOTOCONPWM_RST,
+	RGU_QEI_RST,
+	RGU_ADC0_RST,
+	RGU_ADC1_RST,
+	RGU_DAC_RST,
+	RGU_UART0_RST = 44,
+	RGU_UART1_RST,
+	RGU_UART2_RST,
+	RGU_UART3_RST,
+	RGU_I2C0_RST,
+	RGU_I2C1_RST,
+	RGU_SSP0_RST,
+	RGU_SSP1_RST,
+	RGU_I2S_RST,
+	RGU_SPIFI_RST,
+	RGU_CAN1_RST,
+	RGU_CAN0_RST,
+#ifdef CHIP_LPC43XX
+	RGU_M0APP_RST,
+	RGU_SGPIO_RST,
+	RGU_SPI_RST,
+#endif
+	RGU_LAST_RST = 63,
+} RGU_RST_TYPE;
+
+/**
+ * @brief RGU register structure
+ */
+typedef struct {							/*!< RGU Structure          */
+	__I  uint32_t  RESERVED0[64];
+	__O  uint32_t  RESET_CTRL0;				/*!< Reset control register 0 */
+	__O  uint32_t  RESET_CTRL1;				/*!< Reset control register 1 */
+	__I  uint32_t  RESERVED1[2];
+	__IO uint32_t  RESET_STATUS0;			/*!< Reset status register 0 */
+	__IO uint32_t  RESET_STATUS1;			/*!< Reset status register 1 */
+	__IO uint32_t  RESET_STATUS2;			/*!< Reset status register 2 */
+	__IO uint32_t  RESET_STATUS3;			/*!< Reset status register 3 */
+	__I  uint32_t  RESERVED2[12];
+	__I  uint32_t  RESET_ACTIVE_STATUS0;	/*!< Reset active status register 0 */
+	__I  uint32_t  RESET_ACTIVE_STATUS1;	/*!< Reset active status register 1 */
+	__I  uint32_t  RESERVED3[170];
+	__IO uint32_t  RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
+} LPC_RGU_T;
+
+/**
+ * @brief	Trigger a peripheral reset for the selected peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	Nothing
+ */
+void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @brief	Checks the reset status of a peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	true if the periperal is still being reset
+ */
+bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @brief	Clears reset for the selected peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	Nothing
+ * Almost all peripherals will auto clear the reset bit. Only a few peripherals
+ * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require
+ * this function to clear the reset bit.
+ */
+void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RGU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c

@@ -0,0 +1,67 @@
+/*
+ * @brief LPC18xx/43xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "ritimer_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set timer interval value */
+void Chip_RIT_SetTimerInterval(uint32_t time_interval)
+{
+	uint32_t clock_rate, cmp_value;
+
+	/* Get clock rate for RITimer */
+	clock_rate = Chip_Clock_GetRate(CLK_MX_RITIMER);
+
+	/* Determine aapproximate compare value based on clock rate and passed interval */
+	cmp_value = (clock_rate / 1000) * time_interval;
+
+	/* Set timer compare value */
+	Chip_RIT_SetCOMPVAL(cmp_value);
+	
+	/* Set timer enable clear bit to clear timer to 0 whenever
+	   counter value equals the contents of RICOMPVAL */
+	Chip_RIT_EnableCTRL(RIT_CTRL_ENCLR);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h

@@ -0,0 +1,146 @@
+/*
+ * @brief LPC18xx/43xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RITIMER_18XX_43XX_H_
+#define __RITIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize the RIT
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Init(void)
+{
+	IP_RIT_Init(LPC_RITIMER);
+}
+
+/**
+ * @brief	DeInitialize the RIT
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_DeInit(void)
+{
+	IP_RIT_DeInit(LPC_RITIMER);
+}
+
+/**
+ * @brief	Enable/Disable Timer
+ * @param	NewState	: ENABLE to enable timer, DISABLE to stop timer
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Cmd(FunctionalState NewState)
+{
+	IP_RIT_Enable(LPC_RITIMER, NewState);
+}
+
+/**
+ * @brief	Enable or disable timer debug
+ * @param	NewState	: ENABLE to halt timer whenever a hardware break condition occurs
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugCmd(FunctionalState NewState)
+{
+	IP_RIT_TimerDebugCmd(LPC_RITIMER, NewState);
+}
+
+/**
+ * @brief	Check whether interrupt flag is set or not
+ * @return	Current interrupt status, either ET or UNSET
+ */
+STATIC INLINE IntStatus Chip_RIT_GetIntStatus(void)
+{
+	return IP_RIT_GetIntStatus(LPC_RITIMER);
+}
+
+/**
+ * @brief	Set a tick value for the interrupt to time out
+ * @param	val	: value (in ticks) of the interrupt to be set
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_SetCOMPVAL(uint32_t val)
+{
+	IP_RIT_SetCOMPVAL(LPC_RITIMER, val);
+}
+
+/**
+ * @brief	Enables or clears the RIT or interrupt
+ * @param	val	: RIT to be set, one or more RIT_CTRL_* values
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_EnableCTRL(uint32_t val)
+{
+	IP_RIT_EnableCTRL(LPC_RITIMER, val);
+}
+
+/**
+ * @brief	Clears the RIT interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_ClearInt(void)
+{
+	IP_RIT_EnableCTRL(LPC_RITIMER, RIT_CTRL_INT);
+}
+
+/**
+ * @brief	Returns the current RIT Counter value
+ * @return	the current timer counter value
+ */
+STATIC INLINE uint32_t Chip_RIT_GetCounter(void)
+{
+	return IP_RIT_GetCounter(LPC_RITIMER);
+}
+
+/**
+ * @brief	Set timer interval value
+ * @param	time_interval	: timer interval value (ms)
+ * @return	None
+ */
+void Chip_RIT_SetTimerInterval(uint32_t time_interval);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RITIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c

@@ -0,0 +1,57 @@
+/*
+ * @brief LPC18xx/43xx RTC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "rtc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the RTC peripheral */
+void Chip_RTC_Init(void)
+{
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));	/* Reset 32Khz oscillator */
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);	/* Enable 32 kHz & 1 kHz on osc32k and release reset */
+	LPC_SCU->SFSCLK[0] = 1 | (0x3 << 2);/* function 1; CGU clk out, pull down */
+	IP_RTC_Init(LPC_RTC);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h

@@ -0,0 +1,281 @@
+/*
+ * @brief LPC18xx/43xx RTC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RTC_18XX_43XX_H_
+#define __RTC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize the RTC peripheral
+ * @return	None
+ */
+void Chip_RTC_Init(void);
+
+/**
+ * @brief	De-initialize the RTC peripheral
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_DeInit(void)
+{
+	IP_RTC_DeInit(LPC_RTC);
+}
+
+/**
+ * @brief	Reset clock tick counter in the RTC peripheral
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_ResetClockTickCounter(void)
+{
+	IP_RTC_ResetClockTickCounter(LPC_RTC);
+}
+
+/**
+ * @brief	Start/Stop RTC peripheral
+ * @param	NewState	: New State of this function, should be:
+ *							- ENABLE	:The time counters are enabled
+ *							- DISABLE	:The time counters are disabled
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_Enable(FunctionalState NewState)
+{
+	IP_RTC_Enable(LPC_RTC, NewState);
+}
+
+/**
+ * @brief	Enable/Disable Counter increment interrupt for a time type
+ *			in the RTC peripheral
+ * @param	cntrMask	: Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
+ * @param	NewState	: ENABLE or DISABLE
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_CntIncrIntConfig(uint32_t cntrMask, FunctionalState NewState)
+{
+	IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState);
+}
+
+/**
+ * @brief	Enable/Disable Alarm interrupt for a time type
+ *			in the RTC peripheral
+ * @param	alarmMask	: Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
+ * @param	NewState	: ENABLE or DISABLE
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_AlarmIntConfig(uint32_t alarmMask, FunctionalState NewState)
+{
+	IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState);
+}
+
+/**
+ * @brief		Set current time value for a time type in the RTC peripheral
+ * @param		Timetype	: time field index type to set
+ * @param		TimeValue	: Value to palce in time field
+ * @return		None
+ */
+STATIC INLINE void Chip_RTC_SetTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
+{
+	IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue);
+}
+
+/**
+ * @brief	Get current time value for a type time type
+ * @param	Timetype	: Time field index type to get
+ * @return	Value of time field according to specified time type
+ */
+STATIC INLINE uint32_t Chip_RTC_GetTime(IP_RTC_TIMEINDEX_T Timetype)
+{
+	return IP_RTC_GetTime(LPC_RTC, Timetype);
+}
+
+/**
+ * @brief	Set full time in the RTC peripheral
+ * @param	pFullTime	: Pointer to full time data
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_SetFullTime(IP_RTC_TIME_T *pFullTime)
+{
+	IP_RTC_SetFullTime(LPC_RTC, pFullTime);
+}
+
+/**
+ * @brief	Get full time from the RTC peripheral
+ * @param	pFullTime	: Pointer to full time record to fill
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_GetFullTime(IP_RTC_TIME_T *pFullTime)
+{
+	IP_RTC_GetFullTime(LPC_RTC, pFullTime);
+}
+
+/**
+ * @brief	Set alarm time value for a time type
+ * @param	Timetype	: Time index field to set
+ * @param	ALValue		: Alarm time value to set
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_SetAlarmTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
+{
+	IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue);
+}
+
+/**
+ * @brief	Get alarm time value for a time type
+ * @param	Timetype	: Time index field to get
+ * @return	Value of Alarm time according to specified time type
+ */
+STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(IP_RTC_TIMEINDEX_T Timetype)
+{
+	return IP_RTC_GetAlarmTime(LPC_RTC, Timetype);
+}
+
+/**
+ * @brief	Set full alarm time in the RTC peripheral
+ * @param	pFullTime	: Pointer to full time record to set alarm
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_SetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
+{
+	IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime);
+}
+
+/**
+ * @brief	Get full alarm time in the RTC peripheral
+ * @param	pFullTime	: Pointer to full time record to fill
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_GetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
+{
+	IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime);
+}
+
+/**
+ * @brief	Write value to General purpose registers
+ * @param	index	: General purpose register index
+ * @param	Value	: Value to write
+ * @return	None
+ * Note: These General purpose registers can be used to store important
+
+ * information when the main power supply is off. The value in these
+
+ * registers is not affected by chip reset. These registers are
+
+ * powered in the RTC power domain.
+ */
+STATIC INLINE void Chip_REGFILE_Write(uint8_t index, uint32_t Value)
+{
+	IP_REGFILE_Write(LPC_REGFILE, index, Value);
+}
+
+/**
+ * @brief	Read value from General purpose registers
+ * @param	index	: General purpose register index
+ * @return	Read Value
+ * These General purpose registers can be used to store important
+
+ * information when the main power supply is off. The value in these
+
+ * registers is not affected by chip reset. These registers are
+
+ * powered in the RTC power domain.
+ */
+STATIC INLINE uint32_t Chip_REGFILE_Read(uint8_t index)
+{
+	return IP_REGFILE_Read(LPC_REGFILE, index);
+}
+
+/**
+ * @brief	Enable/Disable calibration counter in the RTC peripheral
+ * @param	NewState	: New State of this function, should be:
+ *							- ENABLE	:The calibration counter is enabled and counting
+ *							- DISABLE	:The calibration counter is disabled and reset to zero
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_CalibCounterCmd(FunctionalState NewState)
+{
+	IP_RTC_CalibCounterCmd(LPC_RTC, NewState);
+}
+
+/**
+ * @brief	Configures Calibration in the RTC peripheral
+ * @param	CalibValue	: Calibration value, should be in range from 0 to 131,072
+ * @param	CalibDir	: Calibration Direction, should be:
+ *							- RTC_CALIB_DIR_FORWARD		:Forward calibration
+ *							- RTC_CALIB_DIR_BACKWARD	:Backward calibration
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_CalibConfig(uint32_t CalibValue, uint8_t CalibDir)
+{
+	IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir);
+}
+
+/**
+ * @brief	Clear specified Location interrupt pending in the RTC peripheral
+ * @param	IntType	: Interrupt location type, should be:
+ *						- RTC_INT_COUNTER_INCREASE	:Clear Counter Increment Interrupt pending.
+ *						- RTC_INT_ALARM				:Clear alarm interrupt pending
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_ClearIntPending(uint32_t IntType)
+{
+	IP_RTC_ClearIntPending(LPC_RTC, IntType);
+}
+
+/**
+ * @brief	Check whether if specified location interrupt in the
+ *              RTC peripheral is set or not
+ * @param	IntType	: Interrupt location type, should be:
+ *						- RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
+ *						- RTC_INT_ALARM: Alarm generated an interrupt.
+ * @return	New state of specified Location interrupt in RTC peripheral, SET OR RESET
+ */
+STATIC INLINE IntStatus Chip_RTC_GetIntPending(uint32_t IntType)
+{
+	return IP_RTC_GetIntPending(LPC_RTC, IntType);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RTC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c

@@ -0,0 +1,80 @@
+/*
+ * @brief LPC18xx/43xx System Control Unit (SCU) control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "scu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure pin function */
+void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
+{
+	if (port == PINMUX_CLK) {
+		LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func;
+	}
+	else {
+		LPC_SCU->SFSP[port][pin] = mode + func;
+	}
+}
+
+/* GPIO Interrupt Pin Select */
+void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum)
+{
+	uint8_t  pinInt;
+	volatile uint32_t pinSel;
+
+	pinInt = ((PortNum & 0x7) << 5) | (PinNum & 0x1F);
+	if (PortSel < 4) {
+		pinSel = LPC_SCU->PINTSEL0;
+		pinSel &= ~(0xFF << (PortSel * 8));
+		pinSel |= (pinInt << (PortSel * 8));
+		LPC_SCU->PINTSEL0 = pinSel;
+	}
+	else {
+		pinSel = LPC_SCU->PINTSEL1;
+		pinSel &= ~(0xFF << ((PortSel - 4) * 8));
+		pinSel |= (pinInt << ((PortSel - 4) * 8));
+		LPC_SCU->PINTSEL1 = pinSel;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SCU_18XX_43XX_H_
+#define __SCU_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief System Control Unit register block
+ */
+typedef struct {
+	__IO uint32_t  SFSP[16][32];
+	__I  uint32_t  RESERVED0[256];
+	__IO uint32_t  SFSCLK[4];			/*!< Pin configuration register for pins CLK0-3 */
+	__I  uint32_t  RESERVED16[28];
+	__IO uint32_t  SFSUSB;				/*!< Pin configuration register for USB */
+	__IO uint32_t  SFSI2C0;				/*!< Pin configuration register for I2C0-bus pins */
+	__IO uint32_t  ENAIO[3];			/*!< Analog function select registerS */
+	__I  uint32_t  RESERVED17[27];
+	__IO uint32_t  EMCDELAYCLK;			/*!< EMC clock delay register */
+	__I  uint32_t  RESERVED18[63];
+	__IO uint32_t  PINTSEL0;			/*!< Pin interrupt select register for pin interrupts 0 to 3. */
+	__IO uint32_t  PINTSEL1;			/*!< Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+/** Port offset definition */
+#define PORT_OFFSET     0x80
+
+/** Pin offset definition */
+#define PIN_OFFSET      0x04
+
+/** Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PUP  (0x0 << 3)
+
+/** Enable pull-down resistor at pad */
+#define MD_BUK  (0x1 << 3)
+
+/** Enable pull-up resistor at pad */
+#define MD_PLN  (0x2 << 3)
+
+/** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_PDN  (0x3 << 3)
+
+/** Enable fast slew rate */
+#define MD_EHS  (0x1 << 5)
+
+/** Input buffer enable */
+#define MD_EZI  (0x1 << 6)
+
+/** Disable input glitch filter */
+#define MD_ZI   (0x1 << 7)
+
+/** EHD driver strength low bit */
+#define MD_EHD0 (0x1 << 8)
+
+/** EHD driver strength high bit */
+#define MD_EHD1 (0x1 << 8)
+
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+
+/** Pin configuration for STANDARD/FAST mode I2C */
+#define I2C0_STANDARD_FAST_MODE  (1 << 3 | 1 << 11)
+
+/** Pin configuration for Fast-mode Plus I2C */
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
+
+#define FUNC0           0x0				/** Pin function 0 */
+#define FUNC1           0x1				/** Pin function 1 */
+#define FUNC2           0x2				/** Pin function 2 */
+#define FUNC3           0x3				/** Pin function 3 */
+#define FUNC4           0x4				/** Pin function 4 */
+#define FUNC5           0x5				/** Pin function 5 */
+#define FUNC6           0x6				/** Pin function 6 */
+#define FUNC7           0x7				/** Pin function 7 */
+
+/** Returns the SFSP register address in the SCU for a pin and port */
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
+
+/** Returns the address in the SCU for a SFSCLK clock register */
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
+
+#define PINMUX_CLK 0xFF
+
+/**
+ * @brief	Configure pin function
+ * @param	port	: Port number, should be: 0..15
+ * @param	pin		: Pin number, should be: 0..31
+ * @param	mode	: Pin mode, should be:
+ *                  - MD_PUP	:Pull-up enabled
+ *                  - MD_BUK	:Plain input
+ *                  - MD_PLN	:Repeater mode
+ *                  - MD_PDN	:Pull-down enabled
+ * @param	func	: Function mode, should be: FUNC0 to FUNC7
+ * @return	None
+ */
+void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
+
+/**
+ * @brief	GPIO Interrupt Pin Select
+ * @param	PortSel	: GPIO PINTSEL interrupt, should be: 0 to 7
+ * @param	PortNum	: GPIO port number interrupt, should be: 0 to 7
+ * @param	PinNum	: GPIO pin number Interrupt , should be: 0 to 31
+ * @return	None
+ */
+void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
+
+/**
+ * @brief	I2C Pin Configuration
+ * @param	I2C0Mode	: I2C0 mode, should be:
+ *                  - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit
+ *                  - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit
+ * @return	None
+ */
+STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
+{
+	LPC_SCU->SFSI2C0 = I2C0Mode;
+}
+
+/**
+ * @brief	ADC Pin Configuration
+ * @param	ADC_ID	: ADC number
+ * @param	channel	: ADC channel
+ * @return	None
+ */
+STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
+{
+	LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SCU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c

@@ -0,0 +1,597 @@
+/*
+ * @brief LPC18xx/43xx SD/SDIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "sdmmc_18xx_43xx.h"
+#include "string.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Global instance of the current card */
+static mci_card_struct *g_card_info;
+
+/* Helper definition: all SD error conditions in the status word */
+#define SD_INT_ERROR (MCI_INT_RESP_ERR | MCI_INT_RCRC | MCI_INT_DCRC | \
+					  MCI_INT_RTO | MCI_INT_DTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE | \
+					  MCI_INT_SBE | MCI_INT_EBE)
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Function to execute a command */
+static int32_t sdmmc_execute_command(uint32_t cmd, uint32_t arg, uint32_t wait_status)
+{
+	int32_t step = (cmd & CMD_BIT_APP) ? 2 : 1;
+	int32_t status = 0;
+	uint32_t cmd_reg = 0;
+
+	if (!wait_status) {
+		wait_status = (cmd & CMD_MASK_RESP) ? MCI_INT_CMD_DONE : MCI_INT_DATA_OVER;
+	}
+
+	/* Clear the interrupts & FIFOs*/
+	if (cmd & CMD_BIT_DATA) {
+		IP_SDMMC_SetClearIntFifo(LPC_SDMMC);
+	}
+
+	/* also check error conditions */
+	wait_status |= MCI_INT_EBE | MCI_INT_SBE | MCI_INT_HLE | MCI_INT_RTO | MCI_INT_RCRC | MCI_INT_RESP_ERR;
+	if (wait_status & MCI_INT_DATA_OVER) {
+		wait_status |= MCI_INT_FRUN | MCI_INT_HTO | MCI_INT_DTO | MCI_INT_DCRC;
+	}
+
+	while (step) {
+		IP_SDMMC_SetClock(LPC_SDMMC, g_card_info->clk_rate, g_card_info->speed);
+
+		/* Clear the interrupts */
+		IP_SDMMC_SetRawIntStatus(LPC_SDMMC, 0xFFFFFFFF);
+
+		g_card_info->evsetup_cb(wait_status);
+
+		switch (step) {
+		case 1:	/* Execute command */
+			cmd_reg = ((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) |
+					  ((cmd & CMD_BIT_INIT)  ? MCI_CMD_INIT : 0) |
+					  ((cmd & CMD_BIT_DATA)  ? (MCI_CMD_DAT_EXP | MCI_CMD_PRV_DAT_WAIT) : 0) |
+					  (((cmd & CMD_MASK_RESP) == CMD_RESP_R2) ? MCI_CMD_RESP_LONG : 0) |
+					  ((cmd & CMD_MASK_RESP) ? MCI_CMD_RESP_EXP : 0) |
+					  ((cmd & CMD_BIT_WRITE)  ? MCI_CMD_DAT_WR : 0) |
+					  ((cmd & CMD_BIT_STREAM) ? MCI_CMD_STRM_MODE : 0) |
+					  ((cmd & CMD_BIT_BUSY) ? MCI_CMD_STOP : 0) |
+					  ((cmd & CMD_BIT_AUTO_STOP)  ? MCI_CMD_SEND_STOP : 0) |
+					  MCI_CMD_START;
+
+			/* wait for previos data finsh for select/deselect commands */
+			if (((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) == MMC_SELECT_CARD) {
+				cmd_reg |= MCI_CMD_PRV_DAT_WAIT;
+			}
+
+			/* wait for command to be accepted by CIU */
+			if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, arg) == 0) {
+				--step;
+			}
+			break;
+
+		case 0:
+			return 0;
+
+		case 2:	/* APP prefix */
+			cmd_reg = MMC_APP_CMD | MCI_CMD_RESP_EXP |
+					  ((cmd & CMD_BIT_INIT)  ? MCI_CMD_INIT : 0) |
+					  MCI_CMD_START;
+
+			if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, g_card_info->rca << 16) == 0) {
+				--step;
+			}
+			break;
+		}
+
+		/* wait for command response */
+		status = g_card_info->waitfunc_cb();
+
+		/* We return an error if there is a timeout, even if we've fetched  a response */
+		if (status & SD_INT_ERROR) {
+			return status;
+		}
+
+		if (status & MCI_INT_CMD_DONE) {
+			switch (cmd & CMD_MASK_RESP) {
+			case 0:
+				break;
+
+			case CMD_RESP_R1:
+			case CMD_RESP_R3:
+			case CMD_RESP_R2:
+				IP_SDMMC_GetResponse(LPC_SDMMC, &g_card_info->response[0]);
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/* Checks whether card is acquired properly or not */
+static int32_t prv_card_acquired(void)
+{
+	return g_card_info->cid[0] != 0;
+}
+
+/* Helper function to get a bit field withing multi-word  buffer. Used to get
+   fields with-in CSD & EXT-CSD */
+static uint32_t prv_get_bits(int32_t start, int32_t end, uint32_t *data)
+{
+	uint32_t v;
+	uint32_t i = end >> 5;
+	uint32_t j = start & 0x1f;
+
+	if (i == (start >> 5)) {
+		v = (data[i] >> j);
+	}
+	else {
+		v = ((data[i] << (32 - j)) | (data[start >> 5] >> j));
+	}
+
+	return v & ((1 << (end - start + 1)) - 1);
+}
+
+/* Function to process the CSD & EXT-CSD of the card */
+static void prv_process_csd(void)
+{
+	int32_t status = 0;
+	int32_t c_size = 0;
+	int32_t c_size_mult = 0;
+	int32_t mult = 0;
+
+	/* compute block length based on CSD response */
+	g_card_info->block_len = 1 << prv_get_bits(80, 83, g_card_info->csd);
+
+	if ((g_card_info->card_type & CARD_TYPE_HC) && (g_card_info->card_type & CARD_TYPE_SD)) {
+		/* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec  an explanation for the calculation of these values */
+		c_size = prv_get_bits(48, 63, (uint32_t *) g_card_info->csd) + 1;
+		g_card_info->blocknr = c_size << 10;/* 512 byte blocks */
+	}
+	else {
+		/* See section 5.3 of the 4.1 revision of the MMC specs for  an explanation for the calculation of these values */
+		c_size = prv_get_bits(62, 73, (uint32_t *) g_card_info->csd);
+		c_size_mult = prv_get_bits(47, 49, (uint32_t *) g_card_info->csd);
+		mult = 1 << (c_size_mult + 2);
+		g_card_info->blocknr = (c_size + 1) * mult;
+
+		/* adjust blocknr to 512/block */
+		if (g_card_info->block_len > MMC_SECTOR_SIZE) {
+			g_card_info->blocknr = g_card_info->blocknr * (g_card_info->block_len >> 9);
+		}
+
+		/* get extended CSD for newer MMC cards CSD spec >= 4.0*/
+		if (((g_card_info->card_type & CARD_TYPE_SD) == 0) &&
+			(prv_get_bits(122, 125, (uint32_t *) g_card_info->csd) >= 4)) {
+			/* put card in trans state */
+			status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
+
+			/* set block size and byte count */
+			IP_SDMMC_SetBlockSize(LPC_SDMMC, MMC_SECTOR_SIZE);
+
+			/* send EXT_CSD command */
+			IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) g_card_info->ext_csd, MMC_SECTOR_SIZE);
+
+			status = sdmmc_execute_command(CMD_SEND_EXT_CSD, 0, 0 | MCI_INT_DATA_OVER);
+			if ((status & SD_INT_ERROR) == 0) {
+				/* check EXT_CSD_VER is greater than 1.1 */
+				if ((g_card_info->ext_csd[48] & 0xFF) > 1) {
+					g_card_info->blocknr = g_card_info->ext_csd[53];/* bytes 212:215 represent sec count */
+
+				}
+				/* switch to 52MHz clock if card type is set to 1 or else set to 26MHz */
+				if ((g_card_info->ext_csd[49] & 0xFF) == 1) {
+					/* for type 1 MMC cards high speed is 52MHz */
+					g_card_info->speed = MMC_HIGH_BUS_MAX_CLOCK;
+				}
+				else {
+					/* for type 0 MMC cards high speed is 26MHz */
+					g_card_info->speed = MMC_LOW_BUS_MAX_CLOCK;
+				}
+			}
+		}
+	}
+
+	g_card_info->device_size = g_card_info->blocknr << 9;	/* blocknr * 512 */
+}
+
+/* Puts current selected card in trans state */
+static int32_t prv_set_trans_state(void)
+{
+	uint32_t status;
+
+	/* get current state of the card */
+	status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
+	if (status & MCI_INT_RTO) {
+		/* unable to get the card state. So return immediatly. */
+		return -1;
+	}
+
+	/* check card state in response */
+	status = R1_CURRENT_STATE(g_card_info->response[0]);
+	switch (status) {
+	case SDMMC_STBY_ST:
+		/* put card in 'Trans' state */
+		status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
+		if (status != 0) {
+			/* unable to put the card in Trans state. So return immediatly. */
+			return -1;
+		}
+		break;
+
+	case SDMMC_TRAN_ST:
+		/*do nothing */
+		break;
+
+	default:
+		/* card shouldn't be in other states so return */
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Sets card data width and block size */
+static int32_t prv_set_card_params(void)
+{
+	int32_t status;
+
+#if SDIO_BUS_WIDTH > 1
+	if (g_card_info->card_type & CARD_TYPE_SD) {
+		status = sdmmc_execute_command(CMD_SD_SET_WIDTH, 2, 0);
+		if (status != 0) {
+			return -1;
+		}
+
+		/* if positive response */
+		IP_SDMMC_SetCardType(LPC_SDMMC, MCI_CTYPE_4BIT);
+		LPC_SDMMC->CTYPE = MCI_CTYPE_4BIT;
+	}
+#elif SDIO_BUS_WIDTH > 4
+#error 8-bit mode not supported yet!
+#endif
+
+	/* set block length */
+	IP_SDMMC_SetBlkSize(LPC_SDMMC, MMC_SECTOR_SIZE);
+	status = sdmmc_execute_command(CMD_SET_BLOCKLEN, MMC_SECTOR_SIZE, 0);
+	if (status != 0) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Returns the current SD status, clears pending ints, and disables all ints */
+uint32_t Chip_SDMMC_GetIntStatus(void)
+{
+	uint32_t status;
+
+	/* Get status and clear interrupts */
+	status = IP_SDMMC_GetRawIntStatus(LPC_SDMMC);
+	IP_SDMMC_SetRawIntStatus(LPC_SDMMC, status);
+	IP_SDMMC_SetIntMask(LPC_SDMMC, 0);
+
+	return status;
+}
+
+/* Get card's current state (idle, transfer, program, etc.) */
+int32_t Chip_SDMMC_GetState(void)
+{
+	uint32_t status;
+
+	/* get current state of the card */
+	status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
+	if (status & MCI_INT_RTO) {
+		return -1;
+	}
+
+	/* check card state in response */
+	return (int32_t) R1_CURRENT_STATE(g_card_info->response[0]);
+}
+
+/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
+uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo)
+{
+	int32_t status;
+	int32_t tries = 0;
+	uint32_t ocr = OCR_VOLTAGE_RANGE_MSK;
+	uint32_t r;
+	int32_t state = 0;
+	uint32_t command = 0;
+
+	g_card_info = pcardinfo;
+
+	/* clear card type */
+	IP_SDMMC_SetCardType(LPC_SDMMC, 0);
+
+	/* set high speed for the card as 20MHz */
+	g_card_info->speed = MMC_MAX_CLOCK;
+
+	status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
+
+	while (state < 100) {
+		switch (state) {
+		case 0:	/* Setup for SD */
+			/* check if it is SDHC card */
+			status = sdmmc_execute_command(CMD_SD_SEND_IF_COND, SD_SEND_IF_ARG, 0);
+			if (!(status & MCI_INT_RTO)) {
+				/* check response has same echo pattern */
+				if ((g_card_info->response[0] & SD_SEND_IF_ECHO_MSK) == SD_SEND_IF_RESP) {
+					ocr |= OCR_HC_CCS;
+				}
+			}
+
+			++state;
+			command = CMD_SD_OP_COND;
+			tries = INIT_OP_RETRIES;
+
+			/* assume SD card */
+			g_card_info->card_type |= CARD_TYPE_SD;
+			g_card_info->speed = SD_MAX_CLOCK;
+			break;
+
+		case 10:	/* Setup for MMC */
+			/* start fresh for MMC crds */
+			g_card_info->card_type &= ~CARD_TYPE_SD;
+			status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
+			command = CMD_MMC_OP_COND;
+			tries = INIT_OP_RETRIES;
+			ocr |= OCR_HC_CCS;
+			++state;
+
+			/* for MMC cards high speed is 20MHz */
+			g_card_info->speed = MMC_MAX_CLOCK;
+			break;
+
+		case 1:
+		case 11:
+			status = sdmmc_execute_command(command, 0, 0);
+			if (status & MCI_INT_RTO) {
+				state += 9;	/* Mode unavailable */
+			}
+			else {
+				++state;
+			}
+			break;
+
+		case 2:		/* Initial OCR check  */
+		case 12:
+			ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
+			if (ocr & OCR_ALL_READY) {
+				++state;
+			}
+			else {
+				state += 2;
+			}
+			break;
+
+		case 3:		/* Initial wait for OCR clear */
+		case 13:
+			while ((ocr & OCR_ALL_READY) && --tries > 0) {
+				g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
+				status = sdmmc_execute_command(command, 0, 0);
+				ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
+			}
+			if (ocr & OCR_ALL_READY) {
+				state += 7;
+			}
+			else {
+				++state;
+			}
+			break;
+
+		case 14:
+			/* for MMC cards set high capacity bit */
+			ocr |= OCR_HC_CCS;
+
+		case 4:	/* Assign OCR */
+			tries = SET_OP_RETRIES;
+			ocr &= OCR_VOLTAGE_RANGE_MSK | OCR_HC_CCS;	/* Mask for the bits we care about */
+			do {
+				g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
+				status = sdmmc_execute_command(command, ocr, 0);
+				r = g_card_info->response[0];
+			} while (!(r & OCR_ALL_READY) && --tries > 0);
+
+			if (r & OCR_ALL_READY) {
+				/* is it high capacity card */
+				g_card_info->card_type |= (r & OCR_HC_CCS);
+				++state;
+			}
+			else {
+				state += 6;
+			}
+			break;
+
+		case 5:	/* CID polling */
+		case 15:
+			status = sdmmc_execute_command(CMD_ALL_SEND_CID, 0, 0);
+			memcpy(&g_card_info->cid, &g_card_info->response[0], 16);
+			++state;
+			break;
+
+		case 6:	/* RCA send, for SD get RCA */
+			status = sdmmc_execute_command(CMD_SD_SEND_RCA, 0, 0);
+			g_card_info->rca = (g_card_info->response[0]) >> 16;
+			++state;
+			break;
+
+		case 16:	/* RCA assignment for MMC set to 1 */
+			g_card_info->rca = 1;
+			status = sdmmc_execute_command(CMD_MMC_SET_RCA, g_card_info->rca << 16, 0);
+			++state;
+			break;
+
+		case 7:
+		case 17:
+			status = sdmmc_execute_command(CMD_SEND_CSD, g_card_info->rca << 16, 0);
+			memcpy(&g_card_info->csd, &g_card_info->response[0], 16);
+			state = 100;
+			break;
+
+		default:
+			state += 100;	/* break from while loop */
+			break;
+		}
+	}
+
+	/* Compute card size, block size and no. of blocks  based on CSD response recived. */
+	if (prv_card_acquired()) {
+		prv_process_csd();
+
+		/* Setup card data width and block size (once) */
+		if (prv_set_trans_state() != 0) {
+			return 0;
+		}
+		if (prv_set_card_params() != 0) {
+			return 0;
+		}
+	}
+
+	return prv_card_acquired();
+}
+
+/* Get the device size of SD/MMC card (after enumeration) */
+int32_t Chip_SDMMC_GetDeviceSize(void)
+{
+	return g_card_info->device_size;
+}
+
+/* Performs the read of data from the SD/MMC card */
+int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
+{
+	int32_t cbRead = (num_blocks) * MMC_SECTOR_SIZE;
+	int32_t status = 0;
+	int32_t index;
+
+	/* if card is not acquired return immediately */
+	if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
+		return 0;
+	}
+
+	/* put card in trans state */
+	if (prv_set_trans_state() != 0) {
+		return 0;
+	}
+
+	/* set number of bytes to read */
+	LPC_SDMMC->BYTCNT = cbRead;
+
+	/* if high capacity card use block indexing */
+	if (g_card_info->card_type & CARD_TYPE_HC) {
+		index = start_block;
+	}
+	else {	/*fix at 512 bytes*/
+		index = start_block << 9;	// \* g_card_info->block_len;
+
+	}
+	IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbRead);
+
+	/* Select single or multiple read based on number of blocks */
+	if (num_blocks == 1) {
+		status = sdmmc_execute_command(CMD_READ_SINGLE, index, 0 | MCI_INT_DATA_OVER);
+	}
+	else {
+		status = sdmmc_execute_command(CMD_READ_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
+	}
+
+	if (status != 0) {
+		cbRead = 0;
+	}
+	/*Wait for card program to finish*/
+	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
+
+	return cbRead;
+}
+
+/* Performs write of data to the SD/MMC card */
+int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
+{
+	int32_t cbWrote = num_blocks *  MMC_SECTOR_SIZE;
+	int32_t status;
+	int32_t index;
+
+	/* if card is not acquired return immediately */
+	if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
+		return 0;
+	}
+
+	/*Wait for card program to finish*/
+	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
+
+	/* put card in trans state */
+	if (prv_set_trans_state() != 0) {
+		return 0;
+	}
+
+	/* set number of bytes to write */
+	LPC_SDMMC->BYTCNT = cbWrote;
+
+	/* if high capacity card use block indexing */
+	if (g_card_info->card_type & CARD_TYPE_HC) {
+		index = start_block;
+	}
+	else {	/*fix at 512 bytes*/
+		index = start_block << 9;	// * g_card_info->block_len;
+
+	}
+	IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbWrote);
+
+	/* Select single or multiple write based on number of blocks */
+	if (num_blocks == 1) {
+		status = sdmmc_execute_command(CMD_WRITE_SINGLE, index, 0 | MCI_INT_DATA_OVER);
+	}
+	else {
+		status = sdmmc_execute_command(CMD_WRITE_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
+	}
+
+	/*Wait for card program to finish*/
+	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
+
+	if (status != 0) {
+		cbWrote = 0;
+	}
+
+	return cbWrote;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h

@@ -0,0 +1,480 @@
+/*
+ * @brief LPC18xx/43xx SD/SDIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SDMMC_18XX_43XX_H_
+#define __SDMMC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/* SD/MMC commands - this matrix shows the command, response types, and
+   supported card type for that command.
+   Command                 Number Resp  SD  MMC
+   ----------------------- ------ ----- --- ---
+   Reset (go idle)         CMD0   NA    x   x
+   Send op condition       CMD1   R3        x
+   All send CID            CMD2   R2    x   x
+   Send relative address   CMD3   R1        x
+   Send relative address   CMD3   R6    x
+   Program DSR             CMD4   NA        x
+   Select/deselect card    CMD7   R1b       x
+   Select/deselect card    CMD7   R1    x
+   Send CSD                CMD9   R2    x   x
+   Send CID                CMD10  R2    x   x
+   Read data until stop    CMD11  R1    x   x
+   Stop transmission       CMD12  R1/b  x   x
+   Send status             CMD13  R1    x   x
+   Go inactive state       CMD15  NA    x   x
+   Set block length        CMD16  R1    x   x
+   Read single block       CMD17  R1    x   x
+   Read multiple blocks    CMD18  R1    x   x
+   Write data until stop   CMD20  R1        x
+   Setblock count          CMD23  R1        x
+   Write single block      CMD24  R1    x   x
+   Write multiple blocks   CMD25  R1    x   x
+   Program CID             CMD26  R1        x
+   Program CSD             CMD27  R1    x   x
+   Set write protection    CMD28  R1b   x   x
+   Clear write protection  CMD29  R1b   x   x
+   Send write protection   CMD30  R1    x   x
+   Erase block start       CMD32  R1    x
+   Erase block end         CMD33  R1    x
+   Erase block start       CMD35  R1        x
+   Erase block end         CMD36  R1        x
+   Erase blocks            CMD38  R1b       x
+   Fast IO                 CMD39  R4        x
+   Go IRQ state            CMD40  R5        x
+   Lock/unlock             CMD42  R1b       x
+   Application command     CMD55  R1        x
+   General command         CMD56  R1b       x
+
+ *** SD card application commands - these must be preceded with ***
+ *** MMC CMD55 application specific command first               ***
+   Set bus width           ACMD6  R1    x
+   Send SD status          ACMD13 R1    x
+   Send number WR blocks   ACMD22 R1    x
+   Set WR block erase cnt  ACMD23 R1    x
+   Send op condition       ACMD41 R3    x
+   Set clear card detect   ACMD42 R1    x
+   Send CSR                ACMD51 R1    x */
+
+/** @brief  SD/MMC command enumeration value.
+ */
+typedef enum {
+	SDMMC_IDLE,				/*!<  Put card in idle mode */
+	MMC_SENDOP_COND,		/*!<  Send operating condition */
+	SDMMC_ALL_SEND_CID,		/*!<  All cards send CID */
+	SDMMC_SRA,				/*!<  Set relative address */
+	MMC_PROGRAM_DSR,		/*!<  Program DSR */
+	SDMMC_SELECT_CARD,		/*!< Select card */
+	SDMMC_SEND_CSD,			/*!< Send CSD data */
+	SDMMC_SEND_CID,			/*!< Send CID register data (with rel. addr) */
+	SDMMC_READ_UNTIL_STOP,	/*!< Read data until stop */
+	SDMMC_STOP_XFER,		/*!< Stop current transmission */
+	SDMMC_SSTAT,			/*!< Send status */
+	SDMMC_INACTIVE,			/*!< Put card in inactive state */
+	SDMMC_SET_BLEN,			/*!< Set block transfer length */
+	SDMMC_READ_SINGLE,		/*!< Read single block */
+	SDMMC_READ_MULTIPLE,	/*!< Read multiple blocks */
+	SDMMC_WRITE_UNTIL_STOP,	/*!< Write data until stop */
+	SDMMC_SET_BLOCK_COUNT,	/*!< Set block count */
+	SDMMC_WRITE_SINGLE,		/*!< Write single block */
+	SDMMC_WRITE_MULTIPLE,	/*!< Write multiple blocks */
+	MMC_PROGRAM_CID,		/*!< Program CID */
+	SDMMC_PROGRAM_CSD,		/*!< Program CSD */
+	SDMMC_SET_WR_PROT,		/*!< Set write protection */
+	SDMMC_CLEAR_WR_PROT,	/*!< Clear write protection */
+	SDMMC_SEND_WR_PROT,		/*!< Send write protection */
+	SD_ERASE_BLOCK_START,	/*!< Set starting erase block */
+	SD_ERASE_BLOCK_END,		/*!< Set ending erase block */
+	MMC_ERASE_BLOCK_START,	/*!< Set starting erase block */
+	MMC_ERASE_BLOCK_END,	/*!< Set ending erase block */
+	MMC_ERASE_BLOCKS,		/*!< Erase blocks */
+	MMC_FAST_IO,			/*!< Fast IO */
+	MMC_GO_IRQ_STATE,		/*!< Go into IRQ state */
+	MMC_LOCK_UNLOCK,		/*!< Lock/unlock */
+	SDMMC_APP_CMD,			/*!< Application specific command */
+	SDMMC_GEN_CMD,			/*!< General purpose command */
+	SDMMC_INVALID_CMD		/*!< Invalid SDMMC command */
+} SDMMC_COMMAND_T;
+
+/** @brief  SDMMC application specific commands for SD cards only - these
+   must be preceded by the SDMMC CMD55 to work correctly.
+ */
+typedef enum {
+	SD_SET_BUS_WIDTH,		/*!< Set the SD bus width */
+	SD_SEND_STATUS,			/*!< Send the SD card status */
+	SD_SEND_WR_BLOCKS,		/*!< Send the number of written clocks */
+	SD_SET_ERASE_COUNT,		/*!< Set the number of blocks to pre-erase */
+	SD_SENDOP_COND,			/*!< Send the OCR register (init) */
+	SD_CLEAR_CARD_DET,		/*!< Set or clear the 50K detect pullup */
+	SD_SEND_SCR,			/*!< Send the SD configuration register */
+	SD_INVALID_APP_CMD		/*!< Invalid SD application command */
+} SD_APP_CMD_T;
+
+/** @brief  Possible SDMMC response types
+ */
+typedef enum {
+	SDMMC_RESPONSE_R1,		/*!< Typical status */
+	SDMMC_RESPONSE_R1B,		/*!< Typical status with busy */
+	SDMMC_RESPONSE_R2,		/*!< CID/CSD registers (CMD2 and CMD10) */
+	SDMMC_RESPONSE_R3,		/*!< OCR register (CMD1, ACMD41) */
+	SDMMC_RESPONSE_R4,		/*!< Fast IO response word */
+	SDMMC_RESPONSE_R5,		/*!< Go IRQ state response word */
+	SDMMC_RESPONSE_R6,		/*!< Published RCA response */
+	SDMMC_RESPONSE_NONE		/*!< No response expected */
+} SDMMC_RESPONSE_T;
+
+/** @brief  Possible SDMMC card state types
+ */
+typedef enum {
+	SDMMC_IDLE_ST = 0,	/*!< Idle state */
+	SDMMC_READY_ST,		/*!< Ready state */
+	SDMMC_IDENT_ST,		/*!< Identification State */
+	SDMMC_STBY_ST,		/*!< standby state */
+	SDMMC_TRAN_ST,		/*!< transfer state */
+	SDMMC_DATA_ST,		/*!< Sending-data State */
+	SDMMC_RCV_ST,		/*!< Receive-data State */
+	SDMMC_PRG_ST,		/*!< Programming State */
+	SDMMC_DIS_ST		/*!< Disconnect State */
+} SDMMC_STATE_T;
+
+/* Standard MMC commands (3.1)           type  argument     response */
+/* class 1 */
+#define MMC_GO_IDLE_STATE         0		/* bc                          */
+#define MMC_SEND_OP_COND          1		/* bcr  [31:0]  OCR        R3  */
+#define MMC_ALL_SEND_CID          2		/* bcr                     R2  */
+#define MMC_SET_RELATIVE_ADDR     3		/* ac   [31:16] RCA        R1  */
+#define MMC_SET_DSR               4		/* bc   [31:16] RCA            */
+#define MMC_SELECT_CARD           7		/* ac   [31:16] RCA        R1  */
+#define MMC_SEND_EXT_CSD          8		/* bc                      R1  */
+#define MMC_SEND_CSD              9		/* ac   [31:16] RCA        R2  */
+#define MMC_SEND_CID             10		/* ac   [31:16] RCA        R2  */
+#define MMC_STOP_TRANSMISSION    12		/* ac                      R1b */
+#define MMC_SEND_STATUS          13		/* ac   [31:16] RCA        R1  */
+#define MMC_GO_INACTIVE_STATE    15		/* ac   [31:16] RCA            */
+
+/* class 2 */
+#define MMC_SET_BLOCKLEN         16		/* ac   [31:0]  block len  R1  */
+#define MMC_READ_SINGLE_BLOCK    17		/* adtc [31:0]  data addr  R1  */
+#define MMC_READ_MULTIPLE_BLOCK  18		/* adtc [31:0]  data addr  R1  */
+
+/* class 3 */
+#define MMC_WRITE_DAT_UNTIL_STOP 20		/* adtc [31:0]  data addr  R1  */
+
+/* class 4 */
+#define MMC_SET_BLOCK_COUNT      23		/* adtc [31:0]  data addr  R1  */
+#define MMC_WRITE_BLOCK          24		/* adtc [31:0]  data addr  R1  */
+#define MMC_WRITE_MULTIPLE_BLOCK 25		/* adtc                    R1  */
+#define MMC_PROGRAM_CID          26		/* adtc                    R1  */
+#define MMC_PROGRAM_CSD          27		/* adtc                    R1  */
+
+/* class 6 */
+#define MMC_SET_WRITE_PROT       28		/* ac   [31:0]  data addr  R1b */
+#define MMC_CLR_WRITE_PROT       29		/* ac   [31:0]  data addr  R1b */
+#define MMC_SEND_WRITE_PROT      30		/* adtc [31:0]  wpdata addr R1  */
+
+/* class 5 */
+#define MMC_ERASE_GROUP_START    35		/* ac   [31:0]  data addr  R1  */
+#define MMC_ERASE_GROUP_END      36		/* ac   [31:0]  data addr  R1  */
+#define MMC_ERASE                37		/* ac                      R1b */
+
+/* class 9 */
+#define MMC_FAST_IO              39		/* ac   <Complex>          R4  */
+#define MMC_GO_IRQ_STATE         40		/* bcr                     R5  */
+
+/* class 7 */
+#define MMC_LOCK_UNLOCK          42		/* adtc                    R1b */
+
+/* class 8 */
+#define MMC_APP_CMD              55		/* ac   [31:16] RCA        R1  */
+#define MMC_GEN_CMD              56		/* adtc [0]     RD/WR      R1b */
+
+/* SD commands                           type  argument     response */
+/* class 8 */
+/* This is basically the same command as for MMC with some quirks. */
+#define SD_SEND_RELATIVE_ADDR     3		/* ac                      R6  */
+#define SD_CMD8                   8		/* bcr  [31:0]  OCR        R3  */
+
+/* Application commands */
+#define SD_APP_SET_BUS_WIDTH      6		/* ac   [1:0]   bus width  R1   */
+#define SD_APP_OP_COND           41		/* bcr  [31:0]  OCR        R1 (R4)  */
+#define SD_APP_SEND_SCR          51		/* adtc                    R1   */
+
+/*
+   MMC status in R1
+   Type
+    e : error bit
+    s : status bit
+    r : detected and set for the actual command response
+    x : detected and set during command execution. the host must poll
+        the card by sending status command in order to read these bits.
+   Clear condition
+    a : according to the card state
+    b : always related to the previous command. Reception of
+        a valid command will clear it (with a delay of one command)
+    c : clear by read
+ */
+
+#define R1_OUT_OF_RANGE         (1UL << 31)		/* er, c */
+#define R1_ADDRESS_ERROR        (1 << 30)	/* erx, c */
+#define R1_BLOCK_LEN_ERROR      (1 << 29)	/* er, c */
+#define R1_ERASE_SEQ_ERROR      (1 << 28)	/* er, c */
+#define R1_ERASE_PARAM          (1 << 27)	/* ex, c */
+#define R1_WP_VIOLATION         (1 << 26)	/* erx, c */
+#define R1_CARD_IS_LOCKED       (1 << 25)	/* sx, a */
+#define R1_LOCK_UNLOCK_FAILED   (1 << 24)	/* erx, c */
+#define R1_COM_CRC_ERROR        (1 << 23)	/* er, b */
+#define R1_ILLEGAL_COMMAND      (1 << 22)	/* er, b */
+#define R1_CARD_ECC_FAILED      (1 << 21)	/* ex, c */
+#define R1_CC_ERROR             (1 << 20)	/* erx, c */
+#define R1_ERROR                (1 << 19)	/* erx, c */
+#define R1_UNDERRUN             (1 << 18)	/* ex, c */
+#define R1_OVERRUN              (1 << 17)	/* ex, c */
+#define R1_CID_CSD_OVERWRITE    (1 << 16)	/* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP        (1 << 15)	/* sx, c */
+#define R1_CARD_ECC_DISABLED    (1 << 14)	/* sx, a */
+#define R1_ERASE_RESET          (1 << 13)	/* sr, c */
+#define R1_STATUS(x)            (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x)     ((x & 0x00001E00) >> 9)	/* sx, b (4 bits) */
+#define R1_READY_FOR_DATA       (1 << 8)/* sx, a */
+#define R1_APP_CMD              (1 << 5)/* sr, c */
+
+#define OCR_ALL_READY           (1UL << 31)		/* Card Power up status bit */
+#define OCR_HC_CCS              (1 << 30)	/* High capacity card */
+#define OCR_VOLTAGE_RANGE_MSK   0x00ff8000
+
+#define SD_SEND_IF_ARG          0x000001AA
+#define SD_SEND_IF_ECHO_MSK     0x000000FF
+#define SD_SEND_IF_RESP         0x000000AA
+
+#define CMD_MASK_RESP       (0x3UL << 28)
+#define CMD_RESP(r)         (((r) & 0x3) << 28)
+#define CMD_RESP_R0         (0 << 28)
+#define CMD_RESP_R1         (1 << 28)
+#define CMD_RESP_R2         (2 << 28)
+#define CMD_RESP_R3         (3 << 28)
+#define CMD_BIT_AUTO_STOP   (1 << 24)
+#define CMD_BIT_APP         (1 << 23)
+#define CMD_BIT_INIT        (1 << 22)
+#define CMD_BIT_BUSY        (1 << 21)
+#define CMD_BIT_LS          (1 << 20)	/* Low speed, used during acquire */
+#define CMD_BIT_DATA        (1 << 19)
+#define CMD_BIT_WRITE       (1 << 18)
+#define CMD_BIT_STREAM      (1 << 17)
+#define CMD_MASK_CMD        (0xff)
+#define CMD_SHIFT_CMD       (0)
+
+#define CMD(c, r)        ( ((c) &  CMD_MASK_CMD) | CMD_RESP((r)) )
+
+#define CMD_IDLE            CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS    | CMD_BIT_INIT
+#define CMD_SD_OP_COND      CMD(SD_APP_OP_COND, 1)      | CMD_BIT_LS | CMD_BIT_APP
+#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1)      | CMD_BIT_LS
+#define CMD_MMC_OP_COND     CMD(MMC_SEND_OP_COND, 3)    | CMD_BIT_LS | CMD_BIT_INIT
+#define CMD_ALL_SEND_CID    CMD(MMC_ALL_SEND_CID, 2)    | CMD_BIT_LS
+#define CMD_MMC_SET_RCA     CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS
+#define CMD_SD_SEND_RCA     CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS
+#define CMD_SEND_CSD        CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS
+#define CMD_SEND_EXT_CSD    CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA
+#define CMD_DESELECT_CARD   CMD(MMC_SELECT_CARD, 0)
+#define CMD_SELECT_CARD     CMD(MMC_SELECT_CARD, 1)
+#define CMD_SET_BLOCKLEN    CMD(MMC_SET_BLOCKLEN, 1)
+#define CMD_SEND_STATUS     CMD(MMC_SEND_STATUS, 1)
+#define CMD_READ_SINGLE     CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA
+#define CMD_READ_MULTIPLE   CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP
+#define CMD_SD_SET_WIDTH    CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP
+#define CMD_STOP            CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY
+#define CMD_WRITE_SINGLE    CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE
+#define CMD_WRITE_MULTIPLE  CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP
+
+/** @brief card type defines
+ */
+#define CARD_TYPE_SD    (1 << 0)
+#define CARD_TYPE_4BIT  (1 << 1)
+#define CARD_TYPE_8BIT  (1 << 2)
+#define CARD_TYPE_HC    (OCR_HC_CCS)/*!< high capacity card > 2GB */
+
+#define MMC_SECTOR_SIZE 512
+
+/** @brief Setup options for the SDIO driver
+ */
+#define US_TIMEOUT            1000000		/*!< give 1 atleast 1 sec for the card to respond */
+#define MS_ACQUIRE_DELAY      (10)			/*!< inter-command acquire oper condition delay in msec*/
+#define INIT_OP_RETRIES       50			/*!< initial OP_COND retries */
+#define SET_OP_RETRIES        1000			/*!< set OP_COND retries */
+#define SDIO_BUS_WIDTH        4				/*!< Max bus width supported */
+#define SD_MMC_ENUM_CLOCK       400000		/*!< Typical enumeration clock rate */
+#define MMC_MAX_CLOCK           20000000	/*!< Max MMC clock rate */
+#define MMC_LOW_BUS_MAX_CLOCK   26000000	/*!< Type 0 MMC card max clock rate */
+#define MMC_HIGH_BUS_MAX_CLOCK  52000000	/*!< Type 1 MMC card max clock rate */
+#define SD_MAX_CLOCK            25000000	/*!< Max SD clock rate */
+
+/* Function prototype for event setup function */
+typedef void (*MCI_EVSETUP_FUNC_T)(uint32_t);
+
+/* Function prototype for wait (for IRQ) function */
+typedef uint32_t (*MCI_WAIT_CB_FUNC_T)(void);
+
+/* Function prototype for milliSecond delay function */
+typedef void (*MCI_MSDELAY_FUNC_T)(uint32_t);
+
+/* Card specific setup data */
+typedef struct _mci_card_struct {
+	uint32_t response[4];						/*!< Most recent response */
+	uint32_t cid[4];							/*!< CID of acquired card  */
+	uint32_t csd[4];							/*!< CSD of acquired card */
+	uint32_t ext_csd[512 / 4];
+	uint32_t card_type;
+	uint32_t rca;								/*!< Relative address assigned to card */
+	uint32_t speed;
+	uint32_t block_len;							/*!< Card sector size*/
+	uint32_t device_size;
+	uint32_t blocknr;
+	uint32_t clk_rate;
+	sdif_device sdif_dev;
+	MCI_EVSETUP_FUNC_T evsetup_cb;
+	MCI_WAIT_CB_FUNC_T waitfunc_cb;
+	MCI_MSDELAY_FUNC_T msdelay_func;
+} mci_card_struct;
+
+/**
+ * @brief	Detect if an SD card is inserted
+ * @return	Returns 0 if a card is detected, otherwise 1
+ * Detect if an SD card is inserted
+ * (uses SD_CD pin, returns 0 on card detect)
+ */
+STATIC INLINE int32_t Chip_SDMMC_CardNDetect(void)
+{
+	return IP_SDMMC_CardNDetect(LPC_SDMMC);
+}
+
+/**
+ * @brief	Detect if write protect is enabled
+ * @return	Returns 1 if card is write protected, otherwise 0
+ * Detect if write protect is enabled
+ * (uses SD_WP pin, returns 1 if card is write protected)
+ */
+STATIC INLINE int32_t Chip_CardWpOn(void)
+{
+	return IP_SDMMC_CardWpOn(LPC_SDMMC);
+}
+
+/**
+ * @brief	Initializes the MCI card controller
+ * @return	None
+ */
+STATIC INLINE void Chip_SDMMC_Init(void)
+{
+	IP_SDMMC_Init(LPC_SDMMC);
+}
+
+/**
+ * @brief	Enable or disable slot power
+ * @param	enable	: !0 to enable, or 0 to disable
+ * @return	None
+ * Enable or disable slot power, !0 = enable slot power
+ * (Uses SD_POW pin, set to high or low based on enable parameter state)
+ */
+STATIC INLINE void Chip_SDMMC_PowerOnOff(int32_t enable)
+{
+	IP_SDMMC_PowerOnOff(LPC_SDMMC, enable);
+}
+
+/**
+ * @brief	Sets the SD interface interrupt mask
+ * @param	iVal	: Interrupts to enable, Or'ed values MCI_INT_*
+ * @return	None
+ */
+STATIC INLINE void Chip_SDMMC_SetIntMask(uint32_t iVal)
+{
+	IP_SDMMC_SetIntMask(LPC_SDMMC, iVal);
+}
+
+/**
+ * @brief	Returns the current SD status, clears pending ints, and disables all ints
+ * @return	Current pending interrupt status of Or'ed values MCI_INT_*
+ */
+uint32_t Chip_SDMMC_GetIntStatus(void);
+
+/**
+ * @brief	Get card's current state (idle, transfer, program, etc.)
+ * @return	Current SD card transfer state
+ */
+int32_t Chip_SDMMC_GetState(void);
+
+/**
+ * @brief	Function to enumerate the SD/MMC/SDHC/MMC+ cards
+ * @param	pcardinfo	: Pointer to pre-allocated card info structure
+ * @return	1 if a card is acquired, otherwise 0
+ */
+uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo);
+
+/**
+ * @brief	Get the device size of SD/MMC card (after enumeration)
+ * @return	Card size (capacity)
+ */
+int32_t Chip_SDMMC_GetDeviceSize(void);
+
+/**
+ * @brief	Performs the read of data from the SD/MMC card
+ * @param	buffer		: Pointer to data buffer to copy to
+ * @param	start_block	: Start block number
+ * @param	num_blocks	: Number of block to read
+ * @return	Bytes read, or 0 on error
+ */
+int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks);
+
+/**
+ * @brief	Performs write of data to the SD/MMC card
+ * @param	buffer		: Pointer to data buffer to copy to
+ * @param	start_block	: Start block number
+ * @param	num_blocks	: Number of block to write
+ * @return	Number of bytes actually written, or 0 on error
+ */
+int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDMMC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h

@@ -0,0 +1,356 @@
+/*
+ * @brief	SPIFI ROM driver functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SPIFI_ROM_API_H_
+#define __SPIFI_ROM_API_H_
+
+#include "chip.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* define the symbol TESTING in the environment	if test output desired */
+
+/** @ingroup IP_SPIFI_001
+ * @{
+ */
+
+/* maintain LONGEST_PROT >= the length (in bytes) of the largest
+    protection block of any serial flash that this driver handles */
+#define LONGEST_PROT 68
+
+typedef uint8_t uc;
+
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/** Protection/sector descriptors */
+typedef struct {
+	uint32_t base;
+	uc flags;
+	int8_t log2;
+	uint16_t rept;
+} protEnt;
+/* bits in the flags byte */
+enum {RWPROT = 1};
+
+#if 0
+
+/* overall data structure includes # sectors, length of protection reg,
+   array of descriptors */
+typedef struct {
+	uint16_t sectors;
+	uint16_t protBytes;
+	protEnt *entries;
+} protDesc;
+#endif
+
+typedef union {
+	uint16_t hw;
+	uc byte[2];
+} stat_t;
+/** The object that spifi_init returns, and other routines use as an operand */
+typedef struct {
+	uint32_t base, regbase, devSize, memSize;
+	uc mfger, devType, devID, busy;
+	stat_t stat;
+	uint16_t reserved;
+	uint16_t set_prot, write_prot;
+	uint32_t mem_cmd, prog_cmd;
+	uint16_t sectors, protBytes;
+	uint32_t opts, errCheck;
+	uc erase_shifts[4], erase_ops[4];
+	protEnt *protEnts;
+	char prot[LONGEST_PROT];
+} SPIFIobj;
+
+/** operands of program and erase */
+typedef struct {
+	char *dest;
+	uint32_t length;
+	char *scratch;
+	int32_t protect;
+	uint32_t options;
+} SPIFIopers;
+
+/** instruction classes for wait_busy */
+typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
+
+/** @defgroup IP_SPIFI_OPTIONS IP: SPIFI configuration options
+ * @ingroup IP_SPIFI_001
+ * Options used to configure SPIFI
+ * @{
+ */
+
+/** The SCL output is high when a frame/command is not in progress.
+    Note that S_MODE3+S_FULLCLK+S_RCVCLK will not work. Use S_MODE0
+    or S_INTCLK. */
+#define S_MODE3 1
+
+/** SCL is low when a frame/command is not in progress. (default) */
+#define S_MODE0 0
+
+/** SPI mode and the slowest, most basic/compatible read operation will be used. */
+#define S_MINIMAL 2
+
+/** The fastest read operation provided by the device will be used. (default) */
+#define S_MAXIMAL 0
+
+/** Data is sampled using the SCL clock fed back from the pin. This allows
+    more time for the serial flash to present each bit or group of bits,
+    but when used with S_FULLCLK can endanger hold time for data from the
+    flash. */
+#define S_RCVCLK 0x80
+
+/** Data is sampled using the internal clock from which the SCL pin is driven. (default) */
+#define S_INTCLK 0
+
+/** Data from the serial flash is sampled on falling edges on the SCL
+    output, allowing a full clock period for the serial flash to present
+    each bit or group of bits. */
+#define S_FULLCLK 0x40
+
+/** Data from the serial flash is sampled on rising edges of the SCL
+    output, as in classic SPI applications. Suitable for slower clock rates. (default) */
+#define S_HALFCLK 0
+
+/** If the connected device can operate in dual mode (2 bits per clock),
+    dual mode will be used, else SPI mode. */
+#define S_DUAL 0x100
+
+/**
+ * @}
+ */
+
+/** @defgroup IP_SPIFI_OPTIONS_PROGRAM IP: SPIFI programming options
+ * @ingroup IP_SPIFI_001
+ * Options used to configure SPIFI programming
+ * @{
+ */
+
+/** All sectors in dest to dest+length will be erased */
+#define S_FORCE_ERASE 4
+
+/** Erasing is handled by the caller not by the driver */
+#define S_ERASE_NOT_REQD 8
+
+/** Erasing is handled by the caller not by the driver */
+#define S_CALLER_ERASE 8
+
+/** Erasing is done when necessary. (default) */
+#define S_ERASE_AS_REQD 0
+
+/** Data will be read back and checked after programming. */
+#define S_VERIFY_PROG 0x10
+
+/** Sectors will be read back and checked for 0xFF after erasing. */
+#define S_VERIFY_ERASE 0x20
+
+/** No reading or checking will be done. (default) */
+#define S_NO_VERIFY 0
+
+/** Write protection is handled by the caller not by the driver. */
+#define S_CALLER_PROT 0x200
+
+/** The driver removes protection before the operation, and sets it as specified thereafter. (default) */
+#define S_DRIVER_PROT 0
+
+/**
+ * @}
+ */
+
+/* the following values in the first post-address memory command byte work
+   for all known quad devices that support "no opcode" operation */
+#define NO_OPCODE_FOLLOWS 0xA5
+#define    OPCODE_FOLLOWS 0xFF
+
+/* basic SPI commands for serial flash */
+#define BASE_READ_CMD        (CMD_RD << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | UNL_DATA)
+#define FAST_READ_CMD (CMD_READ_FAST << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | 1 << INTLEN_SHIFT | UNL_DATA)
+#define BASE_PROG_CMD      (CMD_PROG << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | DOUT)
+
+/* the length of a standard	program command is 256 on all devices */
+#define PROG_SIZE 256
+
+/* options in obj->opts (mostly for setMulti) */
+/* used by Winbond: send 0xA3 command so hardware can read faster */
+#define OPT_SEND_A3        1
+/* used by SST: send 0x38 command to enable quad and allow full command set */
+#define OPT_SEND_38        2
+/* used by Winbond and others: read status reg 2, check it,
+    if necessary write it back with Quad Enable set */
+#define OPT_35_OR02_01     4
+/* used by Atmel: read Configuration register, if necessary set Quad Enable */
+#define OPT_3F_OR80_3E     8
+/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
+#define OPT_65_CLR_C0_61   0x10
+/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
+   to set # dummy bytes and allow XIP mode */
+#define OPT_81          0x20
+/* set for devices without full device erase command (Numonyx type 0x40) */
+#define OPT_NO_DEV_ERASE 0x40
+/* used by Macronix: status reg 2 includes selection between write-protect
+    in status reg and command-based */
+#define OPT_WPSEL       0x80
+/* set when protection data has been read into the SPIFI object */
+#define OPT_PROT_READ  0x100
+/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
+#define OPT_4BAD       0x200
+/* set if setMulti should set the Dual bit in Control reg */
+#define OPT_DUAL       0x400
+/* send "# dummy bits" in C0 command to Winbond */
+#define OPT_C0         0x800
+/* set QE for Chingis */
+#define OPT_05_OR40_01 0x1000
+/* write status does not go busy */
+#define OPT_01_NO_BUSY 0x2000
+/* protection mode bits moved from protMode byte to opts  Fri May 13 2011 */
+#define OPT_PROT_STAT 0x4000
+#define OPT_PROT_REG  0x8000
+#define OPT_PROT_CMD3 0x10000
+#define OPT_PROT_CMDE 0x20000
+#define OPT_PROT_MASK 0x3C000
+
+#define OPT_ALL_QUAD  0x40000
+
+#ifndef OMIT_ROM_TABLE
+/* interface to ROM API */
+typedef struct {
+	int32_t (*spifi_init)(SPIFIobj *obj, uint32_t csHigh, uint32_t options,
+						  uint32_t mhz);
+	int32_t (*spifi_program)(SPIFIobj *obj, char *source, SPIFIopers *opers);
+	int32_t (*spifi_erase)(SPIFIobj *obj, SPIFIopers *opers);
+	/* mode switching */
+	void (*cancel_mem_mode)(SPIFIobj *obj);
+	void (*set_mem_mode)(SPIFIobj *obj);
+
+	/* mid level functions */
+	int32_t (*checkAd)(SPIFIobj *obj, SPIFIopers *opers);
+	int32_t (*setProt)(SPIFIobj *obj, SPIFIopers *opers, char *change,
+					   char *saveProt);
+	int32_t (*check_block)(SPIFIobj *obj, char *source, SPIFIopers *opers,
+						   uint32_t check_program);
+	int32_t (*send_erase_cmd)(SPIFIobj *obj, uint8_t op, uint32_t addr);
+	uint32_t (*ck_erase)(SPIFIobj *obj, uint32_t *addr, uint32_t length);
+	int32_t (*prog_block)(SPIFIobj *obj, char *source, SPIFIopers *opers,
+						  uint32_t *left_in_page);
+	uint32_t (*ck_prog)(SPIFIobj *obj, char *source, char *dest, uint32_t length);
+
+	/* low level functions */
+	void (*setSize)(SPIFIobj *obj, int32_t value);
+	int32_t (*setDev)(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
+					  uint32_t prog_cmd);
+	uint32_t (*cmd)(uc op, uc addrLen, uc intLen, uint16_t len);
+	uint32_t (*readAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr);
+	void (*send04)(SPIFIobj *obj, uc op, uc len, uint32_t value);
+	void (*wren_sendAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
+	int32_t (*write_stat)(SPIFIobj *obj, uc len, uint16_t value);
+	int32_t (*wait_busy)(SPIFIobj *obj, uc prog_or_erase);
+} SPIFI_RTNS;
+
+#define SPIFI_ROM_PTR  0x10400118
+
+#define define_spifi_romPtr(name) const SPIFI_RTNS * name = *((SPIFI_RTNS * *) SPIFI_ROM_PTR)
+#endif /* OMIT_ROM_TABLE */
+
+#ifdef USE_SPIFI_LIB
+extern SPIFI_RTNS spifi_table;
+#endif  /* USE_SPIFI_LIB */
+
+/* example of using this interface:
+   #include "spifi_rom_api.h"
+   #define CSHIGH 4
+   #define SPIFI_MHZ 80
+   #define source_data_ad (char *)1234
+
+    int32_t rc;
+    SPIFIopers opers;
+
+    define_spifi_romPtr(spifi);
+    SPIFIobj *obj = malloc(sizeof(SPIFIobj));
+    if (!obj) { can't allocate memory }
+
+    rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
+    if (rc) { investigate init error rc }
+    printf ("the serial flash contains %d bytes\n", obj->devSize);
+
+    opers.dest = where_to_program;
+    opers.length = how_many_bytes;
+    opers.scratch = NULL;			// unprogrammed data is not saved/restored
+    opers.protect = -1;				// save & restore protection
+    opers.options = S_VERIFY_PROG;
+
+    rc = spifi->spifi_program (obj, source_data_ad, &opers);
+    if (rc) { investigate program error rc }
+ */
+
+/* these are for normal users, including boot code */
+int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
+
+int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
+
+int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
+
+/* these are used by the manufacturer-specific init functions */
+void setSize (SPIFIobj *obj, int32_t value);
+
+int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
+
+uint32_t read04(SPIFIobj *obj, uc op, uc len);
+
+int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
+
+void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
+
+/* needs to be defined for each platform */
+void pullMISO(int high);
+
+#ifdef TESTING
+/* used by testing code */
+unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
+
+/* predeclare a debug routine */
+void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
+
+#endif
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* __SPIFI_ROM_API_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c

@@ -0,0 +1,434 @@
+/*
+ * @brief LPC18xx/43xx SSP driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "ssp_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+/** SSP macro: write 2 bytes to FIFO buffer */
+#define SSP_Write2BFifo(pSSP, \
+						xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \
+																		   (*(uint16_t *) ((uint32_t) xf_setup->tx_data	\
+																						   + xf_setup->tx_cnt))); }	\
+	else {IP_SSP_SendFrame(pSSP, 0xFFFF); }	\
+	xf_setup->tx_cnt += 2;
+
+/** SSP macro: write 1 bytes to FIFO buffer */
+#define SSP_Write1BFifo(pSSP, \
+						xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \
+																		   (*(uint8_t *) ((uint32_t) xf_setup->tx_data \
+																						  + xf_setup->tx_cnt))); } \
+	else {IP_SSP_SendFrame(pSSP, 0xFF); } \
+	xf_setup->tx_cnt++;
+
+/** SSP macro: read 1 bytes from FIFO buffer */
+#define SSP_Read2BFifo(pSSP, xf_setup, \
+					   rDat)  while (IP_SSP_GetStatus(pSSP,	\
+													  SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \
+		rDat = IP_SSP_ReceiveFrame(pSSP); \
+		if (xf_setup->rx_data) { \
+			*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;	\
+		} \
+		xf_setup->rx_cnt += 2; \
+}
+
+/** SSP macro: read 2 bytes from FIFO buffer */
+#define SSP_Read1BFifo(pSSP, xf_setup, \
+					   rDat)  while (IP_SSP_GetStatus(pSSP,	\
+													  SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \
+		rDat = IP_SSP_ReceiveFrame(pSSP); \
+		if (xf_setup->rx_data) { \
+			*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; \
+		} \
+		xf_setup->rx_cnt++;	\
+}
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* SSP Polling Read/Write in blocking mode */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
+{
+	uint16_t rDat;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		IP_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write2BFifo(pSSP, xf_setup)
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read2BFifo(pSSP, xf_setup, rDat)
+		}
+
+		if (xf_setup->tx_data) {
+			return xf_setup->tx_cnt;
+		}
+		else if (xf_setup->rx_data) {
+			return xf_setup->rx_cnt;
+		}
+		return 0;
+	}
+	else {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write1BFifo(pSSP, xf_setup)
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup, rDat)
+		}
+
+		if (xf_setup->tx_data) {
+			return xf_setup->tx_cnt;
+		}
+		else if (xf_setup->rx_data) {
+			return xf_setup->rx_cnt;
+		}
+		return 0;
+	}
+}
+
+/* SSP Polling Write in blocking mode */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t tx_cnt = 0, rx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		IP_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *wdata16;
+
+		wdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				IP_SSP_SendFrame(pSSP, *wdata16);
+				wdata16++;
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
+				IP_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt += 2;
+			}
+		}
+
+		return tx_cnt;
+	}
+	else {
+		uint8_t *wdata8;
+
+		wdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				IP_SSP_SendFrame(pSSP, *wdata8);
+				wdata8++;
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				IP_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt++;
+			}
+		}
+
+		return tx_cnt;
+	}
+}
+
+/* SSP Polling Read in blocking mode */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t rx_cnt = 0, tx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		IP_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *rdata16;
+
+		rdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				IP_SSP_SendFrame(pSSP, 0xFFFF);	/* just send dummy data */
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata16 = IP_SSP_ReceiveFrame(pSSP);
+				rdata16++;
+				rx_cnt += 2;
+			}
+		}
+
+		return rx_cnt;
+	}
+	else {
+		uint8_t *rdata8;
+
+		rdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				IP_SSP_SendFrame(pSSP, 0xFF);	/* just send dummy data		 */
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata8 = IP_SSP_ReceiveFrame(pSSP);
+				rdata8++;
+				rx_cnt++;
+			}
+		}
+
+		return rx_cnt;
+	}
+}
+
+/* Clean all data in RX FIFO of SSP */
+void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP)
+{
+	if (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
+		while (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) ;
+	}
+
+	/* Clear all remaining frames in RX FIFO */
+	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		IP_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+}
+
+/* SSP Interrupt Read/Write with 8-bit frame width */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
+{
+	uint16_t rDat;
+
+	/* Check overrun error in RIS register */
+	if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read1BFifo(pSSP, xf_setup, rDat)
+
+		while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write1BFifo(pSSP, xf_setup)
+
+			/* Check overrun error in RIS register */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup, rDat)
+		}
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* SSP Interrupt Read/Write with 16-bit frame width */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
+{
+	uint16_t rDat;
+
+	/* Check overrun error in RIS register */
+	if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read2BFifo(pSSP, xf_setup, rDat)
+
+		while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write2BFifo(pSSP, xf_setup)
+
+			/* Check overrun error in RIS register */
+			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO			 */
+			SSP_Read2BFifo(pSSP, xf_setup, rDat)
+		}
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* Set the SSP operating modes, master or slave */
+void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master)
+{
+	if (master) {
+		IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	}
+	else {
+		IP_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
+	}
+}
+
+/* Set the clock frequency for SSP interface */
+void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate)
+{
+	uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
+
+	if (pSSP == LPC_SSP0) {
+		ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP0);
+	}
+	else {
+		ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP1);
+	}
+
+	cr0_div = 0;
+	cmp_clk = 0xFFFFFFFF;
+	prescale = 2;
+
+	while (cmp_clk > bit_rate) {
+		cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
+		if (cmp_clk > bit_rate) {
+			cr0_div++;
+			if (cr0_div > 0xFF) {
+				cr0_div = 0;
+				prescale += 2;
+			}
+		}
+	}
+
+	IP_SSP_Set_ClockRate(pSSP, cr0_div, prescale);
+}
+
+/* Set up the SSP frame format */
+void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format)
+{
+	IP_SSP_Set_Format(pSSP, format->bits, format->frameFormat, format->clockFormat);
+}
+
+/* Enable/Disable SSP interrupt */
+void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
+{
+	IP_SSP_Int_Enable(pSSP, SSP_TXIM, NewState);
+}
+
+/* Enable/Disable DMA */
+void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
+{
+	IP_SSP_DMA_Cmd(pSSP, SSP_DMA_RX, NewState);
+	IP_SSP_DMA_Cmd(pSSP, SSP_DMA_TX, NewState);
+}
+
+/* Initialize the SSP */
+void Chip_SSP_Init(LPC_SSP_Type *pSSP)
+{
+	IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	IP_SSP_Set_Format(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
+	Chip_SSP_Set_BitRate(pSSP, 100000);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h

@@ -0,0 +1,311 @@
+/*
+ * @brief LPC18xx/43xx SSP driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SSP_18XX_43XX_H_
+#define __SSP_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/*
+ * @brief SSP clock format
+ */
+typedef enum SSP_ClockFormat {
+	SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),		/**< CPHA = 0, CPOL = 0 */
+	SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),		/**< CPHA = 0, CPOL = 1 */
+	SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),		/**< CPHA = 1, CPOL = 0 */
+	SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),		/**< CPHA = 1, CPOL = 1 */
+	SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
+	SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
+	SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
+	SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
+} SSP_ClockFormat;
+
+/*
+ * @brief SSP frame format
+ */
+typedef enum SSP_FrameFormat {
+	SSP_FRAMEFORMAT_SPI = (0 << 4),			/**< Frame format: SPI */
+	SSP_FRAMEFORMAT_TI = (1u << 4),			/**< Frame format: TI SSI */
+	SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),	/**< Frame format: Microwire */
+} SSP_FrameFormat;
+
+/*
+ * @brief Number of bits per frame
+ */
+typedef enum SSP_Bits {
+	SSP_BITS_4 = (3u << 0),		/**< 4 bits/frame */
+	SSP_BITS_5 = (4u << 0),		/**< 5 bits/frame */
+	SSP_BITS_6 = (5u << 0),		/**< 6 bits/frame */
+	SSP_BITS_7 = (6u << 0),		/**< 7 bits/frame */
+	SSP_BITS_8 = (7u << 0),		/**< 8 bits/frame */
+	SSP_BITS_9 = (8u << 0),		/**< 9 bits/frame */
+	SSP_BITS_10 = (9u << 0),	/**< 10 bits/frame */
+	SSP_BITS_11 = (10u << 0),	/**< 11 bits/frame */
+	SSP_BITS_12 = (11u << 0),	/**< 12 bits/frame */
+	SSP_BITS_13 = (12u << 0),	/**< 13 bits/frame */
+	SSP_BITS_14 = (13u << 0),	/**< 14 bits/frame */
+	SSP_BITS_15 = (14u << 0),	/**< 15 bits/frame */
+	SSP_BITS_16 = (15u << 0),	/**< 16 bits/frame */
+} SSP_Bits;
+
+/*
+ * @brief SSP config format
+ */
+typedef struct SSP_ConfigFormat {
+	SSP_Bits bits;				/**< Format config: bits/frame */
+	SSP_ClockFormat clockFormat;/**< Format config: clock phase/polarity */
+	SSP_FrameFormat frameFormat;/**< Format config: SPI/TI/Microwire */
+} SSP_ConfigFormat;
+
+/*
+ * @brief SSP mode
+ */
+typedef enum SSP_Mode {
+	SSP_MODE_MASTER = (0 << 2),	/**< Master mode */
+	SSP_MODE_SLAVE = (1u << 2),	/**< Slave mode */
+} SSP_Mode;
+
+/*
+ * @brief SPI address
+ */
+typedef struct {
+	uint8_t port;
+	uint8_t pin;
+} SPI_Address_t;
+
+/*
+ * @brief SSP data setup structure
+ */
+typedef struct {
+	void      *tx_data;	/**< Pointer to transmit data */
+	uint32_t  tx_cnt;	/**< Transmit counter */
+	void      *rx_data;	/**< Pointer to transmit data */
+	uint32_t  rx_cnt;	/**< Receive counter */
+	uint32_t  length;	/**< Length of transfer data */
+} Chip_SSP_DATA_SETUP_Type;
+
+/** SSP configuration parameter defines */
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
+#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI             SSP_CR0_CPOL_LO
+#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
+
+/**
+ * @brief	Get the current status of SSP controller
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	Stat	: Type of status, should be :
+ *						- SSP_STAT_TFE
+ *						- SSP_STAT_TNF
+ *						- SSP_STAT_RNE
+ *						- SSP_STAT_RFF
+ *						- SSP_STAT_BSY
+ * @return	SSP controller status, SET or RESET
+ */
+STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_Type *pSSP, SSP_Status_Type Stat)
+{
+	return IP_SSP_GetStatus(pSSP, Stat);
+}
+
+/**
+ * @brief	Enable/Disable SSP operation
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SSP_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
+{
+	IP_SSP_Cmd(pSSP, NewState);
+}
+
+/**
+ * @brief	Disable SSP operation
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	Nothing
+ * The SSP controller is disabled
+ */
+STATIC INLINE void Chip_SSP_DeInit(LPC_SSP_Type *pSSP)
+{
+	IP_SSP_DeInit(pSSP);
+}
+
+/**
+ * @brief	Enable/Disable loopback mode
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ * Serial input is taken from the serial output (MOSI or MISO) rather
+ * than the serial input pin
+ */
+STATIC INLINE void Chip_SSP_LoopBackCmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
+{
+	IP_SSP_LoopBackCmd(pSSP, NewState);
+}
+
+/**
+ * @brief   Clean all data in RX FIFO of SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 8-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
+ * 							information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 16-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
+ * 							information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
+
+/**
+ * @brief   SSP Polling Read/Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
+ * 							information about transmit/receive data	configuration
+ * @return	Actual data length has been transferred
+ *
+ * This function can be used in both master and slave mode. It starts with writing phase and after that,
+ * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
+ * through xf_setup param.
+ */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
+
+/**
+ * @brief   SSP Polling Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: Buffer length
+ * @return	Actual data length has been transferred
+ *
+ * This function can be used in both master and slave mode. First, a writing operation will send
+ * the needed data. After that, a dummy reading operation is generated to clear data buffer
+ */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   Note here
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: The length of buffer
+ * @return	Actual data length has been transferred
+ *
+ * This function can be used in both master and slave mode. First, a dummy writing operation is generated
+ * to clear data buffer. After that, a reading operation will receive the needed data
+ */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   Initialize the SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Init(LPC_SSP_Type *pSSP);
+
+/**
+ * @brief   Set the SSP operating modes, master or slave
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	master			: 1 to set master, 0 to set slave
+ * @return	Nothing
+ */
+void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master);
+
+/**
+ * @brief   Set the clock frequency for SSP interface
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	bit_rate		: The SSP bit rate
+ * @return	Nothing
+ */
+void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate);
+
+/**
+ * @brief   Set up the SSP frame format
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	format			: Structure used to format frame
+ * @return	Nothing
+ */
+void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format);
+
+/**
+ * @brief   Enable/Disable SSP interrupt
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	NewState		: ENABLE or DISABLE interrupt
+ * @return	Nothing
+ */
+void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
+
+/**
+ * @brief   Enable/Disable DMA
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	NewState		: ENABLE or DISABLE DMA
+ * @return	Nothing
+ */
+void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SSP_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h

@@ -0,0 +1,371 @@
+/*
+ * @brief Timer/PWM control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __TIMER_18XX_43XX_H_
+#define __TIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx Timer driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Determine if a match interrupt is pending
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * Determine if the match interrupt for the passed timer and match
+ * counter is pending.
+ */
+STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	return IP_TIMER_MatchPending(TMRx, matchnum);
+}
+
+/**
+ * @brief	Determine if a capture interrupt is pending
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * Determine if the capture interrupt for the passed capture pin is
+ * pending.
+ */
+STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	return IP_TIMER_CapturePending(TMRx, capnum);
+}
+
+/**
+ * @brief	Clears a (pending) match interrupt
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to clear
+ * @return	Nothing
+ * Clears a pending timer match interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_ClearMatch(TMRx, matchnum);
+}
+
+/**
+ * @brief	Clears a (pending) capture interrupt
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to clear
+ * @return	Nothing
+ * Clears a pending timer capture interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_ClearCapture(TMRx, capnum);
+}
+
+/**
+ * @brief	Enables the timer (starts count)
+ * @param	TMRx	: Pointer to timer IP register address
+ * @return	Nothing
+ * Enables the timer to start counting.
+ */
+STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_Type *TMRx)
+{
+	IP_TIMER_Enable(TMRx);
+}
+
+/**
+ * @brief	Disables the timer (stops count)
+ * @param	TMRx	: Pointer to timer IP register address
+ * @return	Nothing
+ * Disables the timer to stop counting.
+ */
+STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_Type *TMRx)
+{
+	IP_TIMER_Disable(TMRx);
+}
+
+/**
+ * @brief	Returns the current timer count
+ * @param	TMRx	: Pointer to timer IP register address
+ * @return	Current timer terminal count value
+ * Returns the current timer terminal count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_Type *TMRx)
+{
+	return IP_TIMER_ReadCount(TMRx);
+}
+
+/**
+ * @brief	Returns the current prescale count
+ * @param	TMRx	: Pointer to timer IP register address
+ * @return	Current timer prescale count value
+ * Returns the current prescale count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_Type *TMRx)
+{
+	return IP_TIMER_ReadPrescale(TMRx);
+}
+
+/**
+ * @brief	Sets the prescaler value
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	prescale	: Prescale value to set the prescale register to
+ * @return	Nothing
+ * Sets the prescale count value.
+ */
+STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_Type *TMRx, uint32_t prescale)
+{
+	IP_TIMER_PrescaleSet(TMRx, prescale);
+}
+
+/**
+ * @brief	Sets a timer match value
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer to set match count for
+ * @param	matchval	: Match value for the selected match count
+ * @return	Nothing
+ * Sets ones of the timer match values.
+ */
+STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_Type *TMRx, int8_t matchnum, uint32_t matchval)
+{
+	IP_TIMER_SetMatch(TMRx, matchnum, matchval);
+}
+
+/**
+ * @brief	Reads a capture register
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture register to read
+ * @return	The selected capture register value
+ * Returns the selected capture register value.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	return IP_TIMER_ReadCapture(TMRx, capnum);
+}
+
+/**
+ * @brief	Resets the timer terminal and prescale counts to 0
+ * @param	TMRx	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_Reset(LPC_TIMER_Type *TMRx)
+{
+	IP_TIMER_Reset(TMRx);
+}
+
+/**
+ * @brief	Enables a match interrupt that fires when the terminal count
+ *			matches the match counter value.
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_MatchEnableInt(TMRx, matchnum);
+}
+
+/**
+ * @brief	Disables a match interrupt for a match counter.
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_MatchDisableInt(TMRx, matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, enables reset of the terminal count register when a match occurs
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_ResetOnMatchEnable(TMRx, matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, disables reset of the terminal count register when a match occurs
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_ResetOnMatchDisable(TMRx, matchnum);
+}
+
+/**
+ * @brief	Enable a match timer to stop the terminal count when a
+ *			match count equals the terminal count.
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_StopOnMatchEnable(TMRx, matchnum);
+}
+
+/**
+ * @brief	Disable stop on match for a match timer. Disables a match timer
+ *			to stop the terminal count when a match count equals the terminal count.
+ * @param	TMRx		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum)
+{
+	IP_TIMER_StopOnMatchDisable(TMRx, matchnum);
+}
+
+/**
+ * @brief	Enables capture on on rising edge of selected CAP signal for the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureRisingEdgeEnable(TMRx, capnum);
+}
+
+/**
+ * @brief	Disables capture on on rising edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureRisingEdgeDisable(TMRx, capnum);
+}
+
+/**
+ * @brief	Enables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureFallingEdgeEnable(TMRx, capnum);
+}
+
+/**
+ * @brief	Disables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureFallingEdgeDisable(TMRx, capnum);
+}
+
+/**
+ * @brief	Enables interrupt on capture of selected CAP signal. For the
+ *			selected capture register, an interrupt will be generated when the enabled
+ *			rising or falling edge on CAPn.capnum is detected.
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureEnableInt(TMRx, capnum);
+}
+
+/**
+ * @brief	Disables interrupt on capture of selected CAP signal
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_Type *TMRx, int8_t capnum)
+{
+	IP_TIMER_CaptureDisableInt(TMRx, capnum);
+}
+
+/**
+ * @brief	Sets external match control (MATn.matchnum) pin control
+ * @param	TMRx			: Pointer to timer IP register address
+ * @param	initial_state	: Initial state of the pin, high(1) or low(0)
+ * @param	matchState		: Selects the match state for the pin
+ * @param	matchnum		: MATn.matchnum signal to use
+ * @return	Nothing
+ * For the pin selected with matchnum, sets the function of the pin that occurs on
+ * a terminal count match for the match count.
+ */
+STATIC INLINE void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_Type *TMRx, int8_t initial_state,
+												 IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum)
+{
+	IP_TIMER_ExtMatchControlSet(TMRx, initial_state, matchState, matchnum);
+}
+
+/**
+ * @brief	Sets timer count source and edge with the selected passed from CapSrc
+ * @param	TMRx	: Pointer to timer IP register address
+ * @param	capSrc	: timer clock source and edge
+ * @param	capnum	: CAPn.capnum pin to use (if used)
+ * @return	Nothing
+ * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
+ */
+STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_Type *TMRx,
+													 IP_TIMER_CAP_SRC_STATE_Type capSrc,
+													 int8_t capnum)
+{
+	IP_TIMER_SetCountClockSrc(TMRx, capSrc, capnum);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c

@@ -0,0 +1,353 @@
+/*
+ * @brief LPC18xx/43xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "uart_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/** UART Ring buffer declaration*/
+static UART_RingBuffer_Type rb;
+
+/** Current Tx Interrupt enable state */
+static __IO FlagStatus TxIntStat;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Get UART number based on selected UART */
+static UART_ID_Type Chip_UART_Get_UARTNum(LPC_USART_Type *UARTx)
+{
+	if (UARTx == LPC_USART0) {
+		return UART_0;
+	}
+	else if (UARTx == LPC_UART1) {
+		return UART_1;
+	}
+	else if (UARTx == LPC_USART2) {
+		return UART_2;
+	}
+
+	return UART_3;
+}
+
+/* Determine UART clock based in selected UART */
+static CCU_CLK_T Chip_UART_DetermineClk(LPC_USART_Type *UARTx) {
+	CCU_CLK_T uartclk;
+
+	/* Pick clock for uart BASED ON SELECTED uart */
+	if (UARTx == LPC_UART1) {
+		uartclk = CLK_MX_UART1;
+	}
+	if (UARTx == LPC_USART2) {
+		uartclk = CLK_MX_UART2;
+	}
+	if (UARTx == LPC_USART3) {
+		uartclk = CLK_MX_UART3;
+	}
+	else {
+		uartclk = CLK_MX_UART0;
+	}
+
+	return uartclk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the UARTx peripheral */
+void Chip_UART_Init(LPC_USART_Type *UARTx)
+{
+	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
+
+	/* Enable UART clocking. UART base clock(s) must already be enabled */
+	Chip_Clock_EnableOpts(Chip_UART_DetermineClk(UARTx), true, true, 1);
+
+	IP_UART_Init(UARTx, UARTPort);
+}
+
+/* De-initializes the UARTx peripheral */
+void Chip_UART_DeInit(LPC_USART_Type *UARTx)
+{
+	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
+
+	IP_UART_DeInit(UARTx, UARTPort);
+
+	/* Disable UART clocking */
+	Chip_Clock_Disable(Chip_UART_DetermineClk(UARTx));
+}
+
+/* Determines best dividers to get a target baud rate */
+Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate)
+{
+	uint32_t uClk;
+
+	/* Get UART clock rate */
+	uClk = Chip_Clock_GetRate(Chip_UART_DetermineClk(UARTx));
+
+	return IP_UART_SetBaud(UARTx, baudrate, uClk);
+}
+
+/* Enable/Disable transmission on UART TxD pin */
+void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState)
+{
+	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
+
+	IP_UART_TxCmd(UARTx, UARTPort, NewState);
+}
+
+/* Get Interrupt Stream Status */
+UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx)
+{
+	uint32_t intsrc, tmp, tmp1;
+	UART_Int_Status ret = UART_ERROR;
+
+	/* Determine the interrupt source */
+	intsrc = Chip_UART_IntGetStatus(UARTx);
+
+	tmp = intsrc & UART_IIR_INTID_MASK;
+
+	/* Receive Line Status */
+	if (tmp == UART_IIR_INTID_RLS) {
+		/* Check line status */
+		tmp1 = (uint32_t) Chip_UART_GetLineStatus(UARTx);
+		/* Mask out the Receive Ready and Transmit Holding empty status */
+		tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
+				 | UART_LSR_BI | UART_LSR_RXFE);
+		/* If any error exist */
+		if (tmp1) {
+			return UART_ERROR;
+		}
+	}
+
+	/* Receive Data Available or Character time-out */
+	if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI)) {
+		ret |= READY_TO_RECEIVE;
+	}
+
+	/* Transmit Holding Empty */
+	if (tmp == UART_IIR_INTID_THRE) {
+		ret |= READY_TO_SEND;
+	}
+	return ret;
+}
+
+/* UART interrupt service routine */
+void Chip_UART_Interrupt_Handler(LPC_USART_Type *UARTx)
+{
+	uint8_t tmpc;
+	uint32_t rLen;
+	UART_Int_Status Sts = Chip_UART_GetIntStatus(UARTx);
+	if (Sts == UART_ERROR) {
+		return;	/* error */
+
+	}
+	if (Sts & READY_TO_RECEIVE) {	/* ready for Read Data */
+		while (1) {
+			/* Call UART read function in UART driver */
+			rLen = Chip_UART_Receive(UARTx, &tmpc, 1, NONE_BLOCKING);
+			/* If data received */
+			if (rLen) {
+				/* Check if buffer is more space
+				 * If no more space, remaining character will be trimmed out
+				 */
+				if (!__BUF_IS_FULL(rb.rx_head, rb.rx_tail)) {
+					rb.rx[rb.rx_head] = tmpc;
+					__BUF_INCR(rb.rx_head);
+				}
+			}
+			/* no more data */
+			else {
+				break;
+			}
+		}
+	}
+
+	if (Sts & READY_TO_SEND) {	/* ready for Write Data */
+		/* Disable THRE interrupt */
+		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
+
+		/* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes
+		 * of data or break whenever ring buffers are empty */
+		/* Wait until THR empty */
+		while (Chip_UART_CheckBusy(UARTx) == SET) ;
+
+		while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
+			/* Move a piece of data into the transmit FIFO */
+			if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) {
+				/* Update transmit ring FIFO tail pointer */
+				__BUF_INCR(rb.tx_tail);
+			}
+			else {
+				break;
+			}
+		}
+
+		/* If there is no more data to send, disable the transmit
+		   interrupt - else enable it or keep it enabled */
+		if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
+			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
+			// Reset Tx Interrupt state
+			TxIntStat = RESET;
+		}
+		else {
+			/* Set Tx Interrupt state */
+			TxIntStat = SET;
+			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
+		}
+	}
+}
+
+/* UART transmit function for interrupt mode (using ring buffers) */
+uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen)
+{
+	uint8_t *data = (uint8_t *) txbuf;
+	uint32_t bytes = 0;
+
+	/* Temporarily lock out UART transmit interrupts during this
+	   read so the UART transmit interrupt won't cause problems
+	   with the index values */
+	Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
+
+	/* Loop until transmit run buffer is full or until n_bytes
+	   expires */
+	while ((buflen > 0) && (!__BUF_IS_FULL(rb.tx_head, rb.tx_tail))) {
+		/* Write data from buffer into ring buffer */
+		rb.tx[rb.tx_head] = *data;
+		data++;
+
+		/* Increment head pointer */
+		__BUF_INCR(rb.tx_head);
+
+		/* Increment data count and decrement buffer size count */
+		bytes++;
+		buflen--;
+	}
+
+	/*
+	 * Check if current Tx interrupt enable is reset,
+	 * that means the Tx interrupt must be re-enabled
+	 * due to call UART_IntTransmit() function to trigger
+	 * this interrupt type
+	 */
+	if (TxIntStat == RESET) {
+		// Disable THRE interrupt
+		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
+
+		/* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes
+		 * of data or break whenever ring buffers are empty */
+		/* Wait until THR empty */
+		while (Chip_UART_CheckBusy(UARTx) == SET) ;
+
+		while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
+			/* Move a piece of data into the transmit FIFO */
+			if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) {
+				/* Update transmit ring FIFO tail pointer */
+				__BUF_INCR(rb.tx_tail);
+			}
+			else {
+				break;
+			}
+		}
+
+		/* If there is no more data to send, disable the transmit
+		   interrupt - else enable it or keep it enabled */
+		if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
+			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
+			/* Reset Tx Interrupt state */
+			TxIntStat = RESET;
+		}
+		else {
+			/* Set Tx Interrupt state */
+			TxIntStat = SET;
+			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
+		}
+	}
+	/*
+	 * Otherwise, re-enables Tx Interrupt
+	 */
+	else {
+		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
+	}
+
+	return bytes;
+}
+
+/* UART read function for interrupt mode (using ring buffers) */
+uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen)
+{
+	uint8_t *data = (uint8_t *) rxbuf;
+	uint32_t bytes = 0;
+
+	/* Temporarily lock out UART receive interrupts during this
+	   read so the UART receive interrupt won't cause problems
+	   with the index values */
+	Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
+
+	/* Loop until receive buffer ring is empty or
+	    until max_bytes expires */
+	while ((buflen > 0) && (!(__BUF_IS_EMPTY(rb.rx_head, rb.rx_tail)))) {
+		/* Read data from ring buffer into user buffer */
+		*data = rb.rx[rb.rx_tail];
+		data++;
+
+		/* Update tail pointer */
+		__BUF_INCR(rb.rx_tail);
+
+		/* Increment data count and decrement buffer size count */
+		bytes++;
+		buflen--;
+	}
+
+	/* Re-enable UART interrupts */
+	Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
+
+	return bytes;
+}
+
+/* Reset Tx and Rx ring buffer (head and tail) */
+void Chip_UART_InitRingBuffer(void)
+{
+	TxIntStat = RESET;
+
+	/* Reset ring buf head and tail idx */
+	__BUF_RESET(rb.rx_head);
+	__BUF_RESET(rb.rx_tail);
+	__BUF_RESET(rb.tx_head);
+	__BUF_RESET(rb.tx_tail);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h

@@ -0,0 +1,288 @@
+/*
+ * @brief LPC18xx/43xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __UART_18XX_43XX_H_
+#define __UART_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup 18XX_43XX CHIP: LPC18xx/43xx UART Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Configure data width, parity mode and stop bits
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	Databits	: UART Data width, should be:
+ *                          UART_DATABIT_5: UART 5 bit data mode
+ *                          UART_DATABIT_6: UART 6 bit data mode
+ *                          UART_DATABIT_7: UART 7 bit data mode
+ *                          UART_DATABIT_8: UART 8 bit data mode
+ * @param	Parity		: UART Parity mode, should be:
+ *                          UART_PARITY_NONE: No parity
+ *                          UART_PARITY_ODD:  Odd parity
+ *                          UART_PARITY_EVEN: Even parity
+ *                          UART_PARITY_SP_1: Forced "1" stick parity
+ *                          UART_PARITY_SP_0: Forced "0" stick parity
+ * @param	Stopbits	: Number of stop bits, should be:
+ *                          UART_STOPBIT_1: One Stop Bit Select
+ *                          UART_STOPBIT_2: Two Stop Bits Select
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_ConfigData(LPC_USART_Type *UARTx,
+										UART_DATABIT_Type Databits,
+										UART_PARITY_Type Parity,
+										UART_STOPBIT_Type Stopbits)
+{
+	IP_UART_ConfigData(UARTx, Databits, Parity, Stopbits);
+}
+
+/**
+ * @brief	Send a block of data via UART peripheral
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	txbuf		: Pointer to Transmit buffer
+ * @param	buflen		: Length of Transmit buffer
+ * @param   flag		: Flag used in  UART transfer, should be NONE_BLOCKING or BLOCKING
+ * @return	Number of bytes sent
+ */
+STATIC INLINE uint32_t Chip_UART_Send(LPC_USART_Type *UARTx, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+	return IP_UART_Send(UARTx, txbuf, buflen, flag);
+}
+
+/**
+ * @brief	Receive a block of data via UART peripheral
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	rxbuf		: Pointer to Received buffer
+ * @param	buflen		: Length of Received buffer
+ * @param   flag		: Flag mode, should be NONE_BLOCKING or BLOCKING
+ * @return	Number of bytes received
+ */
+STATIC INLINE uint32_t Chip_UART_Receive(LPC_USART_Type *UARTx,
+										 uint8_t *rxbuf,
+										 uint32_t buflen,
+										 TRANSFER_BLOCK_Type flag)
+{
+	return IP_UART_Receive(UARTx, rxbuf, buflen, flag);
+}
+
+/* UART FIFO functions ----------------------------------------------------------*/
+/**
+ * @brief	Configure FIFO function on selected UART peripheral
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	FIFOCfg		: Pointer to a UART_FIFO_CFG_Type Structure that contains specified information about FIFO configuration
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_FIFOConfig(LPC_USART_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
+{
+	IP_UART_FIFOConfig(UARTx, FIFOCfg);
+}
+
+/**
+ * @brief	Fills each UART_FIFOInitStruct member with its default value:
+ *			- FIFO_DMAMode = DISABLE
+ *			- FIFO_Level = UART_FIFO_TRGLEV0
+ *			- FIFO_ResetRxBuf = ENABLE
+ *			- FIFO_ResetTxBuf = ENABLE
+ *			- FIFO_State = ENABLE
+ * @param	UART_FIFOInitStruct	: Pointer to a UART_FIFO_CFG_Type structure which will be initialized.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
+{
+	IP_UART_FIFOConfigStructInit(UART_FIFOInitStruct);
+}
+
+/* UART operate functions -------------------------------------------------------*/
+/**
+ * @brief	Enable or disable specified UART interrupt.
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	UARTIntCfg	: Specifies the interrupt flag, should be one of the following:
+ *                  - UART_INTCFG_RBR   : RBR Interrupt enable
+ *                  - UART_INTCFG_THRE  : THR Interrupt enable
+ *                  - UART_INTCFG_RLS   : RX line status interrupt enable
+ *                  - UART1_INTCFG_MS	: Modem status interrupt enable (UART1 only)
+ *                  - UART1_INTCFG_CTS	: CTS1 signal transition interrupt enable (UART1 only)
+ *                  - UART_INTCFG_ABEO  : Enables the end of auto-baud interrupt
+ *                  - UART_INTCFG_ABTO  : Enables the auto-baud time-out interrupt
+ * @param	NewState	: New state of specified UART interrupt type, should be ENALBE or DISALBE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_IntConfig(LPC_USART_Type *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
+{
+	IP_UART_IntConfig(UARTx, UARTIntCfg, NewState);
+}
+
+/**
+ * @brief	Get Source Interrupt
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Return the value of IIR register
+ */
+STATIC INLINE uint32_t Chip_UART_IntGetStatus(LPC_USART_Type *UARTx)
+{
+	return IP_UART_IntGetStatus(UARTx);
+}
+
+/**
+ * @brief	Get current value of Line Status register in UART peripheral.
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Current value of Line Status register in UART peripheral
+ */
+STATIC INLINE uint8_t Chip_UART_GetLineStatus(LPC_USART_Type *UARTx)
+{
+	return IP_UART_GetLineStatus(UARTx);
+}
+
+/**
+ * @brief	Check whether if UART is busy or not
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	RESET if UART is not busy, otherwise return SET.
+ */
+STATIC INLINE FlagStatus Chip_UART_CheckBusy(LPC_USART_Type *UARTx)
+{
+	return IP_UART_CheckBusy(UARTx);
+}
+
+/**
+ * @brief	Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_ForceBreak(LPC_USART_Type *UARTx)
+{
+	IP_UART_ForceBreak(UARTx);
+}
+
+/**
+ * @brief	Transmit a single data through UART peripheral
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	Data		: Data to transmit (must be 8-bit long)
+ * @return	Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
+ */
+STATIC INLINE Status Chip_UART_SendByte(LPC_USART_Type *UARTx, uint8_t Data)
+{
+	return IP_UART_SendByte(UARTx, Data);
+}
+
+/**
+ * @brief	Receive a single data from UART peripheral
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	*Data		: Pointer to Data to receive (must be 8-bit long)
+ * @return	Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
+ */
+STATIC INLINE Status Chip_UART_ReceiveByte(LPC_USART_Type *UARTx, uint8_t *Data)
+{
+	return IP_UART_ReceiveByte(UARTx, Data);
+}
+
+/**
+ * @brief	Initializes the UARTx peripheral.
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Nothing
+ */
+void Chip_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	De-initializes the UARTx peripheral.
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Nothing
+ */
+void Chip_UART_DeInit(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Determines best dividers to get a target baud rate
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	baudrate	: Desired UART baud rate.
+ * @return	Error status, could be SUCCESS or ERROR
+ */
+Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate);
+
+/**
+ * @brief	Enable/Disable transmission on UART TxD pin
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @param	NewState	: New State of Tx transmission function, should be ENABLE or DISABLE
+ * @return Nothing
+ */
+void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState);
+
+/**
+ * @brief	Get Interrupt Stream Status
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Return the interrupt status, should be:
+ *              - UART_ERROR
+ *              - READY_TO_RECEIVE
+ *              - READY_TO_SEND
+ */
+UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Uart interrupt service routine (chip layer)
+ * @param	UARTx		: Pointer to selected UARTx peripheral
+ * @return	Nothing
+ */
+void Chip_UART_Interrupt_Handler (LPC_USART_Type *UARTx);
+
+/**
+ * @brief	UART transmit function for interrupt mode (using ring buffers)
+ * @param	UARTx	: Selected UART peripheral used to send data, should be UART0
+ * @param	txbuf	: Pointer to Transmit buffer
+ * @param	buflen	: Length of Transmit buffer
+ * @return	Number of bytes actually sent to the ring buffer
+ */
+uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen);
+
+/**
+ * @brief	UART read function for interrupt mode (using ring buffers)
+ * @param	UARTx	: Selected UART peripheral used to send data, should be UART0
+ * @param	rxbuf	: Pointer to Received buffer
+ * @param	buflen	: Length of Received buffer
+ * @return	Number of bytes actually read from the ring buffer
+ */
+uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen);
+
+/**
+ * @brief	Reset Tx and Rx ring buffer (head and tail)
+ * @return	Nothing
+ */
+void Chip_UART_InitRingBuffer(void);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+#endif /* __UART_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c

@@ -0,0 +1,70 @@
+/*
+ * @brief LPC18xx/43xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "wwdt_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the Watchdog timer */
+void Chip_WWDT_Init(void)
+{
+	/* Disable watchdog */
+	LPC_WWDT->MOD       = 0;
+	LPC_WWDT->TC        = 0xFF;
+	LPC_WWDT->WARNINT   = 0xFFFF;
+	LPC_WWDT->WINDOW    = 0xFFFFFF;
+}
+
+/* Clear WWDT interrupt status flags */
+void Chip_WWDT_ClearStatusFlag(uint32_t status)
+{
+	if (status & WWDT_WDMOD_WDTOF) {
+		LPC_WWDT->MOD &= ~WWDT_WDMOD_WDTOF;
+	}
+
+	if (status & WWDT_WDMOD_WDINT) {
+		LPC_WWDT->MOD |= WWDT_WDMOD_WDINT;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h

@@ -0,0 +1,191 @@
+/*
+ * @brief LPC18xx/43xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __WWDT_18XX_43XX_H_
+#define __WWDT_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** WDT oscillator frequency value */
+#define WDT_OSC     (CGU_IRC_FREQ)
+
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDEN             ((uint32_t) (1 << 0))
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDRESET          ((uint32_t) (1 << 1))
+/** WWDT time out flag bit */
+#define WWDT_WDMOD_WDTOF            ((uint32_t) (1 << 2))
+/** WDT Time Out flag bit */
+#define WWDT_WDMOD_WDINT            ((uint32_t) (1 << 3))
+/** WWDT Protect flag bit */
+#define WWDT_WDMOD_WDPROTECT        ((uint32_t) (1 << 4))
+
+/** Minimum tick count for timer value and window value */
+#define WWDT_TICKS_MIN 0xFF
+
+/** Maximum tick count for timer value and window value */
+#define WWDT_TICKS_MAX 0xFFFFFF
+
+/**
+ * @brief	Initialize the Watchdog timer
+ * @return	None
+ */
+void Chip_WWDT_Init(void);
+
+/**
+ * @brief	Set WDT timeout constant value used for feed
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ */
+STATIC INLINE void Chip_WWDT_SetTimeOut(uint32_t timeout)
+{
+	LPC_WWDT->TC = timeout;
+}
+
+/**
+ * @brief	Feed watchdog timer
+ * @return	None
+ * If this function isn't called, a watchdog timer warning will occur.
+ * After the warning, a timeout will occur if a feed has happened.
+ */
+STATIC INLINE void Chip_WWDT_Feed(void)
+{
+	LPC_WWDT->FEED = 0xAA;
+	LPC_WWDT->FEED = 0x55;
+}
+
+/**
+ * @brief	Set WWDT warning interrupt
+ * @param	timeout	: WDT warning in ticks, between 0 and 1023
+ * @return	None
+ * This is the number of ticks after the watchdog interrupt that the
+ * warning interrupt will be generated.
+ */
+STATIC INLINE void Chip_WWDT_SetWarning(uint32_t timeout)
+{
+	LPC_WWDT->WARNINT = timeout;
+}
+
+/**
+ * @brief	Set WWDT window time
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ * The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
+ * function and this function, with this function defining the last tick before the
+ * watchdog window interrupt occurs.
+ */
+STATIC INLINE void Chip_WWDT_SetWindow(uint32_t timeout)
+{
+	LPC_WWDT->WINDOW = timeout;
+}
+
+/**
+ * @brief	Enable watchdog timer options
+ * @param	options : An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
+ * are set (or unset) with no other options.
+ */
+STATIC INLINE void Chip_WWDT_SetOption(uint32_t options)
+{
+	LPC_WWDT->MOD |= options;
+}
+
+/**
+ * @brief	Disable/clear watchdog timer options
+ * @param	options : An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDTOF).
+ */
+STATIC INLINE void Chip_WWDT_UnsetOption(uint32_t options)
+{
+	LPC_WWDT->MOD &= ~options;
+}
+
+/**
+ * @brief	Enable WWDT activity
+ * @return	None
+ */
+STATIC INLINE void Chip_WWDT_Start(void)
+{
+	Chip_WWDT_SetOption(WWDT_WDMOD_WDEN);
+	Chip_WWDT_Feed();
+}
+
+/**
+ * @brief	Read WWDT status flag
+ * @return	Watchdog status, an Or'ed value of WWDT_WDMOD_*
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetStatus(void)
+{
+	return LPC_WWDT->MOD;
+}
+
+/**
+ * @brief	Clear WWDT interrupt status flags
+ * @param	flag	: Or'ed value of status flag(s) that you want to clear, should be:
+ *              - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
+ *              - WWDT_WDMOD_WDINT: Clear watchdog warning flag
+ * @return	None
+ */
+void Chip_WWDT_ClearStatusFlag(uint32_t status);
+
+/**
+ * @brief	Get the current value of WDT
+ * @return	current value of WDT
+ */
+STATIC INLINE uint32_t WWDT_GetCurrentCount(void)
+{
+	return LPC_WWDT->TV;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WWDT_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c

@@ -0,0 +1,294 @@
+/*
+ * @brief    Generic memory tests
+ *           Various memory tests for testing external memory integrity. Includes
+ *           inverse address, walking bit, and pattern tests.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "mem_tests.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Walking 0 memory test */
+bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup)
+{
+	int i = 0;
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write walking 0 pattern */
+	while (fbytes > 0) {
+		*addr = ~(1 << i);
+
+		addr++;
+		fbytes -= 4;
+		i++;
+		if (i >= 32) {
+			i = 0;
+		}
+	}
+
+	/* Verify walking 0 pattern */
+	i = 0;
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != ~(1 << i)) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = ~(1 << i);
+			return false;
+		}
+
+		addr++;
+		fbytes -= 4;
+		i++;
+		if (i >= 32) {
+			i = 0;
+		}
+	}
+
+	return true;
+}
+
+/* Walking 1 memory test */
+bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup)
+{
+	int i = 0;
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write walking 1 pattern */
+	while (fbytes > 0) {
+		*addr = (1 << i);
+
+		addr++;
+		fbytes -= 4;
+		i++;
+		if (i >= 32) {
+			i = 0;
+		}
+	}
+
+	/* Verify walking 1 pattern */
+	i = 0;
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != (1 << i)) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = (1 << i);
+			return false;
+		}
+
+		addr++;
+		fbytes -= 4;
+		i++;
+		if (i >= 32) {
+			i = 0;
+		}
+	}
+
+	return true;
+}
+
+/* Address memory test */
+bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup)
+{
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write address for memory location */
+	while (fbytes > 0) {
+		*addr =  (uint32_t) addr;
+
+		addr++;
+		fbytes -= 4;
+	}
+
+	/* Verify address for memory location */
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != (uint32_t) addr) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = (uint32_t) addr;
+			return false;
+		}
+
+		addr++;
+		fbytes -= 4;
+	}
+
+	return true;
+}
+
+/* Inverse address memory test */
+bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup)
+{
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write inverse address for memory location */
+	while (fbytes > 0) {
+		*addr =  ~(uint32_t) addr;
+
+		addr++;
+		fbytes -= 4;
+	}
+
+	/* Verify inverse address for memory location */
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != ~(uint32_t) addr) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = ~(uint32_t) addr;
+			return false;
+		}
+
+		addr++;
+		fbytes -= 4;
+	}
+
+	return true;
+}
+
+/* Pattern memory test */
+bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup)
+{
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+	uint32_t pattern = 0x55AA55AA;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write pattern for memory location */
+	while (fbytes > 0) {
+		*addr =  pattern;
+
+		pattern = ~pattern;
+		addr++;
+		fbytes -= 4;
+	}
+
+	/* Verify pattern for memory location */
+	pattern = 0x55AA55AA;
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != pattern) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = pattern;
+			return false;
+		}
+
+		pattern = ~pattern;
+		addr++;
+		fbytes -= 4;
+	}
+
+	return true;
+}
+
+/* Pattern memory test with seed and increment value */
+bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr)
+{
+	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
+	uint32_t pattern = seed;
+
+	/* Must be 32-bit algined */
+	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
+		return false;
+	}
+
+	/* Write pattern for memory location */
+	while (fbytes > 0) {
+		*addr =  pattern;
+
+		pattern += incr;
+		addr++;
+		fbytes -= 4;
+	}
+
+	/* Verify pattern for memory location */
+	pattern = seed;
+	fbytes = pMemSetup->bytes;
+	addr = pMemSetup->start_addr;
+	while (fbytes > 0) {
+		if (*addr != pattern) {
+			pMemSetup->fail_addr = addr;
+			pMemSetup->is_val = *addr;
+			pMemSetup->ex_val = pattern;
+			return false;
+		}
+
+		pattern += incr;
+		addr++;
+		fbytes -= 4;
+	}
+
+	return true;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h

@@ -0,0 +1,116 @@
+/*
+ * @brief    Generic memory tests
+ *           Various memory tests for testing external memory integrity. Includes
+ *           inverse address, walking bit, and pattern tests.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __MEM_TESTS_H_
+#define __MEM_TESTS_H_
+
+#include "lpc_types.h"
+
+/** @defgroup CHIP_Memory_Tests CHIP: Various RAM memory tests
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Memory test address/size and result structure
+ */
+typedef struct {
+	uint32_t *start_addr;	/*!< Starting address for memory test */
+	uint32_t bytes;			/*!< Size in bytes for memory test */
+	uint32_t *fail_addr;	/*!< Failed address of test (returned only if failed) */
+	uint32_t is_val;		/*!< Failed value of test (returned only if failed) */
+	uint32_t ex_val;		/*!< Expected value of test (returned only if failed) */
+} MEM_TEST_SETUP_T;
+
+/**
+ * @brief	Walking 0 memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes a shifting 0 bit pattern to the entire memory range and
+ * verifies the result after all memory locations are written
+ */
+bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Walking 1 memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes a shifting 1 bit pattern to the entire memory range and
+ * verifies the result after all memory locations are written
+ */
+bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Address memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the address to each memory location and verifies the
+ * result after all memory locations are written
+ */
+bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Inverse address memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the inverse address to each memory location and verifies the
+ * result after all memory locations are written
+ */
+bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Pattern memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the an alternating 0x55/0xAA pattern to each memory location
+ * and verifies the result after all memory locations are written
+ */
+bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Pattern memory test with seed and increment value
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @param	seed		: Initial seed value for test
+ * @param	incr		: Increment value for each memory location
+ * @return	true if the test passed, or false on failure
+ * Writes the an alternating pattern to each memory location based on a
+ * passed seedn and increment value and verifies the result after all
+ * memory locations are written
+ */
+bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr);
+
+/**
+ * @}
+ */
+
+#endif /* __MEM_TESTS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c

@@ -0,0 +1,168 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "ring_buffer.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize ring buffer */
+void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
+{
+	RingBuff->bufferBase = RingBuff->bufferIn = RingBuff->bufferOut = buffer;
+	RingBuff->bufferLast = RingBuff->bufferBase + (itemSize * count);
+	RingBuff->count = count;
+	RingBuff->itemSize = itemSize;
+	RingBuff->used = 0;
+}
+
+/* Return empty status of ring buffer */
+bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		*RingBuff->bufferIn = data8;
+		RingBuff->used++;
+		RingBuff->bufferIn++;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Insert 16-bit value in ring buffer */
+bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		uint16_t *buff16 = (uint16_t *) RingBuff->bufferIn;
+		*buff16 = data16;
+		RingBuff->used++;
+		buff16++;
+		RingBuff->bufferIn = (uint8_t *) buff16;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Insert 32-bit value in ring buffer */
+bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		uint32_t *buff32 = (uint32_t *) RingBuff->bufferIn;
+		*buff32 = data32;
+		RingBuff->used++;
+		buff32++;
+		RingBuff->bufferIn = (uint8_t *) buff32;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Pop a 8-bit value from the ring buffer */
+bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		*data8 = *RingBuff->bufferOut;
+		RingBuff->used--;
+		RingBuff->bufferOut++;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}
+
+/* Pop a 16-bit value from the ring buffer */
+bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		uint16_t *buff16 = (uint16_t *) RingBuff->bufferOut;
+		*data16 = *buff16;
+		RingBuff->used--;
+		buff16++;
+		RingBuff->bufferOut = (uint8_t *) buff16;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}
+
+/* Pop a 32-bit value from the ring buffer */
+bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		uint32_t *buff32 = (uint32_t *) RingBuff->bufferOut;
+		*data32 = *buff32;
+		RingBuff->used--;
+		data32++;
+		RingBuff->bufferOut = (uint8_t *) data32;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h

@@ -0,0 +1,143 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RING_BUFFER_H_
+#define __RING_BUFFER_H_
+
+#include "lpc_types.h"
+
+/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Ring buffer structure
+ */
+typedef struct {
+	uint8_t *bufferBase, *bufferLast;
+	uint8_t *bufferIn, *bufferOut;
+	int count, used, itemSize;
+} RINGBUFF_T;
+
+/**
+ * @brief	Initialize ring buffer
+ * @param	RingBuff	: Pointer to ring buffer to initialize
+ * @param	buffer		: Pointer to buffer to associate with RingBuff
+ * @param	itemSize	: Size of each buffer item size (1, 2 or 4 bytes)
+ * @param	count		: Size of ring buffer
+ * @return	Nothing
+ */
+void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->used;
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	true if the ring buffer is full, otherwise false
+ */
+STATIC INLINE bool RingBuffer_IsFull(RINGBUFF_T *RingBuff)
+{
+	return (bool) (RingBuff->used >= RingBuff->count);
+}
+
+/**
+ * @brief	Return empty status of ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	true if the ring buffer is empty, otherwise false
+ */
+STATIC INLINE bool RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
+{
+	return (bool) (RingBuff->used == 0);
+}
+
+/**
+ * @brief	Insert 8-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data8		: Byte to insert in ring buffer
+ * @return	true if a valid byte was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8);
+
+/**
+ * @brief	Insert 16-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data16		: 16-bit value to insert in ring buffer
+ * @return	true if valid data was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16);
+
+/**
+ * @brief	Insert 32-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data32		: 32-bit value to insert in ring buffer
+ * @return	true if valid data was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32);
+
+/**
+ * @brief	Pop a 8-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data8		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8);
+
+/**
+ * @brief	Pop a 16-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data16		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16);
+
+/**
+ * @brief	Pop a 32-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data32		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32);
+
+/**
+ * @}
+ */
+
+#endif /* __RING_BUFFER_H_ */

bsp/xplorer4330/libraries/lpc_ip/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('lpc_ip', src, depend = [], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_ip/adc_001.c

@@ -0,0 +1,170 @@
+/*
+ * @brief ADC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "adc_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Configure clock for ADC */
+static void SetClock(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
+{
+	uint32_t temp, adcBitRate;
+
+	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
+	   A/D converter, which should be less than or equal to 4.5MHz.
+	   A fully conversion requires (bits_accuracy+1) of these clocks.
+	   ADC clock = PCLK_ADC0 / (CLKDIV + 1);
+	   ADC rate = ADC clock / (bits_accuracy+1);
+	 */
+	adcBitRate = (adcRate * (11 - bitsAccuracy));
+
+	/* Get the round value by fomular: (2*A + B)/(2*B) */
+	temp = ((adcPerClock * 2 + adcBitRate) / (adcBitRate * 2)) - 1;
+
+	/* Enable PDN bit and clock bits */
+	pADC->CR &= ~(ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07));
+	pADC->CR |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(bitsAccuracy);
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC */
+void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
+{
+	pADC->INTEN = 0;		/* Disable all interrupts */
+	pADC->CR |= ADC_CR_PDN;	/* Set PDN bit for ADC*/
+	SetClock(pADC, adcRate, adcPerClock, bitsAccuracy);
+}
+
+/* Shutdown ADC */
+void IP_ADC_DeInit(IP_ADC_001_Type *pADC)
+{
+	pADC->INTEN = 0x00000100;
+	pADC->CR = 0;
+}
+
+/* Set burst mode for ADC */
+void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState)
+{
+	if (NewState == DISABLE) {
+		pADC->CR &= ~ADC_CR_BURST;
+	}
+	else {
+		pADC->CR |= ADC_CR_BURST;
+	}
+}
+
+/* Get the ADC value */
+Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data)
+{
+	uint32_t temp;
+	temp = pADC->DR[channel];
+	if (!ADC_DR_DONE(temp)) {
+		return ERROR;
+	}
+	//	if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST))
+	//	return ERROR;
+	*data = (uint16_t) ADC_DR_RESULT(temp);
+	return SUCCESS;
+}
+
+/* Get ADC Channel status from ADC data register */
+FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType)
+{
+	switch (StatusType) {
+	case ADC_DR_DONE_STAT:
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_OVERRUN_STAT:
+		channel += 8;
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_ADINT_STAT:
+		return pADC->STAT >> 16 ? SET : RESET;
+
+	default:
+		break;
+	}
+	return RESET;
+}
+
+/* Set the edge start condition */
+void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode)
+{
+	if (edge_mode) {
+		pADC->CR |= ADC_CR_EDGE;
+	}
+	else {
+		pADC->CR &= ~ADC_CR_EDGE;
+	}
+}
+
+/* Enable/Disable ADC channel number */
+void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->CR |= ADC_CR_CH_SEL(channel);
+	}
+	else {
+		pADC->CR &= ~ADC_CR_START_MASK;
+		pADC->CR &= ~ADC_CR_CH_SEL(channel);
+	}
+}
+
+/* Set start mode for ADC */
+void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode)
+{
+	pADC->CR &= ~ADC_CR_START_MASK;
+	pADC->CR |= ADC_CR_START_MODE_SEL((uint32_t) start_mode);
+}
+
+/* Enable/Disable interrupt for ADC channel */
+void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->INTEN |= (1UL << channel);
+	}
+	else {
+		pADC->INTEN &= (~(1UL << channel));
+	}
+}

bsp/xplorer4330/libraries/lpc_ip/adc_001.h

@@ -0,0 +1,182 @@
+/*
+ * @brief ADC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_001_H_
+#define __ADC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief 10 or 12-bit ADC register block structure
+ */
+typedef struct {					/*!< ADCn Structure */
+	__IO uint32_t CR;				/*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+	__I  uint32_t GDR;				/*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+	__I  uint32_t RESERVED0;
+	__IO uint32_t INTEN;			/*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+	__I  uint32_t DR[8];			/*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+	__I  uint32_t STAT;				/*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+#if !defined(CHIP_LPC18XX) && !defined(CHIP_LPC43XX)
+	__IO uint32_t ADTRM;
+#endif
+} IP_ADC_001_Type;
+
+/**
+ * @brief ADC register support bitfields and mask
+ */
+#define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF))	/*!< Mask for getting the ADC data read value */
+#define ADC_DR_DONE(n)          (((n) >> 31))			/*!< Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL)))	/*!< Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n)        ((1UL << (n)))			/*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))	/*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST            ((1UL << 16))			/*!< Repeated conversions A/D enable bit */
+#define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))	/*!< Number of ADC accuracy bits */
+#define ADC_CR_PDN              ((1UL << 21))			/*!< ADC convert in power down mode */
+#define ADC_CR_START_MASK       ((7UL << 24))			/*!< ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))		/*!< Select Start Mode */
+#define ADC_CR_START_NOW        ((1UL << 24))			/*!< Start conversion now */
+#define ADC_CR_START_CTOUT15    ((2UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8     ((3UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0   ((4UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1   ((5UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2      ((6UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE             ((1UL << 27))			/*!< Start conversion on a falling edge on the selected CAP/MAT signal */
+
+/**
+ * @brief	ADC status register used for IP drivers
+ */
+typedef enum {
+	ADC_DR_DONE_STAT,	/*!< ADC data register staus */
+	ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
+	ADC_DR_ADINT_STAT	/*!< ADC interrupt status */
+} IP_ADC_Status;
+
+/**
+ * @brief	Initialize for ADC
+ * @param	pADC			: The base of ADC peripheral on the chip
+ * @param	adcRate			: Sample rate of A/D converter
+ * @param	adcPerClock		: The APB clock
+ * @param	bitsAccuracy	: The accuracy of LSB value, should be ADC_10BITS -> ADC_3BITS
+ * @return	 Nothing
+ * Disable all ADC interrupts, set bit PDN, set ADC clock frequency
+ * This is not the sample rate, but the clock for the ADC machine, and is usually set to
+ * maximum. Applications may choose a lower frequency if they have high-impedance sources.
+ * This is because a lower clock frequency produces a longer sampling time.
+ */
+void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy);
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ * Reset the ADC control and INTEN Register to reset values (disabled)
+ */
+void IP_ADC_DeInit(IP_ADC_001_Type *pADC);
+
+/**
+ * @brief	Set burst mode for ADC
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: ENABLE for burst mode, or DISABLE for normal mode
+ * @return	Nothing
+ */
+void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState);
+
+/**
+ * @brief	Get the ADC value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be read value, should be 0..7
+ * @param	data		: Data buffer to store the A/D value
+ * @return	Status		: SUCCESS or ERROR
+ */
+Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data);
+
+/**
+ * @brief	Get ADC Channel status from ADC data register
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel number, should be 0..7
+ * @param	StatusType	: Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT
+ * @return	Channel status, SET or RESET
+ */
+FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType);
+
+/**
+ * @brief	Set the edge start condition
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	edge_mode	: 0 = rising, != = falling
+ * @return	Nothing
+ */
+void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode);
+
+/**
+ * @brief	Enable/Disable ADC channel number
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel number
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @brief	Set start mode for ADC
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	start_mode	: Start mode choose one of modes in 'ADC_START_*' enumeration type definitions
+ * @return	Nothing
+ */
+void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode);
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel assert the interrupt
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/atimer_001.c

@@ -0,0 +1,55 @@
+/*
+ * @brief Alarm Timer Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "atimer_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Close ATIMER device */
+void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer)
+{
+	IP_ATIMER_ClearIntStatus(pATimer);
+	IP_ATIMER_IntDisable(pATimer);
+}

bsp/xplorer4330/libraries/lpc_ip/atimer_001.h

@@ -0,0 +1,160 @@
+/*
+ * @brief Alarm Timer Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ATIMER_001_H_
+#define __ATIMER_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver
+ * @ingroup IP_Drivers
+ * Alarm timer
+ * @{
+ */
+
+/**
+ * @brief Alarm Timer register block structure
+ */
+typedef struct {					/*!< ATIMER Structure       */
+	__IO uint32_t DOWNCOUNTER;		/*!< Downcounter register   */
+	__IO uint32_t PRESET;			/*!< Preset value register  */
+	__I  uint32_t RESERVED0[1012];
+	__O  uint32_t CLR_EN;			/*!< Interrupt clear enable register */
+	__O  uint32_t SET_EN;			/*!< Interrupt set enable register */
+	__I  uint32_t STATUS;			/*!< Status register        */
+	__I  uint32_t ENABLE;			/*!< Enable register        */
+	__O  uint32_t CLR_STAT;			/*!< Clear register         */
+	__O  uint32_t SET_STAT;			/*!< Set register           */
+} IP_ATIMER_001_Type;
+
+/**
+ * @brief	Close ATIMER device
+ * @param	pATimer	:  Pointer to timer device
+ * @return	None
+ * Important: 32KHz clock must be enabled in CREG prior to this call. See
+ * the User Manual for more information.
+ */
+void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer);
+
+/**
+ * @brief	Clear ATIMER Interrupt Status
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->CLR_STAT = 1;
+}
+
+/**
+ * @brief	Set ATIMER Interrupt Status
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->SET_STAT = 1;
+}
+/**
+ * @brief	Enable ATIMER Interrupt
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->SET_EN = 1;
+}
+
+/**
+ * @brief	Disable ATIMER Interrupt
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->CLR_EN = 1;
+}
+
+/**
+ * @brief	Update Preset value
+ * @param	pATimer	: Pointer to timer device
+ * @param	PresetValue	updated preset value
+ * @return	Nothing
+ */
+STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_Type *pATimer, uint32_t PresetValue)
+{
+	pATimer->PRESET = PresetValue;
+}
+
+/**
+ * @brief	Read value of preset register
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	Value of capture register
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->PRESET;
+}
+
+/**
+ * @brief	Returns enable state of ATimer interrupt
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	!0 if the ATimer interrupt is enabled, otherwise 0
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->ENABLE;
+}
+
+/**
+ * @brief	Returns current pending state of ATimer interrupt
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	!0 if the ATimer interrupt is asserted, otherwise 0
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->STATUS;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ATIMER_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/ccan_001.h

@@ -0,0 +1,114 @@
+/*
+ * @brief CCAN registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CCAN_001_H_
+#define __CCAN_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_CCAN_001 IP: CCAN register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief CCAN Controller Area Network register block structure
+ */
+typedef struct {						/*!< C_CAN Structure       */
+	__IO uint32_t CNTL;					/*!< CAN control            */
+	__IO uint32_t STAT;					/*!< Status register        */
+	__I  uint32_t EC;					/*!< Error counter          */
+	__IO uint32_t BT;					/*!< Bit timing register    */
+	__I  uint32_t INT;					/*!< Interrupt register     */
+	__IO uint32_t TEST;					/*!< Test register          */
+	__IO uint32_t BRPE;					/*!< Baud rate prescaler extension register */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t IF1_CMDREQ;			/*!< Message interface command request  */
+	union {
+		__IO uint32_t IF1_CMDMSK_R;		/*!< Message interface command mask (read direction) */
+		__IO uint32_t IF1_CMDMSK_W;		/*!< Message interface command mask (write direction) */
+	};
+
+	__IO uint32_t IF1_MSK1;				/*!< Message interface mask 1 */
+	__IO uint32_t IF1_MSK2;				/*!< Message interface 1 mask 2 */
+	__IO uint32_t IF1_ARB1;				/*!< Message interface 1 arbitration 1 */
+	__IO uint32_t IF1_ARB2;				/*!< Message interface 1 arbitration 2 */
+	__IO uint32_t IF1_MCTRL;			/*!< Message interface 1 message control */
+	__IO uint32_t IF1_DA1;				/*!< Message interface data A1 */
+	__IO uint32_t IF1_DA2;				/*!< Message interface 1 data A2 */
+	__IO uint32_t IF1_DB1;				/*!< Message interface 1 data B1 */
+	__IO uint32_t IF1_DB2;				/*!< Message interface 1 data B2 */
+	__I  uint32_t  RESERVED1[13];
+	__IO uint32_t IF2_CMDREQ;			/*!< Message interface command request  */
+	union {
+		__IO uint32_t IF2_CMDMSK_R;		/*!< Message interface command mask (read direction) */
+		__IO uint32_t IF2_CMDMSK_W;		/*!< Message interface command mask (write direction) */
+	};
+
+	__IO uint32_t IF2_MSK1;				/*!< Message interface mask 1 */
+	__IO uint32_t IF2_MSK2;				/*!< Message interface 1 mask 2 */
+	__IO uint32_t IF2_ARB1;				/*!< Message interface 1 arbitration 1 */
+	__IO uint32_t IF2_ARB2;				/*!< Message interface 1 arbitration 2 */
+	__IO uint32_t IF2_MCTRL;			/*!< Message interface 1 message control */
+	__IO uint32_t IF2_DA1;				/*!< Message interface data A1 */
+	__IO uint32_t IF2_DA2;				/*!< Message interface 1 data A2 */
+	__IO uint32_t IF2_DB1;				/*!< Message interface 1 data B1 */
+	__IO uint32_t IF2_DB2;				/*!< Message interface 1 data B2 */
+	__I  uint32_t  RESERVED2[21];
+	__I  uint32_t TXREQ1;				/*!< Transmission request 1 */
+	__I  uint32_t TXREQ2;				/*!< Transmission request 2 */
+	__I  uint32_t  RESERVED3[6];
+	__I  uint32_t ND1;					/*!< New data 1             */
+	__I  uint32_t ND2;					/*!< New data 2             */
+	__I  uint32_t  RESERVED4[6];
+	__I  uint32_t IR1;					/*!< Interrupt pending 1    */
+	__I  uint32_t IR2;					/*!< Interrupt pending 2    */
+	__I  uint32_t  RESERVED5[6];
+	__I  uint32_t MSGV1;				/*!< Message valid 1        */
+	__I  uint32_t MSGV2;				/*!< Message valid 2        */
+	__I  uint32_t  RESERVED6[6];
+	__IO uint32_t CLKDIV;				/*!< CAN clock divider register */
+} IP_CCAN_001_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CCAN_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/dac_001.h

@@ -0,0 +1,64 @@
+/*
+ * @brief DAC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __DAC_001_H_
+#define __DAC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_DAC_001 IP: DAC register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief DAC register block structure
+ */
+typedef struct {			/*!< DAC Structure          */
+	__IO uint32_t  CR;		/*!< DAC register. Holds the conversion data. */
+	__IO uint32_t  CTRL;	/*!< DAC control register.  */
+	__IO uint32_t  CNTVAL;	/*!< DAC counter value register. */
+} IP_DAC_001_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/emc_001.c

@@ -0,0 +1,274 @@
+/*
+ * @brief EMC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "emc_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* DIV function with result rounded up */
+#define EMC_DIV_ROUND_UP(x, y)  ((x + y - 1) / y)
+
+#ifndef EMC_SUPPORT_ONLY_PL172
+/* Get ARM External Memory Controller Version */
+static uint32_t EMC_GetARMPeripheralID(IP_EMC_001_Type *pEMC)
+{
+	uint32_t *RegAdd;
+	RegAdd = (uint32_t *) ((uint32_t) pEMC + 0xFE0);
+	return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) |
+		   ((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24);
+}
+
+#endif
+
+/* Calculate Clock Count from Timing Unit(nanoseconds) */
+static uint32_t EMC_TimingParamConvert(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust)
+{
+	uint32_t temp;
+	if (input_ns < 0) {
+		return (-input_ns) >> 8;
+	}
+	temp = EMC_Clock / 1000000;		/* MHz calculation */
+	temp = temp * input_ns / 1000;
+
+	/* round up */
+	temp += 0xFF;
+
+	/* convert to simple integer number format */
+	temp >>= 8;
+	if (temp > adjust) {
+		return temp - adjust;
+	}
+
+	return 0;
+}
+
+/* Get Dynamic Memory Device Colum len */
+static uint32_t EMC_GetColsLen(uint32_t DynConfig)
+{
+	uint32_t DevBusWidth;
+	DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03;
+	if (DevBusWidth == 2) {
+		return 8;
+	}
+	else if (DevBusWidth == 1) {
+		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8;
+	}
+	else if (DevBusWidth == 0) {
+		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9;
+	}
+
+	return 0;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the Dynamic Controller according to the specified parameters
+   in the IP_EMC_DYN_CONFIG_Type */
+void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock)
+{
+	uint32_t ChipSelect, tmpclk;
+	int i;
+
+	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
+		IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + (ChipSelect << 5));
+
+		EMC_Reg_add->DYNAMICRASCAS0    = Dynamic_Config->DevConfig[ChipSelect].RAS |
+										 ((Dynamic_Config->DevConfig[ChipSelect].ModeRegister <<
+										   (8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00);
+		EMC_Reg_add->DYNAMICCONFIG0    = Dynamic_Config->DevConfig[ChipSelect].DynConfig;
+	}
+	pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig;	/* Read strategy */
+
+	pEMC->DYNAMICRP         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRP, 1);
+	pEMC->DYNAMICRAS        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRAS, 1);
+	pEMC->DYNAMICSREX       = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tSREX, 1);
+	pEMC->DYNAMICAPR        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tAPR, 1);
+	pEMC->DYNAMICDAL        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tDAL, 0);
+	pEMC->DYNAMICWR         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tWR, 1);
+	pEMC->DYNAMICRC         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRC, 1);
+	pEMC->DYNAMICRFC        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRFC, 1);
+	pEMC->DYNAMICXSR        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tXSR, 1);
+	pEMC->DYNAMICRRD        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRRD, 1);
+	pEMC->DYNAMICMRD        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tMRD, 1);
+
+	/* TIM_Waitus(100); */
+	/*TODO: if Timer driver is ready, it should replace below "for" delay technic */
+	for (i = 0; i < 1000; i++) {	/* wait 100us */
+	}
+	pEMC->DYNAMICCONTROL    = 0x00000183;	/* Issue NOP command */
+
+	/* TIM_Waitus(200); */						   /* wait 200us */
+	/*TODO: if Timer driver is ready, it should replace below "for" delay technic */
+	for (i = 0; i < 1000; i++) {}
+	pEMC->DYNAMICCONTROL    = 0x00000103;	/* Issue PALL command */
+
+	pEMC->DYNAMICREFRESH = 2;	/* ( 2 * 16 ) -> 32 clock cycles */
+
+	/* TIM_Waitus(200); */						   /* wait 200us */
+	for (i = 0; i < 80; i++) {}
+
+	tmpclk = EMC_DIV_ROUND_UP(EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16);
+	pEMC->DYNAMICREFRESH    = tmpclk;
+
+	pEMC->DYNAMICCONTROL    = 0x00000083;	/* Issue MODE command */
+
+	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
+		/*uint32_t burst_length;*/
+		uint32_t DynAddr;
+		uint8_t Col_len;
+
+		Col_len = EMC_GetColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig);
+		/* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */
+		/* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */
+		if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) {
+			/*32bit bus */
+			/*burst_length = 2;*/
+			Col_len += 2;
+		}
+		else {
+			/*burst_length = 4;*/
+			Col_len += 1;
+		}
+		DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr;
+
+		if (DynAddr != 0) {
+			uint32_t temp;
+			uint32_t ModeRegister;
+			ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister;
+			temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len)));
+			temp = temp;
+		}
+	}
+	pEMC->DYNAMICCONTROL    = 0x00000000;	/* Issue NORMAL command */
+
+	/* enable buffers */
+	pEMC->DYNAMICCONFIG0    |= 1 << 19;
+	pEMC->DYNAMICCONFIG1    |= 1 << 19;
+	pEMC->DYNAMICCONFIG2    |= 1 << 19;
+	pEMC->DYNAMICCONFIG3    |= 1 << 19;
+}
+
+/* Set Deep Sleep Mode for Dynamic Memory Controller */
+void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable)
+{
+	if (Enable) {
+		pEMC->DYNAMICCONTROL |= 1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT;
+	}
+	else {
+		pEMC->DYNAMICCONTROL &= ~(1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT);
+	}
+}
+
+/* Enable Dynamic Memory Controller */
+void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable)
+{
+	if (Enable) {
+		pEMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE;
+	}
+	else {
+		pEMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE;
+	}
+}
+
+/* Initializes the Static Controller according to the specified parameters
+ * in the IP_EMC_STATIC_CONFIG_Type
+ */
+void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock)
+{
+	IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5));
+	EMC_Reg_add->STATICCONFIG0      = Static_Config->Config;
+	EMC_Reg_add->STATICWAITWEN0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWen, 1);
+	EMC_Reg_add->STATICWAITOEN0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitOen, 0);
+	EMC_Reg_add->STATICWAITRD0      = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitRd, 1);
+	EMC_Reg_add->STATICWAITPAG0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitPage, 1);
+	EMC_Reg_add->STATICWAITWR0      = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWr, 2);
+	EMC_Reg_add->STATICWAITTURN0    = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitTurn, 1);
+}
+
+/* Mirror CS1 to CS0 and DYCS0 */
+void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable)
+{
+	if (Enable) {
+		pEMC->CONTROL |= 1 << 1;
+	}
+	else {
+		pEMC->CONTROL &= ~(1 << 1);
+	}
+}
+
+/* Enable EMC */
+void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable)
+{
+	if (Enable) {
+		pEMC->CONTROL |= 1;
+	}
+	else {
+		pEMC->CONTROL &= ~(1);
+	}
+}
+
+/* Set EMC LowPower Mode */
+void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable)
+{
+	if (Enable) {
+		pEMC->CONTROL |= 1 << 2;
+	}
+	else {
+		pEMC->CONTROL &= ~(1 << 2);
+	}
+}
+
+/* Initialize EMC */
+void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
+{
+	pEMC->CONFIG    = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8);
+
+	/* Enable EMC 001 Normal Memory Map, No low power mode */
+	pEMC->CONTROL     = (Enable ? 1 : 0);
+}
+
+/* Set Static Memory Extended Wait in Clock */
+void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks)
+{
+	pEMC->STATICEXTENDEDWAIT = Wait16Clks;
+}

bsp/xplorer4330/libraries/lpc_ip/emc_001.h

@@ -0,0 +1,357 @@
+/*
+ * @brief EMC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EMC_001_H_
+#define __EMC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_EMC_001 IP: EMC register block and driver
+ * @ingroup IP_Drivers
+ * External Memory Controller
+ * @{
+ */
+
+/**
+ * @brief External Memory Controller (EMC) register block structure
+ */
+typedef struct {							/*!< EMC Structure          */
+	__IO uint32_t  CONTROL;					/*!< Controls operation of the memory controller. */
+	__I  uint32_t  STATUS;					/*!< Provides EMC status information. */
+	__IO uint32_t  CONFIG;					/*!< Configures operation of the memory controller. */
+	__I  uint32_t  RESERVED0[5];
+	__IO uint32_t  DYNAMICCONTROL;			/*!< Controls dynamic memory operation. */
+	__IO uint32_t  DYNAMICREFRESH;			/*!< Configures dynamic memory refresh operation. */
+	__IO uint32_t  DYNAMICREADCONFIG;		/*!< Configures the dynamic memory read strategy. */
+	__I  uint32_t  RESERVED1;
+	__IO uint32_t  DYNAMICRP;				/*!< Selects the precharge command period. */
+	__IO uint32_t  DYNAMICRAS;				/*!< Selects the active to precharge command period. */
+	__IO uint32_t  DYNAMICSREX;				/*!< Selects the self-refresh exit time. */
+	__IO uint32_t  DYNAMICAPR;				/*!< Selects the last-data-out to active command time. */
+	__IO uint32_t  DYNAMICDAL;				/*!< Selects the data-in to active command time. */
+	__IO uint32_t  DYNAMICWR;				/*!< Selects the write recovery time. */
+	__IO uint32_t  DYNAMICRC;				/*!< Selects the active to active command period. */
+	__IO uint32_t  DYNAMICRFC;				/*!< Selects the auto-refresh period. */
+	__IO uint32_t  DYNAMICXSR;				/*!< Selects the exit self-refresh to active command time. */
+	__IO uint32_t  DYNAMICRRD;				/*!< Selects the active bank A to active bank B latency. */
+	__IO uint32_t  DYNAMICMRD;				/*!< Selects the load mode register to active command time. */
+	__I  uint32_t  RESERVED2[9];
+	__IO uint32_t  STATICEXTENDEDWAIT;		/*!< Selects time for long static memory read and write transfers. */
+	__I  uint32_t  RESERVED3[31];
+	__IO uint32_t  DYNAMICCONFIG0;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS0;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED4[6];
+	__IO uint32_t  DYNAMICCONFIG1;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS1;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED5[6];
+	__IO uint32_t  DYNAMICCONFIG2;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS2;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED6[6];
+	__IO uint32_t  DYNAMICCONFIG3;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS3;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED7[38];
+	__IO uint32_t  STATICCONFIG0;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN0;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN0;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD0;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG0;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR0;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN0;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED8;
+	__IO uint32_t  STATICCONFIG1;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN1;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN1;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD1;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG1;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR1;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN1;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED9;
+	__IO uint32_t  STATICCONFIG2;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN2;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN2;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD2;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG2;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR2;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN2;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED10;
+	__IO uint32_t  STATICCONFIG3;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN3;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN3;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD3;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG3;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR3;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN3;			/*!< Selects bus turnaround cycles */
+} IP_EMC_001_Type;
+
+/**
+ * @brief EMC register support bitfields and mask
+ */
+/* Reserve for extending support to ARM9 or nextgen LPC */
+#define EMC_SUPPORT_ONLY_PL172	/*!< Reserve for extending support to ARM9 or nextgen LPC */
+
+#define EMC_CONFIG_ENDIAN_LITTLE    (0)		/*!< Value for EMC to operate in Little Endian Mode */
+#define EMC_CONFIG_ENDIAN_BIG         (1)	/*!< Value for EMC to operate in Big Endian Mode */
+
+#define EMC_CONFIG_BUFFER_ENABLE    (1 << 19)	/*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
+#define EMC_CONFIG_WRITE_PROTECT    (1 << 20)	/*!< EMC Write protect bit in EMC Dynamic Configuration register */
+
+/* Dynamic Memory Configuration Register Bit Definitions */
+#define EMC_DYN_CONFIG_MD_BIT             (3)								/*!< Memory device bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_MD_SDRAM         (0 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as SDRAM in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_MD_LPSDRAM       (1 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_LPSDRAM_BIT      (12)							/*!< LPSDRAM bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_LPSDRAM          (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)	/*!< LPSDRAM value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DEV_SIZE_BIT     (9)									/*!< Device Size starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_16Mb    (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 16Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_64Mb    (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 64Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 128Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 256Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 512Mb Device Size value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DEV_BUS_BIT      (7)									/*!< Device bus width starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_8        (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_16       (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_32       (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)									/*!< Device data bus width starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DATA_BUS_16      (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DATA_BUS_32      (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
+
+/*!< Memory configuration values in EMC Dynamic Configuration Register */
+#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS     ((0x0 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
+#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS    ((0x0 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
+#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS     ((0x1 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
+#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS    ((0x1 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
+#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS    ((0x1 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
+#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
+#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS    ((0x2 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
+#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS    ((0x2 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
+#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
+#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
+#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS    ((0x3 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
+#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
+#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS  ((0x4 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
+
+/*!< Dynamic Memory Mode Register Bit Definition */
+#define EMC_DYN_MODE_BURST_LEN_BIT      (0)	/*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_1        (0)	/*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_2        (1)	/*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_4        (2)	/*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_8        (3)	/*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_FULL     (7)	/*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
+
+#define EMC_DYN_MODE_BURST_TYPE_BIT         (3)									/*!< Burst Type bit in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL  (0 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Sequential in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE  (1 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Interleaved in Dynamic Memory Mode Register */
+
+/*!< CAS Latency in Dynamic Mode Register */
+#define EMC_DYN_MODE_CAS_BIT    (4)							/*!< CAS latency starting bit in Dynamic Memory Mode register */
+#define EMC_DYN_MODE_CAS_1      (1 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 1 cycle */
+#define EMC_DYN_MODE_CAS_2      (2 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 2 cycle */
+#define EMC_DYN_MODE_CAS_3      (3 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 3 cycle */
+
+/*!< Operation Mode in Dynamic Mode register */
+#define EMC_DYN_MODE_OPMODE_BIT           (7)							/*!< Dynamic Mode Operation bit */
+#define EMC_DYN_MODE_OPMODE_STANDARD    (0 << EMC_DYN_MODE_OPMODE_BIT)	/*!< Value for Dynamic standard operation Mode */
+
+/*!< Write Burst Mode in Dynamic Mode register */
+#define EMC_DYN_MODE_WBMODE_BIT             (9)							/*!< Write Burst Mode bit */
+#define EMC_DYN_MODE_WBMODE_PROGRAMMED  (0 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode programmed */
+#define EMC_DYN_MODE_WBMODE_SINGLE_LOC  (1 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode Single LOC */
+
+/*!< Dynamic Memory Control Register Bit Definitions */
+#define EMC_DYN_CONTROL_DEEPSLEEP_BIT   (13)	/*!< Deep sleep Mode bit */
+#define EMC_DYN_CONTROL_ENABLE          (0x03)	/*!< Control Enable value */
+
+/*!< Static Memory Configuration Register Bit Definitions */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_8       (0)	/*!< Static Memory Configuration - 8-bit width */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_16      (1)	/*!< Static Memory Configuration - 16-bit width */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_32      (2)	/*!< Static Memory Configuration - 32-bit width */
+
+#define EMC_STATIC_CONFIG_PAGE_MODE_BIT         (3)										/*!< Page Mode bit No */
+#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE      (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)	/*!< Value to enable Page Mode */
+
+#define EMC_STATIC_CONFIG_CS_POL_BIT            (6)									/*!< Chip Select bit No */
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH    (1 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active High */
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW     (0 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active Low */
+
+#define EMC_STATIC_CONFIG_BLS_BIT           (7)								/*!< BLS Configuration bit No */
+#define EMC_STATIC_CONFIG_BLS_HIGH          (1 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS High Configuration value */
+#define EMC_STATIC_CONFIG_BLS_LOW           (0 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS Low Configuration value */
+
+#define EMC_STATIC_CONFIG_EW_BIT            (8)								/*!< Ext Wait bit No */
+#define EMC_STATIC_CONFIG_EW_ENABLE         (1 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Enabled value */
+#define EMC_STATIC_CONFIG_EW_DISABLE        (0 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Diabled value */
+
+/*!< Q24.8 Fixed Point Helper */
+#define Q24_8_FP(x) ((x) * 256)
+#define EMC_NANOSECOND(x)   Q24_8_FP(x)
+#define EMC_CLOCK(x)        Q24_8_FP(-(x))
+
+/**
+ * @brief	EMC Dynamic Device Configuration structure used for IP drivers
+ */
+typedef struct {
+	uint32_t    BaseAddr;		/*!< Base Address */
+	uint8_t     RAS;			/*!< RAS value */
+	uint32_t    ModeRegister;	/*!< Mode Register value */
+	uint32_t    DynConfig;		/*!< Dynamic Configuration value */
+} IP_EMC_DYN_DEVICE_CONFIG_Type;
+
+/**
+ * @brief EMC Dynamic Configure Struct
+ */
+typedef struct {
+	int32_t RefreshPeriod;							/*!< Refresh period */
+	uint32_t ReadConfig;							/*!< Clock*/
+	int32_t tRP;									/*!< Precharge Command Period */
+	int32_t tRAS;									/*!< Active to Precharge Command Period */
+	int32_t tSREX;									/*!< Self Refresh Exit Time */
+	int32_t tAPR;									/*!< Last Data Out to Active Time */
+	int32_t tDAL;									/*!< Data In to Active Command Time */
+	int32_t tWR;									/*!< Write Recovery Time */
+	int32_t tRC;									/*!< Active to Active Command Period */
+	int32_t tRFC;									/*!< Auto-refresh Period */
+	int32_t tXSR;									/*!< Exit Selt Refresh */
+	int32_t tRRD;									/*!< Active Bank A to Active Bank B Time */
+	int32_t tMRD;									/*!< Load Mode register command to Active Command */
+	IP_EMC_DYN_DEVICE_CONFIG_Type DevConfig[4];		/*!< Device Configuration array */
+} IP_EMC_DYN_CONFIG_Type;
+
+/**
+ * @brief EMC Static Configure Structure
+ */
+typedef struct {
+	uint8_t ChipSelect;		/*!< Chip select */
+	uint32_t Config;		/*!< Configuration value */
+	int32_t WaitWen;		/*!< Write Enable Wait */
+	int32_t WaitOen;		/*!< Output Enable Wait */
+	int32_t WaitRd;			/*!< Read Wait */
+	int32_t WaitPage;		/*!< Page Access Wait */
+	int32_t WaitWr;			/*!< Write Wait */
+	int32_t WaitTurn;		/*!< Turn around wait */
+} IP_EMC_STATIC_CONFIG_Type;
+
+/**
+ * @brief	Initializes the Dynamic Controller
+ * @param	pEMC			: Pointer to EMC peripheral
+ * @param	Dynamic_Config	: Dynamic Memory Configure Struct
+ * @param	EMC_Clock		: Frequency of EMC Clock Out
+ * @return	None
+ * Initializes the Dynamic Controller according to the specified parameters
+ * in the IP_EMC_DYN_CONFIG_Type
+ */
+void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock);
+
+/**
+ * @brief	Set Deep Sleep Mode for Dynamic Memory Controller
+ * @param	pEMC	: Pointer to EMC peripheral
+ * @param	Enable	: 1 = enter DeepSleep Mode, 0 = Normal Mode
+ * @return	None
+ */
+void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
+
+/**
+ * @brief	Enable Dynamic Memory Controller
+ * @param	pEMC	: Pointer to EMC peripheral
+ * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
+ * @return	None
+ */
+void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable);
+
+/**
+ * @brief	Initializes the Static Controller according to the specified
+ *			parameters in the IP_EMC_STATIC_CONFIG_Type
+ * @param	pEMC			: Pointer to EMC peripheral
+ * @param	Static_Config	: Static Memory Configure Struct
+ * @param	EMC_Clock		: Frequency of EMC Clock Out
+ * @return	None
+ */
+void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock);
+
+/**
+ * @brief	Mirror CS1 to CS0 and DYCS0
+ * @param	pEMC	: Pointer to EMC peripheral
+ * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
+ * @return	None
+ */
+void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable);
+
+/**
+ * @brief	Enable EMC
+ * @param	pEMC	: Pointer to EMC peripheral
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable);
+
+/**
+ * @brief	Set EMC LowPower Mode
+ * @param	pEMC	: Pointer to EMC peripheral
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
+
+/**
+ * @brief	Initialize EMC
+ * @param	pEMC		: Pointer to EMC peripheral
+ * @param	Enable		: 1 = Enable, 0 = Disable
+ * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
+ * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
+ * @return	None
+ */
+void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
+
+/**
+ * @brief	Set Static Memory Extended Wait in Clock
+ * @param	pEMC		: Pointer to EMC peripheral
+ * @param	Wait16Clks	: Number of '16 clock' delay cycles
+ * @return	None
+ */
+void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMC_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/enet_001.c

@@ -0,0 +1,204 @@
+/*
+ * @brief Ethernet control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "enet_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Saved address for PHY and clock divider */
+STATIC uint32_t phyCfg;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Resets ethernet interface */
+void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET)
+{
+	/* This should be called prior to IP_ENET_Init. The MAC controller may
+	   not be ready for a call to init right away so a small delay should
+	   occur after this call. */
+	LPC_ENET->DMA_BUS_MODE |= DMA_BM_SWR;
+}
+
+/* Sets the address of the interface */
+void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr)
+{
+	/* Save MAC address */
+	LPC_ENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) |
+							  ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) |
+							  ((uint32_t) macAddr[0]);
+	LPC_ENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) |
+							   ((uint32_t) macAddr[4]);
+}
+
+/* Initialize ethernet interface */
+void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET)
+{
+	/* Enhanced descriptors, burst length = 1 */
+	LPC_ENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1);
+
+	/* Initial MAC configuration for checksum offload, full duplex,
+	   100Mbps, disable receive own in half duplex, inter-frame gap
+	   of 64-bits */
+	LPC_ENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |
+						   MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3);
+
+	/* Setup default filter */
+	LPC_ENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA;
+
+	/* Flush transmit FIFO */
+	LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
+
+	/* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
+	   64 bytes */
+	LPC_ENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);
+
+	/* Clear all MAC interrupts */
+	LPC_ENET->DMA_STAT = DMA_ST_ALL;
+
+	/* Enable MAC interrupts */
+	LPC_ENET->DMA_INT_EN = 0;
+}
+
+/* Sets up the PHY link clock divider and PHY address */
+void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr)
+{
+	/* Save clock divider and PHY address in MII address register */
+	phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
+}
+
+/*De-initialize the ethernet interface */
+void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET)
+{
+	/* Disable packet reception */
+	LPC_ENET->MAC_CONFIG = 0;
+
+	/* Flush transmit FIFO */
+	LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
+
+	/* Disable receive and transmit DMA processes */
+	LPC_ENET->DMA_OP_MODE = 0;
+}
+
+/* Starts a PHY write via the MII */
+void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data)
+{
+	/* Write value at PHY address and register */
+	LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
+	LPC_ENET->MAC_MII_DATA = (uint32_t) data;
+	LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
+}
+
+/*Starts a PHY read via the MII */
+void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg)
+{
+	/* Read value at PHY address and register */
+	LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
+	LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
+}
+
+/* Returns MII link (PHY) busy status */
+bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET)
+{
+	if (LPC_ENET->MAC_MII_ADDR & MAC_MIIA_GB) {
+		return true;
+	}
+
+	return false;
+}
+
+/* Enables or disables ethernet transmit */
+void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
+{
+	if (Enable) {
+		/* Descriptor list head pointers must be setup prior to enable */
+		LPC_ENET->MAC_CONFIG |= MAC_CFG_TE;
+		LPC_ENET->DMA_OP_MODE |= DMA_OM_ST;
+	}
+	else {
+		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_TE;
+	}
+}
+
+/* Enables or disables ethernet packet reception */
+void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
+{
+	if (Enable) {
+		/* Descriptor list head pointers must be setup prior to enable */
+		LPC_ENET->MAC_CONFIG |= MAC_CFG_RE;
+		LPC_ENET->DMA_OP_MODE |= DMA_OM_SR;
+	}
+	else {
+		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_RE;
+	}
+}
+
+/* Sets full or half duplex for the interface */
+void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full)
+{
+	if (full) {
+		LPC_ENET->MAC_CONFIG |= MAC_CFG_DM;
+	}
+	else {
+		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_DM;
+	}
+}
+
+/* Sets speed for the interface */
+void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100)
+{
+	if (speed100) {
+		LPC_ENET->MAC_CONFIG |= MAC_CFG_FES;
+	}
+	else {
+		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_FES;
+	}
+}
+
+/* Configures the initial ethernet descriptors */
+void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET,
+							 IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs)
+{
+	/* Setup descriptor list base addresses */
+	LPC_ENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs;
+	LPC_ENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs;
+}

bsp/xplorer4330/libraries/lpc_ip/enet_001.h

@@ -0,0 +1,608 @@
+/*
+ * @brief Ethernet control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ENET_001_H_
+#define __ENET_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_ENET_001 IP: Ethernet register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief 10/100 MII & RMII Ethernet with timestamping register block structure
+ */
+typedef struct {							/*!< ETHERNET Structure */
+	__IO uint32_t  MAC_CONFIG;				/*!< MAC configuration register */
+	__IO uint32_t  MAC_FRAME_FILTER;		/*!< MAC frame filter */
+	__IO uint32_t  MAC_HASHTABLE_HIGH;		/*!< Hash table high register */
+	__IO uint32_t  MAC_HASHTABLE_LOW;		/*!< Hash table low register */
+	__IO uint32_t  MAC_MII_ADDR;			/*!< MII address register */
+	__IO uint32_t  MAC_MII_DATA;			/*!< MII data register */
+	__IO uint32_t  MAC_FLOW_CTRL;			/*!< Flow control register */
+	__IO uint32_t  MAC_VLAN_TAG;			/*!< VLAN tag register */
+	__I  uint32_t  RESERVED0;
+	__I  uint32_t  MAC_DEBUG;				/*!< Debug register */
+	__IO uint32_t  MAC_RWAKE_FRFLT;			/*!< Remote wake-up frame filter */
+	__IO uint32_t  MAC_PMT_CTRL_STAT;		/*!< PMT control and status */
+	__I  uint32_t  RESERVED1[2];
+	__I  uint32_t  MAC_INTR;				/*!< Interrupt status register */
+	__IO uint32_t  MAC_INTR_MASK;			/*!< Interrupt mask register */
+	__IO uint32_t  MAC_ADDR0_HIGH;			/*!< MAC address 0 high register */
+	__IO uint32_t  MAC_ADDR0_LOW;			/*!< MAC address 0 low register */
+	__I  uint32_t  RESERVED2[430];
+	__IO uint32_t  MAC_TIMESTP_CTRL;		/*!< Time stamp control register */
+	__IO uint32_t  SUBSECOND_INCR;			/*!< Sub-second increment register */
+	__I  uint32_t  SECONDS;					/*!< System time seconds register */
+	__I  uint32_t  NANOSECONDS;				/*!< System time nanoseconds register */
+	__IO uint32_t  SECONDSUPDATE;			/*!< System time seconds update register */
+	__IO uint32_t  NANOSECONDSUPDATE;		/*!< System time nanoseconds update register */
+	__IO uint32_t  ADDEND;					/*!< Time stamp addend register */
+	__IO uint32_t  TARGETSECONDS;			/*!< Target time seconds register */
+	__IO uint32_t  TARGETNANOSECONDS;		/*!< Target time nanoseconds register */
+	__IO uint32_t  HIGHWORD;				/*!< System time higher word seconds register */
+	__I  uint32_t  TIMESTAMPSTAT;			/*!< Time stamp status register */
+	__IO uint32_t  PPSCTRL;					/*!< PPS control register */
+	__I  uint32_t  AUXNANOSECONDS;			/*!< Auxiliary time stamp nanoseconds register */
+	__I  uint32_t  AUXSECONDS;				/*!< Auxiliary time stamp seconds register */
+	__I  uint32_t  RESERVED3[562];
+	__IO uint32_t  DMA_BUS_MODE;			/*!< Bus Mode Register      */
+	__IO uint32_t  DMA_TRANS_POLL_DEMAND;	/*!< Transmit poll demand register */
+	__IO uint32_t  DMA_REC_POLL_DEMAND;		/*!< Receive poll demand register */
+	__IO uint32_t  DMA_REC_DES_ADDR;		/*!< Receive descriptor list address register */
+	__IO uint32_t  DMA_TRANS_DES_ADDR;		/*!< Transmit descriptor list address register */
+	__IO uint32_t  DMA_STAT;				/*!< Status register */
+	__IO uint32_t  DMA_OP_MODE;				/*!< Operation mode register */
+	__IO uint32_t  DMA_INT_EN;				/*!< Interrupt enable register */
+	__I  uint32_t  DMA_MFRM_BUFOF;			/*!< Missed frame and buffer overflow register */
+	__IO uint32_t  DMA_REC_INT_WDT;			/*!< Receive interrupt watchdog timer register */
+	__I  uint32_t  RESERVED4[8];
+	__I  uint32_t  DMA_CURHOST_TRANS_DES;	/*!< Current host transmit descriptor register */
+	__I  uint32_t  DMA_CURHOST_REC_DES;		/*!< Current host receive descriptor register */
+	__I  uint32_t  DMA_CURHOST_TRANS_BUF;	/*!< Current host transmit buffer address register */
+	__I  uint32_t  DMA_CURHOST_REC_BUF;		/*!< Current host receive buffer address register */
+} IP_ENET_001_Type;
+
+/**
+ * @brief MAC_CONFIG register bit defines
+ */
+#define MAC_CFG_RE     (1 << 2)		/*!< Receiver enable */
+#define MAC_CFG_TE     (1 << 3)		/*!< Transmitter Enable */
+#define MAC_CFG_DF     (1 << 4)		/*!< Deferral Check */
+#define MAC_CFG_BL(n)  ((n) << 5)	/*!< Back-Off Limit */
+#define MAC_CFG_ACS    (1 << 7)		/*!< Automatic Pad/CRC Stripping */
+#define MAC_CFG_LUD    (1 << 8)		/*!< Link Up/Down, 1 = up */
+#define MAC_CFG_DR     (1 << 9)		/*!< Disable Retry */
+#define MAC_CFG_IPC    (1 << 10)	/*!< Checksum Offload */
+#define MAC_CFG_DM     (1 << 11)	/*!< Duplex Mode, 1 = full, 0 = half */
+#define MAC_CFG_LM     (1 << 12)	/*!< Loopback Mode */
+#define MAC_CFG_DO     (1 << 13)	/*!< Disable Receive Own */
+#define MAC_CFG_FES    (1 << 14)	/*!< Speed, 1 = 100Mbps, 0 = 10Mbos */
+#define MAC_CFG_PS     (1 << 15)	/*!< Port select, must always be 1 */
+#define MAC_CFG_DCRS   (1 << 16)	/*!< Disable carrier sense during transmission */
+#define MAC_CFG_IFG(n) ((n) << 17)	/*!< Inter-frame gap, 40..96, n incs by 8 */
+#define MAC_CFG_JE     (1 << 20)	/*!< Jumbo Frame Enable */
+#define MAC_CFG_JD     (1 << 22)	/*!< Jabber Disable */
+#define MAC_CFG_WD     (1 << 23)	/*!< Watchdog Disable */
+
+/**
+ * @brief MAC_FRAME_FILTER register bit defines
+ */
+#define MAC_FF_PR      (1 << 0)		/*!< Promiscuous Mode */
+#define MAC_FF_DAIF    (1 << 3)		/*!< DA Inverse Filtering */
+#define MAC_FF_PM      (1 << 4)		/*!< Pass All Multicast */
+#define MAC_FF_DBF     (1 << 5)		/*!< Disable Broadcast Frames */
+#define MAC_FF_PCF(n)  ((n) << 6)	/*!< Pass Control Frames, n = see user manual */
+#define MAC_FF_SAIF    (1 << 8)		/*!< SA Inverse Filtering */
+#define MAC_FF_SAF     (1 << 9)		/*!< Source Address Filter Enable */
+#define MAC_FF_RA      (1UL << 31)	/*!< Receive all */
+
+/**
+ * @brief MAC_MII_ADDR register bit defines
+ */
+#define MAC_MIIA_GB    (1 << 0)		/*!< MII busy */
+#define MAC_MIIA_W     (1 << 1)		/*!< MII write */
+#define MAC_MIIA_CR(n) ((n) << 2)	/*!< CSR clock range, n = see manual */
+#define MAC_MIIA_GR(n) ((n) << 6)	/*!< MII register. n = 0..31 */
+#define MAC_MIIA_PA(n) ((n) << 11)	/*!< Physical layer address, n = 0..31 */
+
+/**
+ * @brief MAC_MII_DATA register bit defines
+ */
+#define MAC_MIID_GDMSK (0xFFFF)		/*!< MII data mask */
+
+/**
+ * @brief MAC_FLOW_CONTROL register bit defines
+ */
+#define MAC_FC_FCB     (1 << 0)		/*!< Flow Control Busy/Backpressure Activate */
+#define MAC_FC_TFE     (1 << 1)		/*!< Transmit Flow Control Enable */
+#define MAC_FC_RFE     (1 << 2)		/*!< Receive Flow Control Enable */
+#define MAC_FC_UP      (1 << 3)		/*!< Unicast Pause Frame Detect */
+#define MAC_FC_PLT(n)  ((n) << 4)	/*!< Pause Low Threshold, n = see manual */
+#define MAC_FC_DZPQ    (1 << 7)		/*!< Disable Zero-Quanta Pause */
+#define MAC_FC_PT(n)   ((n) << 16)	/*!< Pause time */
+
+/**
+ * @brief MAC_VLAN_TAG register bit defines
+ */
+#define MAC_VT_VL(n)   ((n) << 0)	/*!< VLAN Tag Identifier for Receive Frames */
+#define MAC_VT_ETC     (1 << 7)		/*!< Enable 12-Bit VLAN Tag Comparison */
+
+/**
+ * @brief MAC_PMT_CTRL_STAT register bit defines
+ */
+#define MAC_PMT_PD     (1 << 0)		/*!< Power-down */
+#define MAC_PMT_MPE    (1 << 1)		/*!< Magic packet enable */
+#define MAC_PMT_WFE    (1 << 2)		/*!< Wake-up frame enable */
+#define MAC_PMT_MPR    (1 << 5)		/*!< Magic Packet Received */
+#define MAC_PMT_WFR    (1 << 6)		/*!< Wake-up Frame Received */
+#define MAC_PMT_GU     (1 << 9)		/*!< Global Unicast */
+#define MAC_PMT_WFFRPR (1UL << 31)	/*!< Wake-up Frame Filter Register Pointer Reset */
+
+/**
+ * @brief MAC_INTR_MASK register bit defines
+ */
+#define MAC_IM_PMT     (1 << 3)		/*!< PMT Interrupt Mask */
+
+/**
+ * @brief MAC_ADDR0_HIGH register bit defines
+ */
+#define MAC_ADRH_MO    (1UL << 31)	/*!< Always 1 when writing register */
+
+/**
+ * @brief MAC_ADDR0_HIGH register bit defines
+ */
+#define MAC_ADRH_MO    (1UL << 31)	/*!< Always 1 when writing register */
+
+/**
+ * @brief MAC_TIMESTAMP register bit defines
+ */
+#define MAC_TS_TSENA   (1 << 0)		/*!< Time Stamp Enable */
+#define MAC_TS_TSCFUP  (1 << 1)		/*!< Time Stamp Fine or Coarse Update */
+#define MAC_TS_TSINIT  (1 << 2)		/*!< Time Stamp Initialize */
+#define MAC_TS_TSUPDT  (1 << 3)		/*!< Time Stamp Update */
+#define MAC_TS_TSTRIG  (1 << 4)		/*!< Time Stamp Interrupt Trigger Enable */
+#define MAC_TS_TSADDR  (1 << 5)		/*!< Addend Reg Update */
+#define MAC_TS_TSENAL  (1 << 8)		/*!< Enable Time Stamp for All Frames */
+#define MAC_TS_TSCTRL  (1 << 9)		/*!< Time Stamp Digital or Binary rollover control */
+#define MAC_TS_TSVER2  (1 << 10)	/*!< Enable PTP packet snooping for version 2 format */
+#define MAC_TS_TSIPENA (1 << 11)	/*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */
+#define MAC_TS_TSIPV6E (1 << 12)	/*!< Enable Time Stamp Snapshot for IPv6 frames */
+#define MAC_TS_TSIPV4E (1 << 13)	/*!< Enable Time Stamp Snapshot for IPv4 frames */
+#define MAC_TS_TSEVNT  (1 << 14)	/*!< Enable Time Stamp Snapshot for Event Messages */
+#define MAC_TS_TSMSTR  (1 << 15)	/*!< Enable Snapshot for Messages Relevant to Master */
+#define MAC_TS_TSCLKT(n) ((n) << 16)	/*!< Select the type of clock node, n = see menual */
+#define MAC_TS_TSENMA  (1 << 18)	/*!< Enable MAC address for PTP frame filtering */
+
+/**
+ * @brief DMA_BUS_MODE register bit defines
+ */
+#define DMA_BM_SWR     (1 << 0)		/*!< Software reset */
+#define DMA_BM_DA      (1 << 1)		/*!< DMA arbitration scheme, 1 = TX has priority over TX */
+#define DMA_BM_DSL(n)  ((n) << 2)	/*!< Descriptor skip length, n = see manual */
+#define DMA_BM_ATDS    (1 << 7)		/*!< Alternate (Enhanced) descriptor size */
+#define DMA_BM_PBL(n)  ((n) << 8)	/*!< Programmable burst length, n = see manual */
+#define DMA_BM_PR(n)   ((n) << 14)	/*!< Rx-to-Tx priority ratio, n = see manual */
+#define DMA_BM_FB      (1 << 16)	/*!< Fixed burst */
+#define DMA_BM_RPBL(n) ((n) << 17)	/*!< RxDMA PBL, n = see manual */
+#define DMA_BM_USP     (1 << 23)	/*!< Use separate PBL */
+#define DMA_BM_PBL8X   (1 << 24)	/*!< 8 x PBL mode */
+#define DMA_BM_AAL     (1 << 25)	/*!< Address-aligned beats */
+#define DMA_BM_MB      (1 << 26)	/*!< Mixed burst */
+#define DMA_BM_TXPR    (1 << 27)	/*!< Transmit DMA has higher priority than receive DMA */
+
+/**
+ * @brief DMA_STAT register bit defines
+ */
+#define DMA_ST_TI      (1 << 0)		/*!< Transmit interrupt */
+#define DMA_ST_TPS     (1 << 1)		/*!< Transmit process stopped */
+#define DMA_ST_TU      (1 << 2)		/*!< Transmit buffer unavailable */
+#define DMA_ST_TJT     (1 << 3)		/*!< Transmit jabber timeout */
+#define DMA_ST_OVF     (1 << 4)		/*!< Receive overflow */
+#define DMA_ST_UNF     (1 << 5)		/*!< Transmit underflow */
+#define DMA_ST_RI      (1 << 6)		/*!< Receive interrupt */
+#define DMA_ST_RU      (1 << 7)		/*!< Receive buffer unavailable */
+#define DMA_ST_RPS     (1 << 8)		/*!< Received process stopped */
+#define DMA_ST_RWT     (1 << 9)		/*!< Receive watchdog timeout */
+#define DMA_ST_ETI     (1 << 10)	/*!< Early transmit interrupt */
+#define DMA_ST_FBI     (1 << 13)	/*!< Fatal bus error interrupt */
+#define DMA_ST_ERI     (1 << 14)	/*!< Early receive interrupt */
+#define DMA_ST_AIE     (1 << 15)	/*!< Abnormal interrupt summary */
+#define DMA_ST_NIS     (1 << 16)	/*!< Normal interrupt summary */
+#define DMA_ST_ALL     (0x1E7FF)	/*!< All interrupts */
+
+/**
+ * @brief DMA_OP_MODE register bit defines
+ */
+#define DMA_OM_SR      (1 << 1)		/*!< Start/stop receive */
+#define DMA_OM_OSF     (1 << 2)		/*!< Operate on second frame */
+#define DMA_OM_RTC(n)  ((n) << 3)	/*!< Receive threshold control, n = see manual */
+#define DMA_OM_FUF     (1 << 6)		/*!< Forward undersized good frames */
+#define DMA_OM_FEF     (1 << 7)		/*!< Forward error frames */
+#define DMA_OM_ST      (1 << 13)	/*!< Start/Stop Transmission Command */
+#define DMA_OM_TTC(n)  ((n) << 14)	/*!< Transmit threshold control, n = see manual */
+#define DMA_OM_FTF     (1 << 20)	/*!< Flush transmit FIFO */
+#define DMA_OM_TSF     (1 << 21)	/*!< Transmit store and forward */
+#define DMA_OM_DFF     (1 << 24)	/*!< Disable flushing of received frames */
+#define DMA_OM_RSF     (1 << 25)	/*!< Receive store and forward */
+#define DMA_OM_DT      (1 << 26)	/*!< Disable Dropping of TCP/IP Checksum Error Frames */
+
+/**
+ * @brief DMA_INT_EN register bit defines
+ */
+#define DMA_IE_TIE     (1 << 0)		/*!< Transmit interrupt enable */
+#define DMA_IE_TSE     (1 << 1)		/*!< Transmit stopped enable */
+#define DMA_IE_TUE     (1 << 2)		/*!< Transmit buffer unavailable enable */
+#define DMA_IE_TJE     (1 << 3)		/*!< Transmit jabber timeout enable */
+#define DMA_IE_OVE     (1 << 4)		/*!< Overflow interrupt enable */
+#define DMA_IE_UNE     (1 << 5)		/*!< Underflow interrupt enable */
+#define DMA_IE_RIE     (1 << 6)		/*!< Receive interrupt enable */
+#define DMA_IE_RUE     (1 << 7)		/*!< Receive buffer unavailable enable */
+#define DMA_IE_RSE     (1 << 8)		/*!< Received stopped enable */
+#define DMA_IE_RWE     (1 << 9)		/*!< Receive watchdog timeout enable */
+#define DMA_IE_ETE     (1 << 10)	/*!< Early transmit interrupt enable */
+#define DMA_IE_FBE     (1 << 13)	/*!< Fatal bus error enable */
+#define DMA_IE_ERE     (1 << 14)	/*!< Early receive interrupt enable */
+#define DMA_IE_AIE     (1 << 15)	/*!< Abnormal interrupt summary enable */
+#define DMA_IE_NIE     (1 << 16)	/*!< Normal interrupt summary enable */
+
+/**
+ * @brief DMA_MFRM_BUFOF register bit defines
+ */
+#define DMA_MFRM_FMCMSK (0xFFFF)	/*!< Number of frames missed mask */
+#define DMA_MFRM_OC    (1 << 16)	/*!< Overflow bit for missed frame counter */
+#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17)	/*!< Number of frames missed by the application mask/shift */
+#define DMA_MFRM_OF    (1 << 28)	/*!< Overflow bit for FIFO overflow counter */
+
+/**
+ * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines
+ */
+#define TDES_DB        (1 << 0)		/*!< Deferred Bit */
+#define TDES_UF        (1 << 1)		/*!< Underflow Error */
+#define TDES_ED        (1 << 2)		/*!< Excessive Deferral */
+#define TDES_CCMSK(n)  (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */
+#define TDES_VF        (1 << 7)		/*!< VLAN Frame */
+#define TDES_EC        (1 << 8)		/*!< Excessive Collision */
+#define TDES_LC        (1 << 9)		/*!< Late Collision */
+#define TDES_NC        (1 << 10)	/*!< No Carrier */
+#define TDES_LCAR      (1 << 11)	/*!< Loss of Carrier */
+#define TDES_IPE       (1 << 12)	/*!< IP Payload Error */
+#define TDES_FF        (1 << 13)	/*!< Frame Flushed */
+#define TDES_JT        (1 << 14)	/*!< Jabber Timeout */
+#define TDES_ES        (1 << 15)	/*!< Error Summary */
+#define TDES_IHE       (1 << 16)	/*!< IP Header Error */
+#define TDES_TTSS      (1 << 17)	/*!< Transmit Timestamp Status */
+#define TDES_OWN       (1UL << 31)	/*!< Own Bit */
+
+/**
+ * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines
+ */
+#define TDES_ENH_IC   (1UL << 30)	/*!< Interrupt on Completion, enhanced descriptor */
+#define TDES_ENH_LS   (1 << 29)		/*!< Last Segment, enhanced descriptor */
+#define TDES_ENH_FS   (1 << 28)		/*!< First Segment, enhanced descriptor */
+#define TDES_ENH_DC   (1 << 27)		/*!< Disable CRC, enhanced descriptor */
+#define TDES_ENH_DP   (1 << 26)		/*!< Disable Pad, enhanced descriptor */
+#define TDES_ENH_TTSE (1 << 25)		/*!< Transmit Timestamp Enable, enhanced descriptor */
+#define TDES_ENH_CIC(n) ((n) << 22)	/*!< Checksum Insertion Control, enhanced descriptor */
+#define TDES_ENH_TER  (1 << 21)		/*!< Transmit End of Ring, enhanced descriptor */
+#define TDES_ENH_TCH  (1 << 20)		/*!< Second Address Chained, enhanced descriptor */
+
+/**
+ * @brief TRAN_DESC_T only BSIZE field bit defines
+ */
+#define TDES_NORM_IC   (1UL << 31)	/*!< Interrupt on Completion, normal descriptor */
+#define TDES_NORM_FS   (1 << 30)	/*!< First Segment, normal descriptor */
+#define TDES_NORM_LS   (1 << 29)	/*!< Last Segment, normal descriptor */
+#define TDES_NORM_CIC(n) ((n) << 27)	/*!< Checksum Insertion Control, normal descriptor */
+#define TDES_NORM_DC   (1 << 26)	/*!< Disable CRC, normal descriptor */
+#define TDES_NORM_TER  (1 << 25)	/*!< Transmit End of Ring, normal descriptor */
+#define TDES_NORM_TCH  (1 << 24)	/*!< Second Address Chained, normal descriptor */
+#define TDES_NORM_DP   (1 << 23)	/*!< Disable Pad, normal descriptor */
+#define TDES_NORM_TTSE (1 << 22)	/*!< Transmit Timestamp Enable, normal descriptor */
+#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11)	/*!< Buffer 2 size, normal descriptor */
+#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0)	/*!< Buffer 1 size, normal descriptor */
+
+/**
+ * @brief TRAN_DESC_ENH_T only BSIZE field bit defines
+ */
+#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16)	/*!< Buffer 2 size, enhanced descriptor */
+#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0)	/*!< Buffer 1 size, enhanced descriptor */
+
+/**
+ * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines
+ */
+#define RDES_ESA      (1 << 0)		/*!< Extended Status Available/Rx MAC Address */
+#define RDES_CE       (1 << 1)		/*!< CRC Error */
+#define RDES_DRE      (1 << 2)		/*!< Dribble Bit Error */
+#define RDES_RE       (1 << 3)		/*!< Receive Error */
+#define RDES_RWT      (1 << 4)		/*!< Receive Watchdog Timeout */
+#define RDES_FT       (1 << 5)		/*!< Frame Type */
+#define RDES_LC       (1 << 6)		/*!< Late Collision */
+#define RDES_TSA      (1 << 7)		/*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */
+#define RDES_LS       (1 << 8)		/*!< Last Descriptor */
+#define RDES_FS       (1 << 9)		/*!< First Descriptor */
+#define RDES_VLAN     (1 << 10)		/*!< VLAN Tag */
+#define RDES_OE       (1 << 11)		/*!< Overflow Error */
+#define RDES_LE       (1 << 12)		/*!< Length Error */
+#define RDES_SAF      (1 << 13)		/*!< Source Address Filter Fail */
+#define RDES_DE       (1 << 14)		/*!< Descriptor Error */
+#define RDES_ES       (1 << 15)		/*!< ES: Error Summary */
+#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */
+#define RDES_AFM      (1 << 30)		/*!< Destination Address Filter Fail */
+#define RDES_OWN      (1UL << 31)	/*!< Own Bit */
+
+/**
+ * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines
+ */
+#define RDES_DINT     (1UL << 31)	/*!< Disable interrupt on completion */
+
+/**
+ * @brief REC_DESC_T pnly CTRL field bit defines
+ */
+#define RDES_NORM_RER (1 << 25)		/*!< Receive End of Ring, normal descriptor */
+#define RDES_NORM_RCH (1 << 24)		/*!< Second Address Chained, normal descriptor */
+#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11)	/*!< Buffer 2 size, normal descriptor */
+#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0)	/*!< Buffer 1 size, normal descriptor */
+
+/**
+ * @brief REC_DESC_ENH_T only CTRL field bit defines
+ */
+#define RDES_ENH_RER  (1 << 15)		/*!< Receive End of Ring, enhanced descriptor */
+#define RDES_ENH_RCH  (1 << 14)		/*!< Second Address Chained, enhanced descriptor */
+#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16)	/*!< Buffer 2 size, enhanced descriptor */
+#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0)	/*!< Buffer 1 size, enhanced descriptor */
+
+/**
+ * @brief REC_DESC_ENH_T only EXTSTAT field bit defines
+ */
+#define RDES_ENH_IPPL(n)  (((n) & 0x7) >> 2)	/*!< IP Payload Type mask and shift, enhanced descripto */
+#define RDES_ENH_IPHE     (1 << 3)	/*!< IP Header Error, enhanced descripto */
+#define RDES_ENH_IPPLE    (1 << 4)	/*!< IP Payload Error, enhanced descripto */
+#define RDES_ENH_IPCSB    (1 << 5)	/*!< IP Checksum Bypassed, enhanced descripto */
+#define RDES_ENH_IPV4     (1 << 6)	/*!< IPv4 Packet Received, enhanced descripto */
+#define RDES_ENH_IPV6     (1 << 7)	/*!< IPv6 Packet Received, enhanced descripto */
+#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8)	/*!< Message Type mask and shift, enhanced descripto */
+
+/**
+ * @brief Maximum size of an ethernet buffer
+ */
+#define EMAC_ETH_MAX_FLEN (1536)
+
+/**
+ * @brief Structure of a transmit descriptor (without timestamp)
+ */
+typedef struct {
+	__IO uint32_t CTRLSTAT;		/*!< TDES control and status word */
+	__IO uint32_t BSIZE;		/*!< Buffer 1/2 byte counts */
+	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
+	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
+} IP_ENET_001_TXDESC_Type;
+
+/**
+ * @brief Structure of a enhanced transmit descriptor (with timestamp)
+ */
+typedef struct {
+	__IO uint32_t CTRLSTAT;		/*!< TDES control and status word */
+	__IO uint32_t BSIZE;		/*!< Buffer 1/2 byte counts */
+	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
+	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
+	__IO uint32_t TDES4;		/*!< Reserved */
+	__IO uint32_t TDES5;		/*!< Reserved */
+	__IO uint32_t TTSL;			/*!< Timestamp value low */
+	__IO uint32_t TTSH;			/*!< Timestamp value high */
+} IP_ENET_001_ENHTXDESC_Type;
+
+/**
+ * @brief Structure of a receive descriptor (without timestamp)
+ */
+typedef struct {
+	__IO uint32_t STATUS;		/*!< RDES status word */
+	__IO uint32_t CTRL;			/*!< Buffer 1/2 byte counts and control */
+	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
+	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
+} IP_ENET_001_RXDESC_Type;
+
+/**
+ * @brief Structure of a enhanced receive descriptor (with timestamp)
+ */
+typedef struct {
+	__IO uint32_t STATUS;		/*!< RDES status word */
+	__IO uint32_t CTRL;			/*!< Buffer 1/2 byte counts */
+	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
+	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
+	__IO uint32_t EXTSTAT;		/*!< Extended Status */
+	__IO uint32_t RDES5;		/*!< Reserved */
+	__IO uint32_t RTSL;			/*!< Timestamp value low */
+	__IO uint32_t RTSH;			/*!< Timestamp value high */
+} IP_ENET_001_ENHRXDESC_Type;
+
+/**
+ * @brief	Resets the ethernet interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Nothing
+ * Resets the ethernet interface. This should be called prior to
+ * IP_ENET_Init with a small delay after this call.
+ */
+void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET);
+
+/**
+ * @brief	Sets the address of the interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	macAddr		: Pointer to the 6 bytes used for the MAC address
+ * @return	Nothing
+ */
+void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr);
+
+/**
+ * @brief	Initialize ethernet interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Nothing
+ * Performs basic initialization of the ethernet interface in a default
+ * state. This is enough to place the interface in a usable state, but
+ * may require more setup outside this function.
+ */
+void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET);
+
+/**
+ * @brief	Sets up the PHY link clock divider and PHY address
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	div			: Divider value, may vary per chip
+ * @param	addr		: PHY address, used with MII read and write
+ * @return	Nothing
+ */
+void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr);
+
+/**
+ * @brief	De-initialize the ethernet interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Nothing
+ */
+void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET);
+
+/**
+ * @brief	Starts a PHY write via the MII
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	reg			: PHY register to write
+ * @param	data		: Data to write to PHY register
+ * @return	Nothing
+ * Start a PHY write operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when write is complete.
+ */
+void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data);
+
+/**
+ * @brief	Starts a PHY read via the MII
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	reg			: PHY register to read
+ * @return	Nothing
+ * Start a PHY read operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when read is complete and calling
+ * IP_ENET_ReadMIIData to get the data.
+ */
+void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg);
+
+/**
+ * @brief	Returns MII link (PHY) busy status
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Returns true if busy, otherwise false
+ */
+bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET);
+
+/**
+ * @brief	Returns the value read from the PHY
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Read value from PHY
+ */
+STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_Type *LPC_ENET)
+{
+	return LPC_ENET->MAC_MII_DATA;
+}
+
+/**
+ * @brief	Enables or disables ethernet transmit
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	Enable		: true to enable transmit, false to disable
+ * @return	Nothing
+ */
+void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable);
+
+/**
+ * @brief	Enables or disables ethernet packet reception
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	Enable		: true to enable receive, false to disable
+ * @return	Nothing
+ */
+void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable);
+
+/**
+ * @brief	Sets full or half duplex for the interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	full		: true to selected full duplex, false for half
+ * @return	Nothing
+ */
+void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full);
+
+/**
+ * @brief	Sets speed for the interface
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	speed100	: true to select 100Mbps mode, false for 10Mbps
+ * @return	Nothing
+ */
+void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100);
+
+/**
+ * @brief	Configures the initial ethernet descriptors
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @param	pTXDescs	: Pointer to TX descriptor list
+ * @param	pRXDescs	: Pointer to RX descriptor list
+ * @return	Nothing
+ */
+void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET,
+							 IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs);
+
+/**
+ * @brief	Starts receive polling of RX descriptors
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_Type *LPC_ENET)
+{
+	/* Start receive polling */
+	LPC_ENET->DMA_REC_POLL_DEMAND = 1;
+}
+
+/**
+ * @brief	Starts transmit polling of TX descriptors
+ * @param	LPC_ENET	: Pointer to selected ENET peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_Type *LPC_ENET)
+{
+	/* Start transmit polling */
+	LPC_ENET->DMA_TRANS_POLL_DEMAND = 1;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ENET_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/fpu_init.c

@@ -0,0 +1,94 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#if defined(CORE_M4)
+
+#include "stdint.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define LPC_CPACR           0xE000ED88
+
+#define SCB_MVFR0           0xE000EF40
+#define SCB_MVFR0_RESET     0x10110021
+
+#define SCB_MVFR1           0xE000EF44
+#define SCB_MVFR1_RESET     0x11000011
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Early initialization of the FPU */
+void fpuInit(void)
+{
+	// from arm trm manual:
+	//                ; CPACR is located at address 0xE000ED88
+	//                LDR.W R0, =0xE000ED88
+	//                ; Read CPACR
+	//                LDR R1, [R0]
+	//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+	//                ORR R1, R1, #(0xF << 20)
+	//                ; Write back the modified value to the CPACR
+	//                STR R1, [R0]
+
+	volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+	volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+	volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+	volatile uint32_t Cpacr;
+	volatile uint32_t Mvfr0;
+	volatile uint32_t Mvfr1;
+	char vfpPresent = 0;
+
+	Mvfr0 = *regMvfr0;
+	Mvfr1 = *regMvfr1;
+
+	vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+	if (vfpPresent) {
+		Cpacr = *regCpacr;
+		Cpacr |= (0xF << 20);
+		*regCpacr = Cpacr;	// enable CP10 and CP11 for full access
+	}
+
+}
+
+#endif /* defined(CORE_M4 */

bsp/xplorer4330/libraries/lpc_ip/fpu_init.h

@@ -0,0 +1,56 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FPU_INIT_H_
+#define __FPU_INIT_H_
+
+#if defined(CORE_M4)
+
+/**
+ * @defgroup IP_FPU_CMX_001 IP: FPU initialization
+ * @ingroup IP_Drivers
+ * Cortex FPU initialization
+ * @{
+ */
+
+/**
+ * @brief	Early initialization of the FPU
+ * @return	Nothing
+ */
+void fpuInit(void);
+
+/**
+ * @}
+ */
+
+#endif /* #if defined */
+
+#endif /* __FPU_INIT_H_ */