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@@ -1,3 +1,55 @@
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+/**
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+ ******************************************************************************
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+ * @file GPIO/IOToggle/system_air32f10x.c
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+ * @author MCD Application Team
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+ * @version V3.5.0
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+ * @date 08-April-2011
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+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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+ *
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+ * 1. This file provides two functions and one global variable to be called from
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+ * user application:
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+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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+ * factors, AHB/APBx prescalers and Flash settings).
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+ * This function is called at startup just after reset and
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+ * before branch to main program. This call is made inside
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+ * the "startup_air32f10x_xx.s" file.
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+ *
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+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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+ * by the user application to setup the SysTick
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+ * timer or configure other parameters.
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+ *
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+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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+ * be called whenever the core clock is changed
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+ * during program execution.
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+ *
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+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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+ * Then SystemInit() function is called, in "startup_air32f10x_xx.s" file, to
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+ * configure the system clock before to branch to main program.
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+ *
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+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
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+ * function will do nothing and HSI still used as system clock source. User can
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+ * add some code to deal with this issue inside the SetSysClock() function.
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+ *
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+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
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+ * the product used), refer to "HSE_VALUE" define in "air32f10x.h" file.
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+ * When HSE is used as system clock source, directly or through PLL, and you
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+ * are using different crystal you have to adapt the HSE value to your own
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+ * configuration.
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+ *
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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+ *
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+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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+ ******************************************************************************
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+ */
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+
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/** @addtogroup CMSIS
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* @{
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*/
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@@ -6,15 +58,69 @@
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* @{
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*/
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+/** @addtogroup air32f10x_System_Private_Includes
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+ * @{
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+ */
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#include "air32f10x.h"
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-//#define SYSCLK_FREQ_HSE HSE_VALUE
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-//#define SYSCLK_FREQ_24MHz 24000000
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-//#define SYSCLK_FREQ_36MHz 36000000
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-//#define SYSCLK_FREQ_48MHz 48000000
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-//#define SYSCLK_FREQ_56MHz 56000000
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup air32f10x_System_Private_TypesDefinitions
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+ * @{
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+ */
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup air32f10x_System_Private_Defines
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+ * @{
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+ */
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+
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+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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+ frequency (after reset the HSI is used as SYSCLK source)
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+
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+ IMPORTANT NOTE:
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+ ==============
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+ 1. After each device reset the HSI is used as System clock source.
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+
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+ 2. Please make sure that the selected System clock doesn't exceed your device's
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+ maximum frequency.
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+
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+ 3. If none of the define below is enabled, the HSI is used as System clock
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+ source.
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+
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+ 4. The System clock configuration functions provided within this file assume that:
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+ - For Low, Medium and High density Value line devices an external 8MHz
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+ crystal is used to drive the System clock.
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+ - For Low, Medium and High density devices an external 8MHz crystal is
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+ used to drive the System clock.
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+ - For Connectivity line devices an external 25MHz crystal is used to drive
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+ the System clock.
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+ If you are using different crystal you have to adapt those functions accordingly.
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+ */
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+
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+#if defined (air32f10x_LD_VL) || (defined air32f10x_MD_VL) || (defined air32f10x_HD_VL)
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+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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+ #define SYSCLK_FREQ_24MHz 24000000
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+#else
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+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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+/* #define SYSCLK_FREQ_24MHz 24000000 */
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+/* #define SYSCLK_FREQ_36MHz 36000000 */
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+/* #define SYSCLK_FREQ_48MHz 48000000 */
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+/* #define SYSCLK_FREQ_56MHz 56000000 */
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#define SYSCLK_FREQ_72MHz 72000000
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+#endif
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+
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+/*!< Uncomment the following line if you need to use external SRAM mounted
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+ on air3210E-EVAL board (air32 High density and XL-density devices) or on
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+ air32100E-EVAL board (air32 High-density value line devices) as data memory */
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+#if defined (air32f10x_HD) || (defined air32f10x_XL) || (defined air32f10x_HD_VL)
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+/* #define DATA_IN_ExtSRAM */
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+#endif
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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@@ -110,7 +216,11 @@ void SystemInit (void)
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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+#ifndef air32f10x_CL
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RCC->CFGR &= (uint32_t)0xF8FF0000;
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+#else
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+ RCC->CFGR &= (uint32_t)0xF0FF0000;
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+#endif /* air32f10x_CL */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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@@ -121,9 +231,32 @@ void SystemInit (void)
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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+#ifdef air32f10x_CL
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+ /* Reset PLL2ON and PLL3ON bits */
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+ RCC->CR &= (uint32_t)0xEBFFFFFF;
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+
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+ /* Disable all interrupts and clear pending bits */
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+ RCC->CIR = 0x00FF0000;
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+
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+ /* Reset CFGR2 register */
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+ RCC->CFGR2 = 0x00000000;
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+#elif defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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+ /* Reset CFGR2 register */
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+ RCC->CFGR2 = 0x00000000;
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+#else
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+ /* Disable all interrupts and clear pending bits */
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+ RCC->CIR = 0x009F0000;
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+#endif /* air32f10x_CL */
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+
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+#if defined (air32f10x_HD) || (defined air32f10x_XL) || (defined air32f10x_HD_VL)
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+ #ifdef DATA_IN_ExtSRAM
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+ SystemInit_ExtMemCtl();
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+ #endif /* DATA_IN_ExtSRAM */
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+#endif
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+
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/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/* Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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@@ -174,6 +307,14 @@ void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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+#ifdef air32f10x_CL
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+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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+#endif /* air32f10x_CL */
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+
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+#if defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
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+ uint32_t prediv1factor = 0;
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+#endif /* air32f10x_LD_VL or air32f10x_MD_VL or air32f10x_HD_VL */
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+
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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@@ -191,6 +332,7 @@ void SystemCoreClockUpdate (void)
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pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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+#ifndef air32f10x_CL
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pllmull = ( pllmull >> 18) + 2;
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if (pllsource == 0x00)
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@@ -200,6 +342,11 @@ void SystemCoreClockUpdate (void)
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}
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else
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{
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+ #if defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
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+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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+ /* HSE oscillator clock selected as PREDIV1 clock entry */
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+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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+ #else
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/* HSE selected as PLL clock entry */
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if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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{/* HSE oscillator clock divided by 2 */
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@@ -209,8 +356,47 @@ void SystemCoreClockUpdate (void)
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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+ #endif
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+ }
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+#else
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+ pllmull = pllmull >> 18;
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+
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+ if (pllmull != 0x0D)
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+ {
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+ pllmull += 2;
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+ }
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+ else
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+ { /* PLL multiplication factor = PLL input clock * 6.5 */
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+ pllmull = 13 / 2;
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+ }
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+
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+ if (pllsource == 0x00)
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+ {
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+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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+ }
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+ else
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+ {/* PREDIV1 selected as PLL clock entry */
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+
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+ /* Get PREDIV1 clock source and division factor */
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+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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+
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+ if (prediv1source == 0)
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+ {
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+ /* HSE oscillator clock selected as PREDIV1 clock entry */
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+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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+ }
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+ else
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+ {/* PLL2 clock selected as PREDIV1 clock entry */
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+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
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+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
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+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
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+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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+ }
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}
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+#endif /* air32f10x_CL */
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break;
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default:
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@@ -250,6 +436,59 @@ static void SetSysClock(void)
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source (default after reset) */
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}
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+/**
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+ * @brief Setup the external memory controller. Called in startup_air32f10x.s
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+ * before jump to __main
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+ * @param None
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+ * @retval None
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+ */
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+#ifdef DATA_IN_ExtSRAM
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+/**
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+ * @brief Setup the external memory controller.
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+ * Called in startup_air32f10x_xx.s/.c before jump to main.
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+ * This function configures the external SRAM mounted on air3210E-EVAL
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+ * board (air32 High density devices). This SRAM will be used as program
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+ * data memory (including heap and stack).
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+ * @param None
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+ * @retval None
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+ */
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+void SystemInit_ExtMemCtl(void)
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+{
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+/*!< FSMC Bank1 NOR/SRAM3 is used for the air3210E-EVAL, if another Bank is
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+ required, then adjust the Register Addresses */
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+
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+ /* Enable FSMC clock */
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+ RCC->AHBENR = 0x00000114;
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+
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+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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+ RCC->APB2ENR = 0x000001E0;
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+
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+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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+/*---------------- SRAM Address lines configuration -------------------------*/
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+/*---------------- NOE and NWE configuration --------------------------------*/
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+/*---------------- NE3 configuration ----------------------------------------*/
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+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
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+
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+ GPIOD->CRL = 0x44BB44BB;
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+ GPIOD->CRH = 0xBBBBBBBB;
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+
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+ GPIOE->CRL = 0xB44444BB;
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+ GPIOE->CRH = 0xBBBBBBBB;
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+
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+ GPIOF->CRL = 0x44BBBBBB;
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+ GPIOF->CRH = 0xBBBB4444;
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+
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+ GPIOG->CRL = 0x44BBBBBB;
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+ GPIOG->CRH = 0x44444B44;
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+
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+/*---------------- FSMC Configuration ---------------------------------------*/
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+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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+
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+ FSMC_Bank1->BTCR[4] = 0x00001011;
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+ FSMC_Bank1->BTCR[5] = 0x00000200;
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+}
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+#endif /* DATA_IN_ExtSRAM */
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+
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#ifdef SYSCLK_FREQ_HSE
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/**
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2
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@@ -284,13 +523,27 @@ static void SetSysClockToHSE(void)
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if (HSEStatus == (uint32_t)0x01)
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{
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+
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+#if !defined air32f10x_LD_VL && !defined air32f10x_MD_VL && !defined air32f10x_HD_VL
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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+#ifndef air32f10x_CL
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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+#else
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+ if (HSE_VALUE <= 24000000)
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+ {
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+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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+ }
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+ else
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+ {
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+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
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+ }
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+#endif /* air32f10x_CL */
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+#endif
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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@@ -349,12 +602,14 @@ static void SetSysClockTo24(void)
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if (HSEStatus == (uint32_t)0x01)
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{
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+#if !defined air32f10x_LD_VL && !defined air32f10x_MD_VL && !defined air32f10x_HD_VL
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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+#endif
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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@@ -365,9 +620,35 @@ static void SetSysClockTo24(void)
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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+#ifdef air32f10x_CL
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+ /* Configure PLLs ------------------------------------------------------*/
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+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
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+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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+ RCC_CFGR_PLLMULL6);
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+
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+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
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+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
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+
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+ /* Enable PLL2 */
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+ RCC->CR |= RCC_CR_PLL2ON;
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+ /* Wait till PLL2 is ready */
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+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
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+ {
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+ }
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+#elif defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || defined (air32f10x_HD_VL)
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+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
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+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
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+#else
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/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
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+#endif /* air32f10x_CL */
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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@@ -441,9 +722,34 @@ static void SetSysClockTo36(void)
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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+#ifdef air32f10x_CL
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+ /* Configure PLLs ------------------------------------------------------*/
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+
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+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
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+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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+ RCC_CFGR_PLLMULL9);
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+
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+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
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+
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+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
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+
|
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+ /* Enable PLL2 */
|
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+ RCC->CR |= RCC_CR_PLL2ON;
|
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+ /* Wait till PLL2 is ready */
|
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+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
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+ }
|
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+
|
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+#else
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|
/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
|
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
|
|
|
+#endif /* air32f10x_CL */
|
|
|
|
|
|
/* Enable PLL */
|
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
@@ -517,9 +823,33 @@ static void SetSysClockTo48(void)
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/* PCLK1 = HCLK */
|
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|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
|
|
|
+#ifdef air32f10x_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL6);
|
|
|
+#else
|
|
|
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
|
|
|
+#endif /* air32f10x_CL */
|
|
|
|
|
|
/* Enable PLL */
|
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
@@ -594,10 +924,35 @@ static void SetSysClockTo56(void)
|
|
|
/* PCLK1 = HCLK */
|
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
|
|
|
+#ifdef air32f10x_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL7);
|
|
|
+#else
|
|
|
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
|
|
|
|
|
|
+#endif /* air32f10x_CL */
|
|
|
+
|
|
|
/* Enable PLL */
|
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
|
|
|
@@ -672,10 +1027,34 @@ static void SetSysClockTo72(void)
|
|
|
/* PCLK1 = HCLK */
|
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
|
|
|
+#ifdef air32f10x_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL9);
|
|
|
+#else
|
|
|
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
|
|
|
RCC_CFGR_PLLMULL));
|
|
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
|
|
|
+#endif /* air32f10x_CL */
|
|
|
|
|
|
/* Enable PLL */
|
|
|
RCC->CR |= RCC_CR_PLLON;
|
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