Merge branch 'fix_1103'

# Conflicts:
#	bsp/ra6m4-cpk/README.md
#	bsp/ra6m4-cpk/docs/picture/rascuart.png
#	bsp/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
#	bsp/ra6m4-cpk/src/hal_entry.c

bsp/ra6m4-cpk/.config

@@ -134,7 +134,7 @@ CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
-# CONFIG_RT_USING_PIN is not set
+CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
@@ -573,12 +573,21 @@ CONFIG_SOC_SERIES_R7FA6M4AF=y
 #
 # On-chip Peripheral Drivers
 #
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_ONCHIP_FLASH is not set
+# CONFIG_BSP_USING_WDT is not set
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART7=y
 # CONFIG_BSP_UART7_RX_USING_DMA is not set
 # CONFIG_BSP_UART7_TX_USING_DMA is not set
 CONFIG_BSP_UART7_RX_BUFSIZE=256
 CONFIG_BSP_UART7_TX_BUFSIZE=0
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_PWM is not set
 
 #
 # Board extended module Drivers

bsp/ra6m4-cpk/.ignore_format.yml

@@ -0,0 +1,8 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- ra
+- ra_gen
+- ra_cfg

bsp/ra6m4-cpk/.settings/standalone.prefs

@@ -1,19 +1,21 @@
-#Mon Oct 11 16:20:05 CST 2021
+#Wed Nov 03 20:31:16 CST 2021
 com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/all=1957950123,ra/fsp/inc/api/r_ioport_api.h|1390983687,ra/fsp/inc/instances/r_ioport.h|3204787724,ra/fsp/src/r_ioport/r_ioport.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/all=1390983687,ra/fsp/inc/instances/r_ioport.h|3204787724,ra/fsp/src/r_ioport/r_ioport.c|1957950123,ra/fsp/inc/api/r_ioport_api.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c|1906465970,ra/fsp/inc/api/r_external_irq_api.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/all=3581546608,ra/fsp/inc/fsp_common_api.h|2247478812,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1222394411,ra/fsp/src/bsp/mcu/all/bsp_io.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1390983687,ra/fsp/inc/instances/r_ioport.h|496115995,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3590501432,ra/fsp/src/bsp/mcu/all/bsp_io.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|905231975,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1868795951,ra/fsp/inc/fsp_features.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2966752275,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3098075304,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2556589544,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2812024316,ra/fsp/src/bsp/mcu/all/bsp_common.h|1957950123,ra/fsp/inc/api/r_ioport_api.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|3520119047,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2006974055,ra/fsp/inc/api/bsp_api.h|3819230577,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3131094294,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1982083345,ra/fsp/src/bsp/mcu/all/bsp_security.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|3366593968,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|4191472725,ra/fsp/inc/fsp_version.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1222394411,ra/fsp/src/bsp/mcu/all/bsp_io.c|3098075304,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|905231975,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3590501432,ra/fsp/src/bsp/mcu/all/bsp_io.h|1868795951,ra/fsp/inc/fsp_features.h|2556589544,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3581546608,ra/fsp/inc/fsp_common_api.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|496115995,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2812024316,ra/fsp/src/bsp/mcu/all/bsp_common.h|1390983687,ra/fsp/inc/instances/r_ioport.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|4191472725,ra/fsp/inc/fsp_version.h|2247478812,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3131094294,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3366593968,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3520119047,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1982083345,ra/fsp/src/bsp/mcu/all/bsp_security.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3819230577,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2966752275,ra/fsp/src/bsp/mcu/all/bsp_delay.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2006974055,ra/fsp/inc/api/bsp_api.h|1957950123,ra/fsp/inc/api/r_ioport_api.h
 com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/libraries=
-com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#R7FA6M4AF3CFB\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/all=546157604,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1078551279,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1536854638,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|206980015,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2024281644,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4231934849,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2748964184,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|377628369,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|637879414,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4005730526,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3589068132,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3021372151,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1562896660,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2491522803,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3602366610,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3779323067,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3442821435,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2686445441,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/all=2349328507,ra/fsp/src/r_sci_uart/r_sci_uart.c|853178775,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|1672784957,ra/fsp/inc/instances/r_sci_uart.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/all=3571093944,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h|2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3852442662,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/all=2686445441,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2491522803,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2748964184,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3589068132,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1536854638,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|206980015,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|4005730526,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1078551279,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|546157604,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1562896660,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3021372151,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3602366610,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2024281644,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|4231934849,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|3442821435,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|637879414,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|377628369,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3779323067,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/all=2349328507,ra/fsp/src/r_sci_uart/r_sci_uart.c|1672784957,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|853178775,ra/fsp/inc/api/r_uart_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/all=2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3852442662,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|3571093944,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/libraries=
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.813326093=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/all=3938710240,ra/board/ra6m4_cpk/board_leds.c|3343992478,ra/board/ra6m4_cpk/board.h|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|3559227370,ra/board/ra6m4_cpk/board_init.c|3843040667,ra/board/ra6m4_cpk/board_leds.h|2967196421,ra/board/ra6m4_cpk/board_init.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/all=3843040667,ra/board/ra6m4_cpk/board_leds.h|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|3559227370,ra/board/ra6m4_cpk/board_init.c|2967196421,ra/board/ra6m4_cpk/board_init.h|3343992478,ra/board/ra6m4_cpk/board.h|3938710240,ra/board/ra6m4_cpk/board_leds.c
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/libraries=

bsp/ra6m4-cpk/README.md

@@ -1,4 +1,4 @@
-# STM32H750-artpi 开发板 BSP 说明
+# 瑞萨 CPK-RA6M4 开发板 BSP 说明
 
 ## 简介
 
@@ -25,16 +25,23 @@
 
 **更多详细资料及工具**
 
-
 ## 外设支持
 
 本 BSP 目前对外设的支持情况如下：
 
-| **片上外设** | **支持情况** | **备注**                  |
-| :----------- | :---------- | :------------------------ |
-| UART         |     支持     | UART7               |
-| 持续更新中... |  |          |
-
+| **片上外设** | **支持情况** | **备注** |
+| :----------------- | :----------------- | :------------- |
+| UART               | 支持               | UART7          |
+| GPIO               | 支持               |                |
+| IIC                | 支持               | 软件           |
+| WDT                | 支持               |                |
+| RTC                | 支持               |                |
+| ADC                | 支持               |                |
+| DAC                | 支持               |                |
+| SPI                | 支持               |                |
+| FLASH              | 支持               |                |
+| PWM                | 支持               |                |
+| 持续更新中...      |                    |                |
 
 ## 使用说明
 
@@ -42,16 +49,14 @@
 
 - 快速上手
 
-    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
-
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
 - 进阶使用
 
-    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
-
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
 
 ### 快速上手
 
-本 BSP 为目前仅为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
 
 **硬件连接**
 
@@ -63,7 +68,7 @@
 
 > 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
 
-- 下载：打开 J-Flash lite 工具，选择芯片信号 R7FA6M4AF，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
+- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA6M4AF，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
 
 ![image-20211011181555421](docs/picture/jflash1.png)
 
@@ -85,7 +90,7 @@
  / | \     4.0.4 build Oct 11 2021
  2006 - 2021 Copyright by rt-thread team
 
-asdasHello RT-Thread!
+Hello RT-Thread!
 msh >
 msh >help
 RT-Thread shell commands:
@@ -108,44 +113,57 @@ list             - list all commands in system
 
 msh > 
 ```
-### 进阶使用
 
-**ENV 配置**
+**应用入口函数**
 
-- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+应用层的入口函数在 **bsp\ra6m4-cpk\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
 
-此 BSP 默认只开启了 串口7 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。步骤如下：
+```c
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
 
-1. 在 bsp 下打开 env 工具。
+    while (1)
+    {
+        rt_pin_write(LED3_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED3_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
 
-2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+### 进阶使用
 
-3. 输入`pkgs --update`命令更新软件包。
+**资料及文档**
 
-4. 输入`scons --target=mdk5` 命令重新生成工程。
+- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra6m4-evaluation-board)
+- [开发板用户手册](https://www2.renesas.cn/cn/zh/document/mah/1527156?language=zh&r=1527191)
+- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
+- [RA6 MCU 快速设计指南](https://www2.renesas.cn/cn/zh/document/apn/ra6-quick-design-guide)
+- [RA6M4_datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra6m4-group-datasheet)
+- [RA6M4 Group User’s Manual: Hardware](https://www2.renesas.cn/cn/zh/document/man/ra6m4-group-user-s-manual-hardware)
 
 **FSP 配置**
 
-如果需要修改瑞萨的 BSP 外设配置或者需要添加新的外设端口，需要用到瑞萨的 FSP 配置工具。
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
 
 1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)
-2. 下载安装完成后，需要添加这款开发板的官方[CPK-RA6M4板级支持包](https://www2.renesas.cn/document/sws/1527176?language=zh&r=1527191)
-3. 如何将BSP配置包添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
-4. 在 MDK 中添加自定义命名来打开当前工程的配置详细步骤，请查看文档： [使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)
-
-## 更多资料及文档
-
-- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra6m4-evaluation-board)
-
-- [开发板用户手册](https://www2.renesas.cn/cn/zh/document/mah/1527156?language=zh&r=1527191)
+2. 下载安装完成后，需要添加 CPK-RA6M4 开发板的[官方板级支持包](https://www2.renesas.cn/document/sws/1527176?language=zh&r=1527191)
+3. 如何将 BSP 配置包添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
+4. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置，
 
-- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091) 
+**ENV 配置**
 
-- [RA6 MCU 快速设计指南](https://www2.renesas.cn/cn/zh/document/apn/ra6-quick-design-guide) 
+- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
 
-- [RA6M4_datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra6m4-group-datasheet) 
+此 BSP 默认只开启了 串口7 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
 
-- [RA6M4 Group User’s Manual: Hardware](https://www2.renesas.cn/cn/zh/document/man/ra6m4-group-user-s-manual-hardware) 
+步骤如下：
+1. 在 bsp 下打开 env 工具。
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+3. 输入`pkgs --update`命令更新软件包。
+4. 输入`scons --target=mdk5` 命令重新生成工程。
 
 ## 联系人信息
 
@@ -153,4 +171,4 @@ msh >
 
 ## 贡献代码
 
-如果您对 CPK-RA6M4 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github) 。
+如果您对 CPK-RA6M4 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github) 。

bsp/ra6m4-cpk/buildinfo.gpdsc

@@ -58,12 +58,14 @@
         <file category="source" name="ra/board/ra6m4_cpk/board_leds.c"/>
         <file category="header" name="ra/board/ra6m4_cpk/board_leds.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
@@ -97,6 +99,7 @@
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h" path=""/>
+        <file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
         <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
         <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
         <file category="other" name="ra/SConscript"/>
@@ -112,6 +115,7 @@
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
         <file category="other" name="ra_cfg/SConscript"/>

bsp/ra6m4-cpk/configuration.xml

@@ -163,6 +163,10 @@
       <description>SCI UART</description>
       <originalPack>Renesas.RA.3.1.0.pack</originalPack>
     </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.1.0">
+      <description>External Interrupt</description>
+      <originalPack>Renesas.RA.3.1.0.pack</originalPack>
+    </component>
   </raComponentSelection>
   <raElcConfiguration/>
   <raIcuConfiguration/>
@@ -196,13 +200,26 @@
       <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
       <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
     </module>
+    <module id="module.driver.external_irq_on_icu.402865750">
+      <property id="module.driver.external_irq.name" value="g_external_irq0"/>
+      <property id="module.driver.external_irq.channel" value="0"/>
+      <property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
+      <property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
+      <property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
+      <property id="module.driver.external_irq.p_callback" value="irq0_callback"/>
+      <property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority12"/>
+    </module>
     <context id="_hal.0">
       <stack module="module.driver.ioport_on_ioport.0"/>
       <stack module="module.driver.uart_on_sci_uart.813326093"/>
+      <stack module="module.driver.external_irq_on_icu.402865750"/>
     </context>
     <config id="config.driver.ioport">
       <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
     </config>
+    <config id="config.driver.icu">
+      <property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
+    </config>
     <config id="config.driver.sci_uart">
       <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
       <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
@@ -320,16 +337,19 @@
     <symbolicName propertyId="p712.symbolic_name" value="ARDUINO_GPIO_PWM"/>
     <symbolicName propertyId="p713.symbolic_name" value="ARDUINO_GPIO"/>
     <pincfg active="true" name="RA6M4 CPK" selected="true" symbol="g_bsp_pin_cfg">
-      <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
-      <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
-      <configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/>
       <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
       <configSetting altId="adc0.an04.p004" configurationId="adc0.an04"/>
       <configSetting altId="adc0.an05.p005" configurationId="adc0.an05"/>
       <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="adc1.an00.p000" configurationId="adc1.an00"/>
+      <configSetting altId="adc1.an01.p001" configurationId="adc1.an01"/>
+      <configSetting altId="adc1.an02.p002" configurationId="adc1.an02"/>
+      <configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/>
       <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/>
       <configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/>
       <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/>
+      <configSetting altId="dac0.da.p014" configurationId="dac0.da"/>
+      <configSetting altId="dac0.mode.enabled" configurationId="dac0.mode"/>
       <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
       <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
       <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
@@ -361,8 +381,8 @@
       <configSetting altId="p006.gpio_pupd.gpio_pupd_ip_up" configurationId="p006.gpio_pupd"/>
       <configSetting altId="p008.output.low" configurationId="p008"/>
       <configSetting altId="p008.gpio_mode.gpio_mode_out.low" configurationId="p008.gpio_mode"/>
-      <configSetting altId="p014.output.low" configurationId="p014"/>
-      <configSetting altId="p014.gpio_mode.gpio_mode_out.low" configurationId="p014.gpio_mode"/>
+      <configSetting altId="p014.asel" configurationId="p014"/>
+      <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
       <configSetting altId="p015.output.low" configurationId="p015"/>
       <configSetting altId="p015.gpio_mode.gpio_mode_out.low" configurationId="p015.gpio_mode"/>
       <configSetting altId="p105.irq0.irq00" configurationId="p105"/>

bsp/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md

@@ -1,5 +1,7 @@
 ## 在 MDK 中使用 FSP
 
+- 添加RA Smart Config
+
 1. 打开 MDK，选择 “Tools -> Customize Tools Menu…”
 2. 点击 “new” 图标，添加一条自定义命令: RA Smart Configurator
 3. Command 输入工具的安装路径， 点击“…”找到安装路径下的“rasc.exe”文件并选中 (setup_fsp_v3_1_0_rasc_ 安装目录下)
@@ -13,10 +15,198 @@
 
 ![image.png](picture/openrasc.png)
 
+- 添加 Device Partition Manager，添加步骤同上。
+
+1. 输入命令名称: `Device Partition Manager`
+2. Command: 在安装路径选中 `rasc.exe`
+3. Initial Folder : `$P`
+4. Arguments: `-application com.renesas.cdt.ddsc.dpm.ui.dpmapplication configuration.xml "SL%L"` 
+
+> PS：以上相关操作也可以在 FSP 的说明文档中找到。
+>
+> 文档路径（本地）：在 FSP 的安装目录下  .\fsp_documentation\v3.1.0\fsp_user_manual_v3.1.0\index.html
+>
+> 文档路径（官网）：https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document
+
+## 更新工程配置
+
+使用 FSP 配置完成后如果有新的文件添加进工程中，不会马上添加进去。需要先编译一次，如果弹出如下提醒，选择 “是” 然后再次编译即可。
+
+![img](picture/import_changes.png)
+
+
 ## UART
 
-- 添加一个 UART 端口外设配置
+如何添加一个 UART 端口外设配置？
+
+1. 选择 Stacks 配置页，点击 New Stack 找到 UART。
 
 ![image.png](picture/rascuart.png)
 
-![image.png](picture/rascuart1.png)
+2. 配置 UART 参数，因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel**  、**callback** 是一致的标号。![image.png](picture/rascuart1.png)
+
+## GPIO 中断
+
+如何添加一个 IO 中断？
+
+1. 选择引脚编号，进入配置，比如选择 P105 做为中断引脚。可先找到引脚查看可配置成的 IRQx 通道号。
+
+![image-20211103200949759](picture/p105.png)
+
+2. 打开 ICU 中断通道 IRQ00
+
+![image-20211103200813467](picture/irq0.png)
+
+3. 创建 stack 并进入配置。因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel**  、**callback** 是一致的标号。选择你希望的触发方式，最后保存配置，生成配置代码。
+
+![](picture/1635929089445.png)
+
+![image-20211103201047103](picture/irq1.png)
+
+4. 测试中断是否成功开启
+
+   ```c
+   #define IRQ_TEST_PIN	"p104"
+   void irq_callback_test(void *args)
+   {
+       rt_kprintf("\n IRQ01 triggered \n");
+   }
+
+   void icu_sample(void)
+   {
+       /* init P104 */
+       rt_uint32_t pin = rt_pin_get(IRQ_TEST_PIN);
+       rt_kprintf("\n pin number : 0x%04X \n", pin);
+       rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, irq_callback_test, RT_NULL);
+       if(RT_EOK != err)
+       {
+           rt_kprintf("\n attach irq failed. \n");
+       }
+       err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
+       if(RT_EOK != err)
+       {
+           rt_kprintf("\n enable irq failed. \n");
+       }
+   }
+   MSH_CMD_EXPORT(icu_sample, icu sample);
+   ```
+
+## WDT
+
+1. 创建 WDT
+
+![image-20211019152302939](picture/wdt.png)
+
+2. 配置 WDT，需要注意在 RT-Thread 中只使用了一个 WDT 设备，所以没有对其进行编号，如果是新创建的 WDT 设备需要注意 name 字段，在驱动中默认使用的是`g_wdt` 。
+
+![image-20211019152407572](picture/wdt_config.png)
+
+3. 如何在 ENV 中打开 WDT 以及[WDT 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog)
+
+![image-20211027183406251](picture/wdt_env.png)
+
+## RTC
+
+1. 添加 RTC 设备
+
+![image-20211019152536749](picture/rtc.png)
+
+2. 配置 RTC，需要注意在 RT-Thread 中只是用了一个 RTC 设备，所以没有对其进行编号，如果是新创建的 RTC 设备需要注意 name 字段，在驱动中默认使用的是`g_rtc` 。修改 Callback 为 rtc_callback
+
+![image-20211019152627412](picture/rtc_config.png)
+
+3. 如何在 ENV 中打开 RTC 以及[ RTC 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) 
+
+![image-20211027181550233](picture/rtc_env.png)
+
+## Flash
+
+1. 创建 Flash
+
+![image-20211026105031200](picture/add_flash.png)
+
+2. 配置 Flash，需要注意在 RT-Thread 中只使用了一个 flash 设备，所以没有对其进行编号，如果是新创建的 flash 设备需要注意 name 字段，在驱动中默认使用的是`g_flash` 。
+
+![image-20211026105628706](picture/config_flash.png)
+
+3. 如何在 ENV 中打开 Flash
+
+![image-20211026123252310](picture/flash_menuconfig.png)
+
+## SPI
+
+1. 添加一个 SPI 外设端口
+
+![image-20211027180820968](picture/spi_add.png)
+
+2. 配置 channel、name、Clock Phase、Clock Polarity、Callback、 SPI Mode 等参数，波特率在代码中可通过 API 修改，这里可以设置一个默认值。
+
+![img](picture/spi.png)
+
+3. 如何在 ENV 中打开 SPI 以及 [SPI 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi)
+
+   ![image-20211027181444023](picture/spi_env.png)
+
+## ADC/DAC
+
+创建 ADC/DAC
+
+![img](picture/adc_dac.png)
+
+- **ADC**
+
+1. 配置 name、unit、mode，选择扫描的通道编号
+
+![img](picture/adc_config.png)
+
+2. 配置扫描通道对应的引脚
+
+![img](picture/adc_config1.png)
+
+3. 在 menuconfig 中打开对应的通道
+
+- **DAC**
+
+1. 需要先关闭 P014 的默认 mode
+
+![img](picture/dac_config0.png)
+
+2. 开启 DAC0 通道
+
+![img](picture/dac_config1.png)
+
+3. 修改通道号为 0，与 DAC0 对应
+
+![img](picture/dac_config2.png)
+
+4. 在 menuconfig 中打开对应的通道
+
+## 通用 PWM 定时器（GPT）
+
+GPT 定时器在该芯片中可作为通用定时器，也可以用于产生 PWM 信号。在将其用于产生 PWM 信号时，GPT 定时器提供了 gpt0 - gpt9 总共 10 个通道，每个通道可以设定两个输出端口。当前版本的 PWM 驱动将每个通道都看做一个单独的 PWM 设备，每个设备都只有一个通道。用户可以选择开启一个通道的任意一个输出端口，或将两个端口均开启，但在同时开启两个端口的情况下，它们输出的波形将完全一致。
+
+1. 添加 GPT 设备
+
+   ![img](./picture/add_gpt1.png)
+   
+2. 配置通道
+
+   ![img](./picture/add_gpt2.png)
+
+   对 GPT 较为关键的配置如图所示，具体解释如下：
+
+   1. 将``Common`` ->``Pin Output Support`` 设置为 Enable ，以开启 PWM 波形的输出。
+   2. 指定 GPT 通道，并根据通道数指定 GPT 的名称，例如此处指定 GPT 通道 3 ，所以 GPT 的名称必须为``g_timer3``。并且将定时器模式设置为 PWM ，并指定每个 PWM 周期的计数值。
+   3. 设定 PWM 通道默认输出的占空比，这里为 50% 。
+   4. 设定 GPT 通道下两个输出端口的使能状态。
+   5. 此处设置 GPT 通道下两个输出端口各自对应的引脚。
+   
+3. 配置输出引脚
+
+   ![img](./picture/add_gpt3.png)
+
+   在完成上一步对 GPT 定时器的设置后，根据图示找到对应 GPT 通道输出引脚设置的界面（这里是 GPT3），将图中标号 **1** 处设置为 ``GTIOCA or GTIOCB`` ，并根据需要在图中标号 **2** 处设置 GPT 通道下两个输出端口各自对应的输出引脚。
+   
+   4. 在 menuconfig 中打开对应的通道，[RT-Thread 的 pwm 框架介绍](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) 
+   
+   ![image-20211103202216381](picture/pwm_env.png)

bsp/ra6m4-cpk/drivers/Kconfig

@@ -12,6 +12,20 @@ menu "Hardware Drivers Config"
 
     menu "On-chip Peripheral Drivers"
 
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_ONCHIP_FLASH
+            bool "Enable Onchip FLASH"
+            default n
+
+        config BSP_USING_WDT
+            bool "Enable Watchdog Timer"
+            select RT_USING_WDT
+            default n
+
         menuconfig BSP_USING_UART
             bool "Enable UART"
             default y
@@ -46,6 +60,127 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 BUS (software simulation)"
+                    default y
+                    if BSP_USING_I2C1
+                        config BSP_I2C1_SCL_PIN
+                            int "i2c1 scl pin number"
+                            range 0x0000 0x0B0F
+                            default 0x0512
+                        config BSP_I2C1_SDA_PIN
+                            int "I2C1 sda pin number"
+                            range 0x0000 0x0B0F
+                            default 0x0511
+                    endif
+            endif
+
+        menuconfig BSP_USING_ONCHIP_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+            if BSP_USING_ONCHIP_RTC
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI
+                config BSP_SPI_USING_DTC_DMA
+                    bool "Enable SPI DTC transfers data without using the CPU."
+                    default n
+
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+        
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_DAC
+            bool "Enable DAC"
+            default n
+            select RT_USING_DAC
+            if BSP_USING_DAC
+                config BSP_USING_DAC0
+                    bool "Enable DAC0"
+                    default n
+
+                config BSP_USING_DAC1
+                    bool "Enable DAC1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM0
+                    bool "Enable GPT0 (32-Bits) output PWM"
+                    default n
+                
+                config BSP_USING_PWM1
+                    bool "Enable GPT1 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM2
+                    bool "Enable GPT2 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM3
+                    bool "Enable GPT3 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM4
+                    bool "Enable GPT4 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM6
+                    bool "Enable GPT6 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM7
+                    bool "Enable GPT7 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM8
+                    bool "Enable GPT8 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM9
+                    bool "Enable GPT9 (16-Bits) output PWM"
+                    default n
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/ra6m4-cpk/drivers/SConscript

@@ -9,13 +9,41 @@ src = Split("""
     drv_common.c
 """)
 
-if GetDepend(['RT_USING_SERIAL']):
+if GetDepend(['BSP_USING_UART']):
     if GetDepend(['RT_USING_SERIAL_V2']):
         src += ['drv_usart_v2.c']
     else:
         print("\nThe current project does not support serial-v1\n")
         Return('group')
 
+if GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['BSP_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['BSP_USING_ONCHIP_FLASH']):
+    src += ['drv_flash.c']
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
+
 path =  [cwd]
 path += [cwd + '/config']
 

bsp/ra6m4-cpk/drivers/config/drv_config.h

@@ -21,6 +21,18 @@ extern "C" {
 #ifdef SOC_SERIES_R7FA6M4AF
 #include "ra6m4/uart_config.h"
 
+#ifdef BSP_USING_ADC
+#include "ra6m4/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra6m4/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra6m4/pwm_config.h"
+#endif
+
 #endif/* SOC_SERIES_R7FA6M4AF */
 
 #ifdef __cplusplus

bsp/ra6m4-cpk/drivers/config/ra6m4/adc_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+struct ra_adc_map
+{
+    char name;
+    const adc_cfg_t *g_cfg;
+    const adc_instance_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+
+struct ra_dev
+{
+    rt_adc_device_t     ra_adc_device_t;
+    struct ra_adc_map  *ra_adc_dev;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/ra6m4-cpk/drivers/config/ra6m4/dac_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-26     KevinXu           first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/ra6m4-cpk/drivers/drv_adc.c

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include "drv_config.h"
+#ifdef RT_USING_ADC
+
+// #define DRV_DEBUG
+#define DBG_TAG              "drv.adc"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_adc_map ra_adc[] =
+{
+#if defined(BSP_USING_ADC0)
+    {'0', &g_adc0_cfg, &g_adc0_ctrl, &g_adc0_channel_cfg},
+#endif
+
+#if defined(BSP_USING_ADC1)
+    {'1', &g_adc1_cfg, &g_adc1_ctrl, &g_adc1_channel_cfg},
+#endif
+};
+
+#if defined(BSP_USING_ADC0)
+struct rt_adc_device adc0_device;
+struct ra_dev _ra_adc0_device = {.ra_adc_device_t = &adc0_device, .ra_adc_dev = &ra_adc[0]};
+#endif
+
+#if defined(BSP_USING_ADC1)
+struct rt_adc_device adc1_device;
+struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]};
+#endif
+
+static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    /**< start adc*/
+    if (enabled)
+    {
+        if (FSP_SUCCESS != R_ADC_ScanStart((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("start adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    else
+    {
+        /**< stop adc*/
+        if (FSP_SUCCESS != R_ADC_ScanStop((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("stop adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_adc_close(struct rt_adc_device *device)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)(struct ra_adc_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_ADC_Close((adc_ctrl_t *)adc->g_ctrl))
+    {
+        LOG_E("close adc%c failed.", adc->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    if (RT_EOK != R_ADC_Read32((adc_ctrl_t *)adc->g_ctrl, channel, value))
+    {
+        LOG_E("get adc value failed.\n");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops ra_adc_ops =
+{
+    .enabled = ra_adc_enabled,
+    .convert = ra_get_adc_value,
+};
+
+static int ra_adc_init(void)
+{
+#if defined(BSP_USING_ADC0)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc0_device.ra_adc_device_t, "adc0", &ra_adc_ops, (void *)_ra_adc0_device.ra_adc_dev))
+    {
+        LOG_E("adc0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#if defined(BSP_USING_ADC1)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc1_device.ra_adc_device_t, "adc1", &ra_adc_ops, (void *)_ra_adc1_device.ra_adc_dev))
+    {
+        LOG_E("adc1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(ra_adc_init);
+#endif

bsp/ra6m4-cpk/drivers/drv_common.c

@@ -12,12 +12,16 @@
 #include <bsp_api.h>
 #include "board.h"
 
-#ifdef RT_USING_SERIAL
-#ifdef RT_USING_SERIAL_V2
-#include <drv_usart_v2.h>
-#else
-#include <drv_usart.h>
+#ifdef RT_USING_PIN
+    #include <drv_gpio.h>
 #endif
+
+#ifdef RT_USING_SERIAL
+    #ifdef RT_USING_SERIAL_V2
+        #include <drv_usart_v2.h>
+    #else
+        #include <drv_usart.h>
+    #endif
 #endif
 
 #ifdef RT_USING_FINSH

bsp/ra6m4-cpk/drivers/drv_common.h

@@ -14,7 +14,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 #ifdef RT_USING_DEVICE
-#include <rtdevice.h>
+    #include <rtdevice.h>
 #endif
 
 #ifdef __cplusplus

bsp/ra6m4-cpk/drivers/drv_dac.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include "drv_config.h"
+#ifdef RT_USING_DAC
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.dac"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_dac_map ra_dac[] =
+{
+#ifdef BSP_USING_DAC0
+    {'0', &g_dac0_cfg, &g_dac0_ctrl},
+#endif
+#ifdef BSP_USING_DAC1
+    {'1', &g_dac1_cfg, &g_dac1_ctrl},
+#endif
+};
+
+#ifdef BSP_USING_DAC0
+struct rt_dac_device dac0_device;
+struct ra_dac_dev _ra_dac0_device = {.ra_dac_device_t = &dac0_device, .ra_dac_map_dev = &ra_dac[0]};
+#endif
+
+#ifdef BSP_USING_DAC1
+struct rt_dac_device dac1_device;
+struct ra_dac_dev _ra_dac1_device = {.ra_dac_device_t = &dac1_device, .ra_dac_map_dev = &ra_dac[1]};
+#endif
+
+rt_err_t ra_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Stop((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c stop failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Start((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c start failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_write(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Write((dac_ctrl_t *)dac->g_ctrl, *value))
+    {
+        LOG_E("dac%c set value failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+struct rt_dac_ops ra_dac_ops =
+{
+    .disabled = ra_dac_disabled,
+    .enabled  = ra_dac_enabled,
+    .convert  = ra_dac_write,
+};
+
+static int ra_dac_init(void)
+{
+#ifdef BSP_USING_DAC0
+    _ra_dac0_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac0_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *)_ra_dac0_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac0_device.ra_dac_device_t, "dac0", &ra_dac_ops, (void *)_ra_dac0_device.ra_dac_map_dev))
+    {
+        LOG_E("dac0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#ifdef BSP_USING_DAC1
+    _ra_dac1_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac1_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *) _ra_dac1_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac1_device.ra_dac_device_t, "dac1", &ra_dac_ops, (void *)_ra_dac1_device.ra_dac_map_dev))
+    {
+        LOG_E("dac1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(ra_dac_init);
+
+#endif

bsp/ra6m4-cpk/drivers/drv_flash.c

@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "board.h"
+#include "hal_data.h"
+#include "drv_flash.h"
+
+#include <rtthread.h>
+
+#if defined(PKG_USING_FAL)
+    #include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+int _flash_init(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    /* Open Flash_HP */
+    err = R_FLASH_HP_Open(&g_flash_ctrl, &g_flash_cfg);
+    /* Handle Error */
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("\r\n Flah_HP_Open API failed");
+    }
+    /* Setup Default  Block 0 as Startup Setup Block */
+    err = R_FLASH_HP_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
+    }
+    return 0;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int _flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -1;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result      = RT_EOK;
+    rt_base_t level;
+    fsp_err_t err = FSP_SUCCESS;
+    size_t written_size = 0;
+
+    if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size % BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE)
+    {
+        LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+        return -RT_EINVAL;
+    }
+
+    while (written_size < size)
+    {
+        level = rt_hw_interrupt_disable();
+        /* Write code flash data*/
+        err = R_FLASH_HP_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+        rt_hw_interrupt_enable(level);
+
+        /* Error Handle */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Write API failed");
+            return -RT_EIO;
+        }
+
+        written_size += BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE;
+    }
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int _flash_erase_8k(rt_uint32_t addr, size_t size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+    if ((addr + size) > BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    /* Erase Block */
+    err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_8KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1);
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase API failed");
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+int _flash_erase_128k(rt_uint32_t addr, size_t size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+    if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    /* Erase Block */
+    err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_32KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase API failed");
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
+
+static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
+
+static int fal_flash_erase_8k(long offset, size_t size);
+static int fal_flash_erase_128k(long offset, size_t size);
+
+const struct fal_flash_dev _onchip_flash_8k = { "onchip_flash_8k", FLASH_HP_CF_BLCOK_0, FLASH_HP_CF_BLOCK_8, (8 * 1024), {_flash_init, fal_flash_read_8k, fal_flash_write_8k, fal_flash_erase_8k} };
+const struct fal_flash_dev _onchip_flash_128k = { "onchip_flash_128k", FLASH_HP_CF_BLOCK_8, 32 * 3 * 1024, (128 * 1024), {_flash_init, fal_flash_read_128k, fal_flash_write_128k, fal_flash_erase_128k} };
+
+static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_8k.addr + offset, buf, size);
+}
+
+static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_128k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_8k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_128k.addr + offset, buf, size);
+}
+
+static int fal_flash_erase_8k(long offset, size_t size)
+{
+    return _flash_erase_8k(_onchip_flash_8k.addr + offset, size);
+}
+
+static int fal_flash_erase_128k(long offset, size_t size)
+{
+    return _flash_erase_128k(_onchip_flash_128k.addr + offset, size);
+}
+
+int flash_test(void)
+{
+#define TEST_OFF 0x10000
+    const struct fal_partition *param;
+    uint8_t write_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
+    uint8_t read_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint8_t index = 0; index < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    fal_init();
+
+    param = fal_partition_find("param");
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition param!");
+        return -1;
+    }
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST_OFF, read_buffer, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash_test, "drv flash test.");
+
+#endif

bsp/ra6m4-cpk/drivers/drv_flash.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Code Flash */
+#define FLASH_HP_CF_BLOCK_SIZE_32KB       (32*1024)    /* Block Size 32 KB */
+#define FLASH_HP_CF_BLOCK_SIZE_8KB        (8*1024)     /* Block Size 8KB */
+
+#define FLASH_HP_CF_BLCOK_0               0x00000000U  /*    8 KB:  0x00000000 - 0x00001FFF */
+#define FLASH_HP_CF_BLOCK_1               0x00002000U  /*    8 KB:  0x00002000 - 0x00003FFF */
+#define FLASH_HP_CF_BLOCK_2               0x00004000U  /*    8 KB:  0x00004000 - 0x00005FFF */
+#define FLASH_HP_CF_BLOCK_3               0x00006000U  /*    8 KB:  0x00006000 - 0x00007FFF */
+#define FLASH_HP_CF_BLOCK_4               0x00008000U  /*    8 KB:  0x00008000 - 0x00009FFF */
+#define FLASH_HP_CF_BLOCK_5               0x0000A000U  /*    8 KB:  0x0000A000 - 0x0000BFFF */
+#define FLASH_HP_CF_BLOCK_6               0x0000C000U  /*    8 KB:  0x0000C000 - 0x0000DFFF */
+#define FLASH_HP_CF_BLOCK_7               0x0000E000U  /*    8 KB:  0x0000E000 - 0x0000FFFF */
+#define FLASH_HP_CF_BLOCK_8               0x00010000U  /*   32 KB: 0x00010000 - 0x00017FFF */
+#define FLASH_HP_CF_BLOCK_9               0x00018000U  /*   32 KB: 0x00018000 - 0x0001FFFF */
+#define FLASH_HP_CF_BLCOK_10              0x00020000U  /*   32 KB: 0x00020000 - 0x0004FFFF */
+
+#define FLASH_HP_DF_BLOCK_SIZE            (64)
+/* Data Flash */
+#if (defined (BOARD_RA6M4_EK) || defined (BOARD_RA6M5_EK) || defined (BOARD_RA4M3_EK)||defined(BOARD_RA4M2_EK))
+
+#define FLASH_HP_DF_BLOCK_0               0x08000000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x08000040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x08000080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x080000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#else
+
+#define FLASH_HP_DF_BLOCK_0               0x40100000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x40100040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x40100080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x401000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#endif
+
+#define BLOCK_SIZE                        (128)
+#define BLOCK_NUM                         (2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/ra6m4-cpk/drivers/drv_gpio.c

@@ -0,0 +1,589 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#include <drv_gpio.h>
+
+#ifdef RT_USING_PIN
+
+#define DBG_TAG              "drv.gpio"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#ifdef R_ICU_H
+static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
+{
+    switch (pin)
+    {
+    case BSP_IO_PORT_04_PIN_00:
+    case BSP_IO_PORT_02_PIN_06:
+    case BSP_IO_PORT_01_PIN_05:
+        return 0;
+
+    case BSP_IO_PORT_02_PIN_05:
+    case BSP_IO_PORT_01_PIN_01:
+    case BSP_IO_PORT_01_PIN_04:
+        return 1;
+
+    case BSP_IO_PORT_02_PIN_03:
+    case BSP_IO_PORT_01_PIN_00:
+    case BSP_IO_PORT_02_PIN_13:
+        return 2;
+
+    case BSP_IO_PORT_02_PIN_02:
+    case BSP_IO_PORT_01_PIN_10:
+    case BSP_IO_PORT_02_PIN_12:
+        return 3;
+
+    case BSP_IO_PORT_04_PIN_02:
+    case BSP_IO_PORT_01_PIN_11:
+    case BSP_IO_PORT_04_PIN_11:
+        return 4;
+
+    case BSP_IO_PORT_04_PIN_01:
+    case BSP_IO_PORT_03_PIN_02:
+    case BSP_IO_PORT_04_PIN_10:
+        return 5;
+
+    case BSP_IO_PORT_03_PIN_01:
+    case BSP_IO_PORT_00_PIN_00:
+    case BSP_IO_PORT_04_PIN_09:
+        return 6;
+
+    case BSP_IO_PORT_00_PIN_01:
+    case BSP_IO_PORT_04_PIN_08:
+        return 7;
+
+    case BSP_IO_PORT_00_PIN_02:
+    case BSP_IO_PORT_03_PIN_05:
+    case BSP_IO_PORT_04_PIN_15:
+        return 8;
+
+    case BSP_IO_PORT_00_PIN_04:
+    case BSP_IO_PORT_03_PIN_04:
+    case BSP_IO_PORT_04_PIN_14:
+        return 9;
+
+    case BSP_IO_PORT_00_PIN_05:
+    case BSP_IO_PORT_07_PIN_09:
+        return 10;
+
+    case BSP_IO_PORT_05_PIN_01:
+    case BSP_IO_PORT_00_PIN_06:
+    case BSP_IO_PORT_07_PIN_08:
+        return 11;
+
+    case BSP_IO_PORT_05_PIN_02:
+    case BSP_IO_PORT_00_PIN_08:
+        return 12;
+
+    case BSP_IO_PORT_00_PIN_15:
+    case BSP_IO_PORT_00_PIN_09:
+        return 13;
+
+    case BSP_IO_PORT_04_PIN_03:
+    case BSP_IO_PORT_05_PIN_12:
+    case BSP_IO_PORT_05_PIN_05:
+        return 14;
+
+    case BSP_IO_PORT_04_PIN_04:
+    case BSP_IO_PORT_05_PIN_11:
+    case BSP_IO_PORT_05_PIN_06:
+        return 15;
+
+    default  :
+        return -1;
+    }
+}
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+#define RA_IRQ_MAX  16
+struct ra_pin_irq_map pin_irq_map[RA_IRQ_MAX] = {0};
+
+static void ra_pin_map_init(void)
+{
+#ifdef VECTOR_NUMBER_ICU_IRQ0
+    pin_irq_map[0].irq_ctrl = &g_external_irq0_ctrl;
+    pin_irq_map[0].irq_cfg = &g_external_irq0_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ1
+    pin_irq_map[1].irq_ctrl = &g_external_irq1_ctrl;
+    pin_irq_map[1].irq_cfg = &g_external_irq1_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ2
+    pin_irq_map[2].irq_ctrl = &g_external_irq2_ctrl;
+    pin_irq_map[2].irq_cfg = &g_external_irq2_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ3
+    pin_irq_map[3].irq_ctrl = &g_external_irq3_ctrl;
+    pin_irq_map[3].irq_cfg = &g_external_irq3_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ4
+    pin_irq_map[4].irq_ctrl = &g_external_irq4_ctrl;
+    pin_irq_map[4].irq_cfg = &g_external_irq4_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ5
+    pin_irq_map[5].irq_ctrl = &g_external_irq5_ctrl;
+    pin_irq_map[5].irq_cfg = &g_external_irq5_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ6
+    pin_irq_map[6].irq_ctrl = &g_external_irq6_ctrl;
+    pin_irq_map[6].irq_cfg = &g_external_irq6_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ7
+    pin_irq_map[7].irq_ctrl = &g_external_irq7_ctrl;
+    pin_irq_map[7].irq_cfg = &g_external_irq7_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ8
+    pin_irq_map[8].irq_ctrl = &g_external_irq8_ctrl;
+    pin_irq_map[8].irq_cfg = &g_external_irq8_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ9
+    pin_irq_map[9].irq_ctrl = &g_external_irq9_ctrl;
+    pin_irq_map[9].irq_cfg = &g_external_irq9_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ10
+    pin_irq_map[10].irq_ctrl = &g_external_irq10_ctrl;
+    pin_irq_map[10].irq_cfg = &g_external_irq10_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ11
+    pin_irq_map[11].irq_ctrl = &g_external_irq11_ctrl;
+    pin_irq_map[11].irq_cfg = &g_external_irq11_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ12
+    pin_irq_map[12].irq_ctrl = &g_external_irq12_ctrl;
+    pin_irq_map[12].irq_cfg = &g_external_irq12_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ13
+    pin_irq_map[13].irq_ctrl = &g_external_irq13_ctrl;
+    pin_irq_map[13].irq_cfg = &g_external_irq13_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ14
+    pin_irq_map[14].irq_ctrl = &g_external_irq14_ctrl;
+    pin_irq_map[14].irq_cfg = &g_external_irq14_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ15
+    pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
+    pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
+#endif
+}
+#endif  /* R_ICU_H */
+
+static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    fsp_err_t err;
+    /* Initialize the IOPORT module and configure the pins */
+    err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("GPIO open failed");
+        return;
+    }
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_INPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_INPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_OUTPUT_OD:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
+            return;
+        }
+        break;
+    }
+}
+
+static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
+
+    if (value != level)
+    {
+        level = BSP_IO_LEVEL_LOW;
+    }
+
+    R_BSP_PinAccessEnable();
+    R_BSP_PinWrite(pin, level);
+    R_BSP_PinAccessDisable();
+}
+
+static int ra_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
+    {
+        LOG_E("GPIO pin value is illegal");
+        return -RT_ERROR;
+    }
+    return R_BSP_PinRead(pin);
+}
+
+static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+#ifdef R_ICU_H
+    rt_err_t err;
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (PIN_IRQ_ENABLE == enabled)
+    {
+        if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+        {
+            err = R_ICU_ExternalIrqOpen((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl,
+                                        (external_irq_cfg_t const * const)pin_irq_map[irqx].irq_cfg);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Open failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqOpen API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+
+            err = R_ICU_ExternalIrqEnable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Enable failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqEnable API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+        }
+    }
+    else if (PIN_IRQ_DISABLE == enabled)
+    {
+        err = R_ICU_ExternalIrqDisable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Disable failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqDisable API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+        err = R_ICU_ExternalIrqClose((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Close failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqClose API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                  rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < (sizeof(pin_irq_map) / sizeof(pin_irq_map[0])))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == irqx &&
+                pin_irq_hdr_tab[irqx].hdr == hdr &&
+                pin_irq_hdr_tab[irqx].mode == mode &&
+                pin_irq_hdr_tab[irqx].args == args)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        if (pin_irq_hdr_tab[irqx].pin != -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EBUSY;
+        }
+        pin_irq_hdr_tab[irqx].pin = irqx;
+        pin_irq_hdr_tab[irqx].hdr = hdr;
+        pin_irq_hdr_tab[irqx].mode = mode;
+        pin_irq_hdr_tab[irqx].args = args;
+        rt_hw_interrupt_enable(level);
+    }
+    else return -RT_ERROR;
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        pin_irq_hdr_tab[irqx].pin = -1;
+        pin_irq_hdr_tab[irqx].hdr = RT_NULL;
+        pin_irq_hdr_tab[irqx].mode = 0;
+        pin_irq_hdr_tab[irqx].args = RT_NULL;
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_base_t ra_pin_get(const char *name)
+{
+    int pin_number = -1, port = -1, pin = -1;
+    if (rt_strlen(name) != 4)
+        return -1;
+    if ((name[0] == 'P') || (name[0] == 'p'))
+    {
+        if ('0' <= (int)name[1] && (int)name[1] <= '9')
+        {
+            port = ((int)name[1] - 48) * 16 * 16;
+            if ('0' <= (int)name[2] && (int)name[2] <= '9')
+            {
+                if ('0' <= (int)name[3] && (int)name[3] <= '9')
+                {
+                    pin = ((int)name[2] - 48) * 10;
+                    pin += (int)name[3] - 48;
+                    pin_number = port + pin;
+                }
+                else return -1;
+            }
+            else return -1;
+        }
+        else return -1;
+    }
+    return pin_number;
+}
+
+const static struct rt_pin_ops _ra_pin_ops =
+{
+    .pin_mode       = ra_pin_mode,
+    .pin_write      = ra_pin_write,
+    .pin_read       = ra_pin_read,
+    .pin_attach_irq = ra_pin_attach_irq,
+    .pin_detach_irq = ra_pin_dettach_irq,
+    .pin_irq_enable = ra_pin_irq_enable,
+    .pin_get        = ra_pin_get,
+};
+
+int rt_hw_pin_init(void)
+{
+#ifdef R_ICU_H
+    ra_pin_map_init();
+#endif
+    return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
+}
+
+#ifdef R_ICU_H
+void irq0_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (0 == pin_irq_hdr_tab[0].pin)
+    {
+        pin_irq_hdr_tab[0].hdr(pin_irq_hdr_tab[0].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq1_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (1 == pin_irq_hdr_tab[1].pin)
+    {
+        pin_irq_hdr_tab[1].hdr(pin_irq_hdr_tab[1].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq2_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (2 == pin_irq_hdr_tab[2].pin)
+    {
+        pin_irq_hdr_tab[2].hdr(pin_irq_hdr_tab[2].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq3_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (3 == pin_irq_hdr_tab[3].pin)
+    {
+        pin_irq_hdr_tab[3].hdr(pin_irq_hdr_tab[3].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq4_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (4 == pin_irq_hdr_tab[4].pin)
+    {
+        pin_irq_hdr_tab[4].hdr(pin_irq_hdr_tab[4].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq5_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (5 == pin_irq_hdr_tab[5].pin)
+    {
+        pin_irq_hdr_tab[5].hdr(pin_irq_hdr_tab[5].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq6_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (6 == pin_irq_hdr_tab[6].pin)
+    {
+        pin_irq_hdr_tab[6].hdr(pin_irq_hdr_tab[6].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq7_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (7 == pin_irq_hdr_tab[7].pin)
+    {
+        pin_irq_hdr_tab[7].hdr(pin_irq_hdr_tab[7].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq8_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (8 == pin_irq_hdr_tab[8].pin)
+    {
+        pin_irq_hdr_tab[8].hdr(pin_irq_hdr_tab[8].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq9_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (9 == pin_irq_hdr_tab[9].pin)
+    {
+        pin_irq_hdr_tab[9].hdr(pin_irq_hdr_tab[9].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq10_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (10 == pin_irq_hdr_tab[10].pin)
+    {
+        pin_irq_hdr_tab[10].hdr(pin_irq_hdr_tab[10].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq11_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (11 == pin_irq_hdr_tab[11].pin)
+    {
+        pin_irq_hdr_tab[11].hdr(pin_irq_hdr_tab[11].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq12_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (12 == pin_irq_hdr_tab[12].pin)
+    {
+        pin_irq_hdr_tab[12].hdr(pin_irq_hdr_tab[12].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq13_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (13 == pin_irq_hdr_tab[13].pin)
+    {
+        pin_irq_hdr_tab[13].hdr(pin_irq_hdr_tab[13].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq14_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (14 == pin_irq_hdr_tab[14].pin)
+    {
+        pin_irq_hdr_tab[14].hdr(pin_irq_hdr_tab[14].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq15_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (15 == pin_irq_hdr_tab[15].pin)
+    {
+        pin_irq_hdr_tab[15].hdr(pin_irq_hdr_tab[15].args);
+    }
+    rt_interrupt_leave();
+};
+#endif /* R_ICU_H */
+
+#endif /* RT_USING_PIN */

bsp/ra6m4-cpk/drivers/drv_gpio.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <board.h>
+#include <rthw.h>
+#include <rtdbg.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_common.h>
+#include <hal_data.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_00
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_11_PIN_15
+
+#ifdef R_ICU_H
+struct ra_pin_irq_map
+{
+    const icu_instance_ctrl_t     *irq_ctrl;
+    const external_irq_cfg_t      *irq_cfg;
+};
+#endif
+
+int rt_hw_pin_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */

bsp/ra6m4-cpk/drivers/drv_pwm.c

@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-25     KevinXu      first version
+ */
+
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+
+/* Declare the control function first */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
+static struct rt_pwm_ops drv_ops =
+{
+    drv_pwm_control
+};
+
+static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
+{
+#ifdef BSP_USING_PWM0
+    [BSP_PWM0_INDEX] = PWM_DRV_INITIALIZER(0),
+#endif
+#ifdef BSP_USING_PWM1
+    [BSP_PWM1_INDEX] = PWM_DRV_INITIALIZER(1),
+#endif
+#ifdef BSP_USING_PWM2
+    [BSP_PWM2_INDEX] = PWM_DRV_INITIALIZER(2),
+#endif
+#ifdef BSP_USING_PWM3
+    [BSP_PWM3_INDEX] = PWM_DRV_INITIALIZER(3),
+#endif
+#ifdef BSP_USING_PWM4
+    [BSP_PWM4_INDEX] = PWM_DRV_INITIALIZER(4),
+#endif
+#ifdef BSP_USING_PWM5
+    [BSP_PWM5_INDEX] = PWM_DRV_INITIALIZER(5),
+#endif
+#ifdef BSP_USING_PWM6
+    [BSP_PWM6_INDEX] = PWM_DRV_INITIALIZER(6),
+#endif
+#ifdef BSP_USING_PWM7
+    [BSP_PWM7_INDEX] = PWM_DRV_INITIALIZER(7),
+#endif
+#ifdef BSP_USING_PWM8
+    [BSP_PWM8_INDEX] = PWM_DRV_INITIALIZER(8),
+#endif
+#ifdef BSP_USING_PWM9
+    [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
+#endif
+};
+
+
+/* Convert the raw PWM period counts into ns */
+static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
+    return ns;
+}
+
+/* Convert ns into raw PWM period counts */
+static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
+    return counts;
+}
+
+
+/* PWM_CMD_ENABLE or PWM_CMD_DISABLE */
+static rt_err_t drv_pwm_enable(struct ra_pwm *device,
+                               struct rt_pwm_configuration *configuration,
+                               rt_bool_t enable)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    if (enable)
+    {
+        err = R_GPT_Start(device->g_ctrl);
+    }
+    else
+    {
+        err = R_GPT_Stop(device->g_ctrl);
+    }
+
+    return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
+}
+
+/* PWM_CMD_GET */
+static rt_err_t drv_pwm_get(struct ra_pwm *device,
+                            struct rt_pwm_configuration *configuration)
+{
+    timer_info_t info;
+    if (R_GPT_InfoGet(device->g_ctrl, &info) != FSP_SUCCESS)
+        return -RT_ERROR;
+
+    configuration->pulse =
+        _convert_counts_ns(device->g_cfg->source_div, device->g_cfg->duty_cycle_counts);
+    configuration->period =
+        _convert_counts_ns(device->g_cfg->source_div, info.period_counts);
+    configuration->channel = device->g_cfg->channel;
+
+    return RT_EOK;
+}
+
+/* PWM_CMD_SET */
+static rt_err_t drv_pwm_set(struct ra_pwm *device,
+                            struct rt_pwm_configuration *conf)
+{
+    uint32_t counts;
+    fsp_err_t fsp_erra;
+    fsp_err_t fsp_errb;
+    rt_err_t rt_err;
+    uint32_t pulse;
+    uint32_t period;
+    struct rt_pwm_configuration orig_conf;
+
+    rt_err = drv_pwm_get(device, &orig_conf);
+    if (rt_err != RT_EOK)
+    {
+        return rt_err;
+    }
+
+    /* Pulse cannot last longer than period. */
+    period = conf->period;
+    pulse = (period >= conf->pulse) ? conf->pulse : period;
+
+    /* Not to set period again if it's not changed. */
+    if (period != orig_conf.period)
+    {
+        counts = _convert_ns_counts(device->g_cfg->source_div, period);
+        fsp_erra = R_GPT_PeriodSet(device->g_ctrl, counts);
+        if (fsp_erra != FSP_SUCCESS)
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    /* Two pins of a channel will not be separated. */
+    counts = _convert_ns_counts(device->g_cfg->source_div, pulse);
+    fsp_erra = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCA);
+    fsp_errb = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCB);
+    if (fsp_erra != FSP_SUCCESS || fsp_errb != FSP_SUCCESS)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * Implement of control method in struct rt_pwm_ops.
+ */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    struct ra_pwm *pwm_device = (struct ra_pwm *)device->parent.user_data;
+
+    /**
+     * There's actually only one GPT timer with 10 channels. In this case, the
+     * timer is separated into 10 PWM devices, so each device has only one
+     * channel.
+     */
+    if (configuration->channel != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_FALSE);
+    case PWM_CMD_GET:
+        return drv_pwm_get(pwm_device, configuration);
+    case PWM_CMD_SET:
+        return drv_pwm_set(pwm_device, configuration);
+    default:
+        return -RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * This is to register the PWM device
+ *
+ * Note that the PWM driver only supports one fixed pin.
+ */
+int rt_hw_pwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    rt_err_t rt_err = RT_EOK;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    for (int i = 0; i < BSP_PWMS_NUM; i++)
+    {
+        fsp_err = R_GPT_Open(ra6m4_pwm_obj[i].g_ctrl,
+                             ra6m4_pwm_obj[i].g_cfg);
+
+        rt_err = rt_device_pwm_register(&ra6m4_pwm_obj[i].pwm_device,
+                                        ra6m4_pwm_obj[i].name,
+                                        &drv_ops,
+                                        &ra6m4_pwm_obj[i]);
+
+        if (fsp_err != FSP_SUCCESS || rt_err != RT_EOK)
+        {
+            ret = -RT_ERROR;
+        }
+    }
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
+#endif /* RT_USING_PWM */

bsp/ra6m4-cpk/drivers/drv_pwm.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-25     KevinXu      first version
+ */
+
+#ifndef __DRV_PWM_H__
+#define __DRV_PWM_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+/* PWM device object structure */
+struct ra_pwm
+{
+    struct rt_device_pwm            pwm_device;
+    gpt_instance_ctrl_t             *g_ctrl;
+    timer_instance_t const *const   g_timer;
+    timer_cfg_t const *const        g_cfg;
+    char                            *name;
+};
+
+/* Get ra6m4 pwm device object from the general pwm device object */
+#define _GET_RA6M4_PWM_OBJ(ptr) rt_container_of(ptr, struct ra_pwm, pwm_device)
+
+#endif /* __DRV_PWM_H__ */

bsp/ra6m4-cpk/drivers/drv_rtc.c

@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-14     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include <sys/time.h>
+#include "hal_data.h"
+
+#ifdef BSP_USING_ONCHIP_RTC
+
+#define DBG_TAG              "drv.rtc"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static rt_err_t ra_rtc_init(void)
+{
+    rt_err_t result = RT_EOK;
+
+    if (R_RTC_Open(&g_rtc_ctrl, &g_rtc_cfg) != RT_EOK)
+    {
+        LOG_E("rtc init failed.");
+        result = -RT_ERROR;
+    }
+
+    return result;
+}
+
+static time_t get_rtc_timestamp(void)
+{
+    struct tm tm_new = {0};
+    rtc_time_t g_current_time = {0};
+
+    R_RTC_CalendarTimeGet(&g_rtc_ctrl, &g_current_time);
+
+    tm_new.tm_year  = g_current_time.tm_year;
+    tm_new.tm_mon   = g_current_time.tm_mon;
+    tm_new.tm_mday  = g_current_time.tm_mday;
+
+    tm_new.tm_hour  = g_current_time.tm_hour;
+    tm_new.tm_min   = g_current_time.tm_min;
+    tm_new.tm_sec   = g_current_time.tm_sec;
+
+    tm_new.tm_wday  = g_current_time.tm_wday;
+    tm_new.tm_yday  = g_current_time.tm_yday;
+    tm_new.tm_isdst = g_current_time.tm_isdst;
+
+    return timegm(&tm_new);
+}
+
+static rt_err_t ra_get_secs(void *args)
+{
+    *(rt_uint32_t *)args = get_rtc_timestamp();
+    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return RT_EOK;
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+    struct tm *p_tm;
+    rtc_time_t g_current_time = {0};
+    p_tm = gmtime(&time_stamp);
+    if (p_tm->tm_year < 100)
+    {
+        return -RT_ERROR;
+    }
+
+    g_current_time.tm_sec    = p_tm->tm_sec ;
+    g_current_time.tm_min    = p_tm->tm_min ;
+    g_current_time.tm_hour   = p_tm->tm_hour;
+
+    g_current_time.tm_mday   = p_tm->tm_mday;
+    g_current_time.tm_mon    = p_tm->tm_mon;
+    g_current_time.tm_year   = p_tm->tm_year;
+
+    g_current_time.tm_wday   = p_tm->tm_wday;
+    g_current_time.tm_yday   = p_tm->tm_yday;
+
+    if (R_RTC_CalendarTimeSet(&g_rtc_ctrl, &g_current_time) != FSP_SUCCESS)
+    {
+        LOG_E("set rtc time failed.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ra_set_secs(void *args)
+{
+
+    rt_err_t result = RT_EOK;
+
+    if (set_rtc_time_stamp(*(rt_uint32_t *)args))
+    {
+        result = -RT_ERROR;
+    }
+    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return result;
+}
+
+#ifdef RT_USING_ALARM
+static rt_err_t ra_get_alarm(void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    rtc_alarm_time_t alarm_time_get =
+    {
+        .sec_match        =  RT_FALSE,
+        .min_match        =  RT_FALSE,
+        .hour_match       =  RT_FALSE,
+        .mday_match       =  RT_FALSE,
+        .mon_match        =  RT_FALSE,
+        .year_match       =  RT_FALSE,
+        .dayofweek_match  =  RT_FALSE,
+    };
+
+    if (RT_EOK == R_RTC_CalendarAlarmGet(&g_rtc_ctrl, &alarm_time_get))
+    {
+        wkalarm->tm_hour = alarm_time_get.time.tm_hour;
+        wkalarm->tm_min  = alarm_time_get.time.tm_min;
+        wkalarm->tm_sec  = alarm_time_get.time.tm_sec;
+    }
+    else
+    {
+        LOG_E("Calendar alarm Get failed.");
+    }
+
+    return result;
+}
+
+static rt_err_t ra_set_alarm(void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    rtc_alarm_time_t alarm_time_set =
+    {
+        .sec_match        =  RT_TRUE,
+        .min_match        =  RT_TRUE,
+        .hour_match       =  RT_TRUE,
+        .mday_match       =  RT_FALSE,
+        .mon_match        =  RT_FALSE,
+        .year_match       =  RT_FALSE,
+        .dayofweek_match  =  RT_FALSE,
+    };
+
+    alarm_time_set.time.tm_hour = wkalarm->tm_hour;
+    alarm_time_set.time.tm_min  = wkalarm->tm_min;
+    alarm_time_set.time.tm_sec  = wkalarm->tm_sec;
+    if (1 == wkalarm->enable)
+    {
+        if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
+        {
+            LOG_E("Calendar alarm Set failed.");
+            result = -RT_ERROR;
+        }
+    }
+    else
+    {
+        alarm_time_set.sec_match        =  RT_FALSE;
+        alarm_time_set.min_match        =  RT_FALSE;
+        alarm_time_set.hour_match       =  RT_FALSE;
+        if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
+        {
+            LOG_E("Calendar alarm Stop failed.");
+            result = -RT_ERROR;
+        }
+    }
+    return result;
+}
+#endif /* RT_USING_ALARM */
+
+void rtc_callback(rtc_callback_args_t *p_args)
+{
+#ifdef RT_USING_ALARM
+    static rt_device_t ra_device;
+    if (RTC_EVENT_ALARM_IRQ == p_args->event)
+    {
+        rt_alarm_update(ra_device, 1);
+    }
+#endif
+}
+
+static const struct rt_rtc_ops ra_rtc_ops =
+{
+    .init      = ra_rtc_init,
+    .get_secs  = ra_get_secs,
+    .set_secs  = ra_set_secs,
+#ifdef RT_USING_ALARM
+    .set_alarm = ra_set_alarm,
+    .get_alarm = ra_get_alarm,
+#endif
+};
+
+static rt_rtc_dev_t ra_rtc_dev;
+
+static int rt_hw_rtc_init(void)
+{
+    rt_err_t result;
+
+    ra_rtc_dev.ops = &ra_rtc_ops;
+
+    result = rt_hw_rtc_register(&ra_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
+    if (result != RT_EOK)
+    {
+        LOG_E("rtc register err code: %d", result);
+        return result;
+    }
+    LOG_D("rtc init success");
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif

bsp/ra6m4-cpk/drivers/drv_soft_i2c.c

@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#include "board.h"
+#include "drv_soft_i2c.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_I2C
+
+#define DBG_TAG              "drv.i2c"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
+    #error "Please define at least one BSP_USING_I2Cx"
+    /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
+#endif
+
+static const struct ra_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_I2C0
+    I2C0_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C1
+    I2C1_BUS_CONFIG,
+#endif
+};
+
+static struct ra_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param ra i2c dirver class.
+ */
+static void ra_i2c_gpio_init(struct ra_i2c *i2c)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param ra config class.
+ * @param The sda pin state.
+ */
+static void ra_set_sda(void *data, rt_int32_t state)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param ra config class.
+ * @param The scl pin state.
+ */
+static void ra_set_scl(void *data, rt_int32_t state)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t ra_get_sda(void *data)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t ra_get_scl(void *data)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    return rt_pin_read(cfg->scl);
+}
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void ra_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops ra_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = ra_set_sda,
+    .set_scl  = ra_set_scl,
+    .get_sda  = ra_get_sda,
+    .get_scl  = ra_get_scl,
+    .udelay   = ra_udelay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param ra config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t ra_i2c_bus_unlock(const struct ra_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            ra_udelay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            ra_udelay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ra_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = ra_bit_ops_default;
+        i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        ra_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        ra_i2c_bus_unlock(&soft_i2c_config[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              soft_i2c_config[i].bus_name,
+              soft_i2c_config[i].scl,
+              soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */

bsp/ra6m4-cpk/drivers/drv_soft_i2c.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+/* ra config class */
+struct ra_soft_i2c_config
+{
+    rt_uint32_t scl;
+    rt_uint32_t sda;
+    const char *bus_name;
+};
+/* ra i2c dirver class */
+struct ra_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C1_SCL_PIN,                         \
+        .sda = BSP_I2C1_SDA_PIN,                         \
+        .bus_name = "i2c1",                              \
+    }
+#endif
+
+#ifdef BSP_USING_I2C2
+#define I2C2_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C2_SCL_PIN,                         \
+        .sda = BSP_I2C2_SDA_PIN,                         \
+        .bus_name = "i2c2",                              \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif

bsp/ra6m4-cpk/drivers/drv_spi.c

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     Mr.Tiger     first version
+ */
+/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
+
+#include "drv_spi.h"
+
+#ifdef RT_USING_SPI
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.spi"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static struct ra_spi_handle spi_handle[] =
+{
+#ifdef BSP_USING_SPI0
+    {.bus_name = "spi0", .spi_ctrl_t = &g_spi0_ctrl, .spi_cfg_t = &g_spi0_cfg,},
+#endif
+
+#ifdef BSP_USING_SPI1
+    {.bus_name = "spi1", .spi_ctrl_t = &g_spi1_ctrl, .spi_cfg_t = &g_spi1_cfg,},
+#endif
+};
+
+static struct ra_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
+
+void g_spi0_callback(spi_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
+    {
+        LOG_D("SPI0 cb");
+    }
+    rt_interrupt_leave();
+}
+
+void g_spi1_callback(spi_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
+    {
+        LOG_D("SPI1 cb");
+    }
+    rt_interrupt_leave();
+}
+
+static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device->parent.user_data != NULL);
+    RT_ASSERT(send_buf != NULL);
+    RT_ASSERT(len > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+    spi_dev->cs_pin = *(rt_uint32_t *)device->parent.user_data;
+
+    /**< Configure Select Line */
+    R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
+
+    /* Start a write transfer */
+    R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_LOW);
+
+    /**< send msessage */
+    err = R_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, spi_dev->rt_spi_cfg_t->data_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s write failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+
+    return len;
+}
+
+static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device->parent.user_data != NULL);
+    RT_ASSERT(recv_buf != NULL);
+    RT_ASSERT(len > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+    spi_dev->cs_pin = *(rt_uint32_t *)device->parent.user_data;
+
+    /**< Configure Select Line */
+    R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
+
+    /* Start read transfer */
+    R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_LOW);
+
+    /**< receive message */
+    err = R_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, spi_dev->rt_spi_cfg_t->data_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("\n%s write failed.\n", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+
+    return len;
+}
+
+static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+    RT_ASSERT(message->length > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+
+    /**< write and receive message */
+    err = R_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, spi_dev->rt_spi_cfg_t->data_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s write and read failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+
+    return message->length;
+}
+
+/**< init spi TODO : MSB does not support modification */
+static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
+                                    struct rt_spi_configuration *configuration)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(configuration != NULL);
+    rt_err_t err = RT_EOK;
+
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+    spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
+
+    /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
+    rt_uint8_t data_width = configuration->data_width / 8;
+    RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
+    configuration->data_width = configuration->data_width / 8;
+    spi_dev->rt_spi_cfg_t = configuration;
+
+    spi_extended_cfg_t *spi_cfg = (spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
+
+    /**< Configure Select Line */
+    R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
+
+    /**< config bitrate */
+    R_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->spck_div);
+
+    /**< init */
+    err = R_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
+    /* handle error */
+    if (RT_EOK != err)
+    {
+        LOG_E("%s init failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_uint32_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+    rt_err_t err = RT_EOK;
+
+    if (message->length <= 0)
+    {
+        LOG_E("buf length err.");
+    }
+    else
+    {
+        if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< receive message */
+            err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
+        {
+            /**< send message */
+            err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< send and receive message */
+            err =  ra_write_read_message(device, message);
+        }
+    }
+    return err;
+}
+
+static const struct rt_spi_ops ra_spi_ops =
+{
+    .configure = ra_hw_spi_configure,
+    .xfer = ra_spixfer,
+};
+
+void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device_name != NULL);
+    RT_ASSERT(bus_name != NULL);
+    RT_ASSERT(user_data != NULL);
+
+    rt_err_t err = rt_spi_bus_attach_device(device, device_name, bus_name, user_data);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s attach failed.", bus_name);
+    }
+}
+
+int ra_hw_spi_init(void)
+{
+    for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
+    {
+        spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
+
+        /**< register spi bus */
+        rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
+        if (RT_EOK != err)
+        {
+            LOG_E("%s bus register failed.", spi_config[spi_index].ra_spi_handle_t->bus_name);
+        }
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(ra_hw_spi_init);
+#endif /* RT_USING_SPI */

bsp/ra6m4-cpk/drivers/drv_spi.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     Mr.Tiger   first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#include "board.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef R_SPI_H
+struct ra_spi_handle
+{
+    const char *bus_name;
+    const spi_cfg_t           *spi_cfg_t;
+    const spi_instance_ctrl_t *spi_ctrl_t;
+};
+
+struct ra_spi
+{
+    rt_uint32_t                  cs_pin;
+    struct ra_spi_handle        *ra_spi_handle_t;
+    struct rt_spi_configuration *rt_spi_cfg_t;
+    struct rt_spi_bus            bus;
+};
+#endif
+
+void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+/* stm32 spi dirver class */
+
+#endif /*__DRV_SPI_H__ */

bsp/ra6m4-cpk/drivers/drv_usart_v2.c

@@ -15,9 +15,9 @@
 //#define DRV_DEBUG
 #define DBG_TAG              "drv.usart"
 #ifdef DRV_DEBUG
-#define DBG_LVL               DBG_LOG
+    #define DBG_LVL               DBG_LOG
 #else
-#define DBG_LVL               DBG_INFO
+    #define DBG_LVL               DBG_INFO
 #endif /* DRV_DEBUG */
 #include <rtdbg.h>
 
@@ -81,7 +81,7 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial
     uart = rt_container_of(serial, struct ra_uart, serial);
     RT_ASSERT(uart != RT_NULL);
 
-    err = R_SCI_UART_Open (uart->config->p_api_ctrl, uart->config->p_cfg);
+    err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
     if (FSP_SUCCESS != err)
     {
         return RT_ERROR;
@@ -103,10 +103,10 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c)
     uart = rt_container_of(serial, struct ra_uart, serial);
     RT_ASSERT(uart != RT_NULL);
 
-    sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
+    sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
 
     p_ctrl->p_reg->TDR = c;
-    while((p_ctrl->p_reg->SSR_b.TEND) == 0);
+    while ((p_ctrl->p_reg->SSR_b.TEND) == 0);
 
     return RT_EOK;
 }
@@ -125,13 +125,13 @@ void uart7_isr_cb(uart_callback_args_t *p_args)
     struct rt_serial_device *serial = &uart_obj[0].serial;
     RT_ASSERT(serial != RT_NULL);
 
-    if(UART_EVENT_RX_CHAR == p_args->event)
+    if (UART_EVENT_RX_CHAR == p_args->event)
     {
         struct rt_serial_rx_fifo *rx_fifo;
         rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
         RT_ASSERT(rx_fifo != RT_NULL);
 
-        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t )p_args->data);
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
 
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
     }
@@ -149,13 +149,13 @@ void uart1_isr_cb(uart_callback_args_t *p_args)
     struct rt_serial_device *serial = &uart_obj[1].serial;
     RT_ASSERT(serial != RT_NULL);
 
-    if(UART_EVENT_RX_CHAR == p_args->event)
+    if (UART_EVENT_RX_CHAR == p_args->event)
     {
         struct rt_serial_rx_fifo *rx_fifo;
         rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
         RT_ASSERT(rx_fifo != RT_NULL);
 
-        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t )p_args->data);
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
 
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
     }
@@ -187,9 +187,9 @@ int rt_hw_usart_init(void)
         uart_obj[i].serial.ops = &ra_uart_ops;
         /* register UART device */
         result = rt_hw_serial_register(&uart_obj[i].serial,
-                                        uart_obj[i].config->name,
-                                        RT_DEVICE_FLAG_RDWR,
-                                        NULL);
+                                       uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR,
+                                       NULL);
         RT_ASSERT(result == RT_EOK);
     }
 

bsp/ra6m4-cpk/drivers/drv_usart_v2.h

@@ -22,8 +22,8 @@
 struct ra_uart_config
 {
     const char *name;
-    uart_ctrl_t * const p_api_ctrl;
-    uart_cfg_t const * const p_cfg;
+    uart_ctrl_t *const p_api_ctrl;
+    uart_cfg_t const *const p_cfg;
 };
 
 struct ra_uart

bsp/ra6m4-cpk/drivers/drv_wdt.c

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-20     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+#ifdef RT_USING_WDT
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.wdt"
+#include <rtdbg.h>
+
+static struct rt_watchdog_device ra_wdt_dev;
+static struct rt_watchdog_ops ops;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    struct st_wdt_timeout_values *wdt_value = {0};
+    switch (cmd)
+    {
+    /* feed the watchdog */
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
+        {
+            LOG_E("watch dog keepalive fail.");
+        }
+        break;
+    /* set watchdog timeout */
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        /**< set*/
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        wdt_value = (struct st_wdt_timeout_values *)arg;
+        if (R_WDT_TimeoutGet(&g_wdt_ctrl, wdt_value) != FSP_SUCCESS)
+        {
+            LOG_E("wdt get timeout failed.");
+            return -RT_ERROR;
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        if (R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg) == FSP_SUCCESS)
+        {
+            if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
+            {
+                LOG_E("wdt start failed.");
+                return -RT_ERROR;
+            }
+        }
+        else
+        {
+            LOG_E("wdt start failed.");
+            return -RT_ERROR;
+        }
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int rt_wdt_init(void)
+{
+    ops.init = &wdt_init;
+    ops.control = &wdt_control;
+    ra_wdt_dev.ops = &ops;
+    /* register watchdog device */
+    if (rt_hw_watchdog_register(&ra_wdt_dev, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_wdt_init);
+
+#endif /* RT_USING_WDT */

bsp/ra6m4-cpk/ports/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/ra6m4-cpk/ports/fal/SConscript

@@ -0,0 +1,20 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+src     += Glob('*.c')
+CPPPATH = [cwd]
+LOCAL_CCFLAGS = ''
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    LOCAL_CCFLAGS += ' -std=c99'
+elif rtconfig.CROSS_TOOL == 'keil':
+    LOCAL_CCFLAGS += ' --c99'
+
+group = DefineGroup('FAL', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
+
+Return('group')

bsp/ra6m4-cpk/ports/fal/fal_cfg.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-21     MurphyZhao   the first version
+ */
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable stm32l4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_STM32L4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev _onchip_flash_8k;
+extern const struct fal_flash_dev _onchip_flash_128k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &_onchip_flash_8k,                                               \
+    &_onchip_flash_128k,                                             \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                                                   \
+{                                                                                                                        \
+    {FAL_PART_MAGIC_WROD,        "app", "onchip_flash_8k",                                    0,       64 * 1024, 0},    \
+    {FAL_PART_MAGIC_WROD,      "param", "onchip_flash_128k",                                  0,     3 * 128 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

bsp/ra6m4-cpk/project.uvoptx

@@ -194,8 +194,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName>
-      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\common\div0.c</PathWithFileName>
+      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -206,32 +206,32 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\common\div0.c</PathWithFileName>
-      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>1</GroupNumber>
       <FileNumber>4</FileNumber>
-      <FileType>1</FileType>
+      <FileType>2</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName>
-      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName>
+      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>1</GroupNumber>
       <FileNumber>5</FileNumber>
-      <FileType>2</FileType>
+      <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName>
-      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName>
+      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -250,8 +250,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\serial\serial_v2.c</PathWithFileName>
-      <FilenameWithoutPath>serial_v2.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\misc\pin.c</PathWithFileName>
+      <FilenameWithoutPath>pin.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -262,8 +262,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName>
-      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\serial\serial_v2.c</PathWithFileName>
+      <FilenameWithoutPath>serial_v2.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -274,8 +274,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName>
-      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -286,8 +286,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\completion.c</PathWithFileName>
-      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
+      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -298,8 +298,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
-      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -322,8 +322,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName>
-      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
+      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -334,8 +334,20 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
-      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName>
+      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -343,13 +355,25 @@
 
   <Group>
     <GroupName>Drivers</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>14</FileNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>drivers\drv_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>16</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -361,7 +385,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>15</FileNumber>
+      <FileNumber>17</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -381,7 +405,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>4</GroupNumber>
-      <FileNumber>16</FileNumber>
+      <FileNumber>18</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -393,7 +417,7 @@
     </File>
     <File>
       <GroupNumber>4</GroupNumber>
-      <FileNumber>17</FileNumber>
+      <FileNumber>19</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -405,7 +429,7 @@
     </File>
     <File>
       <GroupNumber>4</GroupNumber>
-      <FileNumber>18</FileNumber>
+      <FileNumber>20</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -425,43 +449,43 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>19</FileNumber>
+      <FileNumber>21</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\mem.c</PathWithFileName>
-      <FilenameWithoutPath>mem.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>20</FileNumber>
+      <FileNumber>22</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
-      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\thread.c</PathWithFileName>
+      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>21</FileNumber>
+      <FileNumber>23</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\components.c</PathWithFileName>
-      <FilenameWithoutPath>components.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\device.c</PathWithFileName>
+      <FilenameWithoutPath>device.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>22</FileNumber>
+      <FileNumber>24</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -473,97 +497,97 @@
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>23</FileNumber>
+      <FileNumber>25</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\device.c</PathWithFileName>
-      <FilenameWithoutPath>device.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\components.c</PathWithFileName>
+      <FilenameWithoutPath>components.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>24</FileNumber>
+      <FileNumber>26</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\object.c</PathWithFileName>
-      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\clock.c</PathWithFileName>
+      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>25</FileNumber>
+      <FileNumber>27</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\idle.c</PathWithFileName>
-      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>26</FileNumber>
+      <FileNumber>28</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\thread.c</PathWithFileName>
-      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\mem.c</PathWithFileName>
+      <FilenameWithoutPath>mem.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>27</FileNumber>
+      <FileNumber>29</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\timer.c</PathWithFileName>
-      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\object.c</PathWithFileName>
+      <FilenameWithoutPath>object.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>28</FileNumber>
+      <FileNumber>30</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\irq.c</PathWithFileName>
-      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
+      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>29</FileNumber>
+      <FileNumber>31</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
-      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\irq.c</PathWithFileName>
+      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>30</FileNumber>
+      <FileNumber>32</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\clock.c</PathWithFileName>
-      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\idle.c</PathWithFileName>
+      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -577,7 +601,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>31</FileNumber>
+      <FileNumber>33</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -591,13 +615,13 @@
 
   <Group>
     <GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>32</FileNumber>
+      <FileNumber>34</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -609,7 +633,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>33</FileNumber>
+      <FileNumber>35</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>

bsp/ra6m4-cpk/project.uvprojx

@@ -80,13 +80,13 @@
             <nStopB2X>0</nStopB2X>
           </BeforeMake>
           <AfterMake>
-            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>cmd /c ""D:\ProgramFiles\Renesas\RA\sc_v2021-04_fsp_v3.1.0\eclipse\rasc.exe" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2&gt; "%%TEMP%%\rasc_stderr.out""</UserProg1Name>
+            <UserProg1Name></UserProg1Name>
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>2</nStopA1X>
+            <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
@@ -339,7 +339,7 @@
               <MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
               <Define>SOC_R7FA6M4AF, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
               <Undefine></Undefine>
-              <IncludePath>..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;drivers;drivers\config;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel</IncludePath>
+              <IncludePath>..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;drivers\config;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -388,31 +388,36 @@
               <FileType>1</FileType>
               <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
-            <File>
-              <FileName>showmem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
-            </File>
             <File>
               <FileName>div0.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
             <File>
-              <FileName>cpuport.c</FileName>
+              <FileName>showmem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
             </File>
             <File>
               <FileName>context_rvds.S</FileName>
               <FileType>2</FileType>
               <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
             </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>DeviceDrivers</GroupName>
           <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
             <File>
               <FileName>serial_v2.c</FileName>
               <FileType>1</FileType>
@@ -424,40 +429,45 @@
               <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
             </File>
             <File>
-              <FileName>waitqueue.c</FileName>
+              <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
+              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
             </File>
             <File>
-              <FileName>completion.c</FileName>
+              <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
             </File>
             <File>
-              <FileName>ringbuffer.c</FileName>
+              <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
             </File>
             <File>
-              <FileName>workqueue.c</FileName>
+              <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
             </File>
             <File>
-              <FileName>dataqueue.c</FileName>
+              <FileName>completion.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
             </File>
             <File>
-              <FileName>ringblk_buf.c</FileName>
+              <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
+              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
           <GroupName>Drivers</GroupName>
           <Files>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_gpio.c</FilePath>
+            </File>
             <File>
               <FileName>drv_usart_v2.c</FileName>
               <FileType>1</FileType>
@@ -494,19 +504,19 @@
           <GroupName>Kernel</GroupName>
           <Files>
             <File>
-              <FileName>mem.c</FileName>
+              <FileName>ipc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
+              <FilePath>..\..\src\ipc.c</FilePath>
             </File>
             <File>
-              <FileName>scheduler.c</FileName>
+              <FileName>thread.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
+              <FilePath>..\..\src\thread.c</FilePath>
             </File>
             <File>
-              <FileName>components.c</FileName>
+              <FileName>device.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\components.c</FilePath>
+              <FilePath>..\..\src\device.c</FilePath>
             </File>
             <File>
               <FileName>kservice.c</FileName>
@@ -514,44 +524,44 @@
               <FilePath>..\..\src\kservice.c</FilePath>
             </File>
             <File>
-              <FileName>device.c</FileName>
+              <FileName>components.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
+              <FilePath>..\..\src\components.c</FilePath>
             </File>
             <File>
-              <FileName>object.c</FileName>
+              <FileName>clock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
+              <FilePath>..\..\src\clock.c</FilePath>
             </File>
             <File>
-              <FileName>idle.c</FileName>
+              <FileName>timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
+              <FilePath>..\..\src\timer.c</FilePath>
             </File>
             <File>
-              <FileName>thread.c</FileName>
+              <FileName>mem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
+              <FilePath>..\..\src\mem.c</FilePath>
             </File>
             <File>
-              <FileName>timer.c</FileName>
+              <FileName>object.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
+              <FilePath>..\..\src\object.c</FilePath>
             </File>
             <File>
-              <FileName>irq.c</FileName>
+              <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
+              <FilePath>..\..\src\scheduler.c</FilePath>
             </File>
             <File>
-              <FileName>ipc.c</FileName>
+              <FileName>irq.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
+              <FilePath>..\..\src\irq.c</FilePath>
             </File>
             <File>
-              <FileName>clock.c</FileName>
+              <FileName>idle.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
+              <FilePath>..\..\src\idle.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/ra6m4-cpk/ra/SConscript

@@ -20,6 +20,9 @@ elif rtconfig.CROSS_TOOL == 'gcc':
     if GetDepend(['RT_USING_SERIAL']):
         src += [cwd + '/fsp/src/r_sci_uart/r_sci_uart.c']
 
+    if GetDepend(['RT_USING_PIN']):
+        src += [cwd + '/fsp/src/r_icu/r_icu.c']
+
     CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
                 cwd + '/fsp/inc',
                 cwd + '/fsp/inc/api',

bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h

@@ -190,7 +190,7 @@
             /* Security attribution for registers for IRQ channels. */
 #ifndef BSP_TZ_CFG_ICUSARA
 #define BSP_TZ_CFG_ICUSARA (\
-            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \

bsp/ra6m4-cpk/ra_gen/hal_data.c

@@ -1,5 +1,29 @@
 /* generated HAL source file - do not edit */
 #include "hal_data.h"
+icu_instance_ctrl_t g_external_irq0_ctrl;
+const external_irq_cfg_t g_external_irq0_cfg =
+{
+    .channel             = 0,
+    .trigger             = EXTERNAL_IRQ_TRIG_RISING,
+    .filter_enable       = false,
+    .pclk_div            = EXTERNAL_IRQ_PCLK_DIV_BY_64,
+    .p_callback          = irq0_callback,
+    .p_context           = NULL,
+    .p_extend            = NULL,
+    .ipl                 = (12),
+#if defined(VECTOR_NUMBER_ICU_IRQ0)
+    .irq                 = VECTOR_NUMBER_ICU_IRQ0,
+#else
+    .irq                 = FSP_INVALID_VECTOR,
+#endif
+};
+/* Instance structure to use this module. */
+const external_irq_instance_t g_external_irq0 =
+{
+    .p_ctrl        = &g_external_irq0_ctrl,
+    .p_cfg         = &g_external_irq0_cfg,
+    .p_api         = &g_external_irq_on_icu
+};
 sci_uart_instance_ctrl_t     g_uart7_ctrl;
 
             baud_setting_t               g_uart7_baud_setting =

bsp/ra6m4-cpk/ra_gen/hal_data.h

@@ -4,9 +4,21 @@
 #include <stdint.h>
 #include "bsp_api.h"
 #include "common_data.h"
+#include "r_icu.h"
+#include "r_external_irq_api.h"
 #include "r_sci_uart.h"
             #include "r_uart_api.h"
 FSP_HEADER
+/** External IRQ on ICU Instance. */
+extern const external_irq_instance_t g_external_irq0;
+
+/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
+extern icu_instance_ctrl_t g_external_irq0_ctrl;
+extern const external_irq_cfg_t g_external_irq0_cfg;
+
+#ifndef irq0_callback
+void irq0_callback(external_irq_callback_args_t * p_args);
+#endif
 /** UART on SCI Instance. */
             extern const uart_instance_t      g_uart7;
 

bsp/ra6m4-cpk/ra_gen/pin_data.c

@@ -38,7 +38,7 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
     },
     {
         .pin = BSP_IO_PORT_00_PIN_14,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
     },
     {
         .pin = BSP_IO_PORT_00_PIN_15,

bsp/ra6m4-cpk/ra_gen/vector_data.c

@@ -8,6 +8,7 @@
             [1] = sci_uart_txi_isr, /* SCI7 TXI (Transmit data empty) */
             [2] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */
             [3] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */
+            [4] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
         };
         const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
         {
@@ -15,5 +16,6 @@
             [1] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TXI), /* SCI7 TXI (Transmit data empty) */
             [2] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */
             [3] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */
+            [4] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
         };
         #endif

bsp/ra6m4-cpk/ra_gen/vector_data.h

@@ -3,19 +3,21 @@
         #define VECTOR_DATA_H
                 /* Number of interrupts allocated */
         #ifndef VECTOR_DATA_IRQ_COUNT
-        #define VECTOR_DATA_IRQ_COUNT    (4)
+        #define VECTOR_DATA_IRQ_COUNT    (5)
         #endif
         /* ISR prototypes */
         void sci_uart_rxi_isr(void);
         void sci_uart_txi_isr(void);
         void sci_uart_tei_isr(void);
         void sci_uart_eri_isr(void);
+        void r_icu_isr(void);
 
         /* Vector table allocations */
         #define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */
         #define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type) 1) /* SCI7 TXI (Transmit data empty) */
         #define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type) 2) /* SCI7 TEI (Transmit end) */
         #define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
+        #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
         typedef enum IRQn {
             Reset_IRQn = -15,
             NonMaskableInt_IRQn = -14,
@@ -32,5 +34,6 @@
             SCI7_TXI_IRQn = 1, /* SCI7 TXI (Transmit data empty) */
             SCI7_TEI_IRQn = 2, /* SCI7 TEI (Transmit end) */
             SCI7_ERI_IRQn = 3, /* SCI7 ERI (Receive error) */
+            ICU_IRQ0_IRQn = 4, /* ICU IRQ0 (External pin interrupt 0) */
         } IRQn_Type;
         #endif /* VECTOR_DATA_H */

bsp/ra6m4-cpk/rtconfig.h

@@ -86,6 +86,7 @@
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V2
 #define RT_SERIAL_USING_DMA
+#define RT_USING_PIN
 
 /* Using USB */
 
@@ -177,6 +178,7 @@
 
 /* On-chip Peripheral Drivers */
 
+#define BSP_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART7
 #define BSP_UART7_RX_BUFSIZE 256

bsp/ra6m4-cpk/src/hal_entry.c

@@ -6,10 +6,15 @@
  * Change Logs:
  * Date           Author        Notes
  * 2021-10-10     Sherman       first version
+ * 2021-11-03     Sherman       Add icu_sample
  */
 
 #include <rtthread.h>
 #include "hal_data.h"
+#include <rtdevice.h>
+
+#define LED3_PIN    BSP_IO_PORT_01_PIN_06
+#define USER_INPUT	"P105"
 
 void hal_entry(void)
 {
@@ -17,6 +22,32 @@ void hal_entry(void)
 
     while (1)
     {
-        rt_thread_mdelay(1000);
+        rt_pin_write(LED3_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED3_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+
+void irq_callback_test(void *args)
+{
+    rt_kprintf("\n IRQ00 triggered \n");
+}
+
+void icu_sample(void)
+{
+    /* init */
+    rt_uint32_t pin = rt_pin_get(USER_INPUT);
+    rt_kprintf("\n pin number : 0x%04X \n", pin);
+    rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, irq_callback_test, RT_NULL);
+    if(RT_EOK != err)
+    {
+        rt_kprintf("\n attach irq failed. \n");
+    }
+    err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
+    if(RT_EOK != err)
+    {
+        rt_kprintf("\n enable irq failed. \n");
     }
-}
+}
+MSH_CMD_EXPORT(icu_sample, icu sample);

bsp/ra6m4-cpk/template.uvoptx

@@ -179,7 +179,7 @@
 
   <Group>
     <GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>

bsp/ra6m4-cpk/template.uvprojx

@@ -79,13 +79,13 @@
             <nStopB2X>0</nStopB2X>
           </BeforeMake>
           <AfterMake>
-            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>cmd /c ""D:\ProgramFiles\Renesas\RA\sc_v2021-04_fsp_v3.1.0\eclipse\rasc.exe" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2&gt; "%%TEMP%%\rasc_stderr.out""</UserProg1Name>
+            <UserProg1Name></UserProg1Name>
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>2</nStopA1X>
+            <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>