format files in zynqmp-r5-axu4ev bsp

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c

@@ -81,27 +81,27 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
 			   UINTPTR EffectiveAddress)
 {
 	/* Verify arguments */
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(CfgPtr != NULL);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(CfgPtr != NULL);
 
 	/* Set device base address and ID */
-	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddress;
-	InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+    InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+    InstancePtr->Config.BaseAddress = EffectiveAddress;
+    InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
 #if defined  (XCLOCKING)
-	InstancePtr->Config.RefClk = CfgPtr->RefClk;
+    InstancePtr->Config.RefClk = CfgPtr->RefClk;
 #endif
 
 	/* Set callbacks to an initial stub routine */
-	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
-	InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
-	InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+    InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+    InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+    InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
 
 	/* Reset the hardware and set default options */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-	XEmacPs_Reset(InstancePtr);
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+    XEmacPs_Reset(InstancePtr);
 
-	return (LONG)(XST_SUCCESS);
+    return (LONG)(XST_SUCCESS);
 }
 
 
@@ -134,15 +134,15 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
 ******************************************************************************/
 void XEmacPs_Start(XEmacPs *InstancePtr)
 {
-	u32 Reg;
+    u32 Reg;
 
 	/* Assert bad arguments and conditions */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
 #if defined  (XCLOCKING)
-	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
-		Xil_ClockEnable(InstancePtr->Config.RefClk);
+    if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+	    Xil_ClockEnable(InstancePtr->Config.RefClk);
 	}
 #endif
 
@@ -150,39 +150,39 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
 	/* When starting the DMA channels, both transmit and receive sides
 	 * need an initialized BD list.
 	 */
-	if (InstancePtr->Version == 2) {
-		Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
-		Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    if (InstancePtr->Version == 2) {
+	    Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+	    Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_RXQBASE_OFFSET,
 			   InstancePtr->RxBdRing.BaseBdAddr);
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_TXQBASE_OFFSET,
 			   InstancePtr->TxBdRing.BaseBdAddr);
 	}
 
 	/* clear any existed int status */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 			   XEMACPS_IXR_ALL_MASK);
 
 	/* Enable transmitter if not already enabled */
-	if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+	    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_NWCTRL_OFFSET);
+	    if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 					   XEMACPS_NWCTRL_OFFSET,
 				   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
 		}
 	}
 
 	/* Enable receiver if not already enabled */
-	if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
-		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-		if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+	    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_NWCTRL_OFFSET);
+	    if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 					   XEMACPS_NWCTRL_OFFSET,
 				   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
 		}
@@ -190,17 +190,17 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
 
         /* Enable TX and RX interrupts */
         XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
-	XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+    XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
 	(u32)XEMACPS_IXR_TXCOMPL_MASK));
 
 	/* Enable TX Q1 Interrupts */
-	if (InstancePtr->Version > 2)
-		XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+    if (InstancePtr->Version > 2)
+	    XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
 
 	/* Mark as started */
-	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+    InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
 
-	return;
+    return;
 }
 
 
@@ -231,27 +231,27 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
 ******************************************************************************/
 void XEmacPs_Stop(XEmacPs *InstancePtr)
 {
-	u32 Reg;
+    u32 Reg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
 	/* Disable all interrupts */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
 			   XEMACPS_IXR_ALL_MASK);
 
 	/* Disable the receiver & transmitter */
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCTRL_OFFSET);
-	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
-	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_NWCTRL_OFFSET);
+    Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+    Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_NWCTRL_OFFSET, Reg);
 
 	/* Mark as stopped */
-	InstancePtr->IsStarted = 0U;
+    InstancePtr->IsStarted = 0U;
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
 }
 
@@ -290,53 +290,53 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
 ******************************************************************************/
 void XEmacPs_Reset(XEmacPs *InstancePtr)
 {
-	u32 Reg;
-	u8 i;
-	s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+    u32 Reg;
+    u8 i;
+    s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
 	/* Stop the device and reset hardware */
-	XEmacPs_Stop(InstancePtr);
-	InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+    XEmacPs_Stop(InstancePtr);
+    InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
 
-	InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+    InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
 
-	InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+    InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
 
-	InstancePtr->MaxMtuSize = XEMACPS_MTU;
-	InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
-					XEMACPS_TRL_SIZE;
-	InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
-					XEMACPS_HDR_VLAN_SIZE;
-	InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+    InstancePtr->MaxMtuSize = XEMACPS_MTU;
+    InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+				    XEMACPS_TRL_SIZE;
+    InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+				    XEMACPS_HDR_VLAN_SIZE;
+    InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
 
 	/* Setup hardware with default values */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCTRL_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+		    XEMACPS_NWCTRL_OFFSET,
 			(XEMACPS_NWCTRL_STATCLR_MASK |
-			XEMACPS_NWCTRL_MDEN_MASK) &
+		    XEMACPS_NWCTRL_MDEN_MASK) &
 			(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
 
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_NWCFG_OFFSET);
-	Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+		    XEMACPS_NWCFG_OFFSET);
+    Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
 
-	Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+    Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
 			(u32)XEMACPS_NWCFG_FDEN_MASK |
 			(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCFG_OFFSET, Reg);
-	if (InstancePtr->Version > 2) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_NWCFG_OFFSET, Reg);
+    if (InstancePtr->Version > 2) {
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
 			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
-				XEMACPS_NWCFG_DWIDTH_64_MASK));
+			    XEMACPS_NWCFG_DWIDTH_64_MASK));
 	}
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_DMACR_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+		    XEMACPS_DMACR_OFFSET,
 			(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
 				(((((u32)XEMACPS_RX_BUF_SIZE %
 				(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
@@ -346,8 +346,8 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
 				(u32)XEMACPS_DMACR_TXSIZE_MASK);
 
 
-	if (InstancePtr->Version > 2) {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+    if (InstancePtr->Version > 2) {
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
 			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
 #if defined(__aarch64__) || defined(__arch64__)
 			(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
@@ -355,44 +355,44 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
 			(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
 	}
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
 
-	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
-	if (InstancePtr->Version > 2)
-		XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
-	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+    XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+    if (InstancePtr->Version > 2)
+	    XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+    XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
 
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
 			   XEMACPS_IXR_ALL_MASK);
 
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_ISR_OFFSET);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_ISR_OFFSET);
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 			   Reg);
 
-	XEmacPs_ClearHash(InstancePtr);
+    XEmacPs_ClearHash(InstancePtr);
 
-	for (i = 1U; i < 5U; i++) {
+    for (i = 1U; i < 5U; i++) {
 		(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
 		(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
 	}
 
 	/* clear all counters */
-	for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+    for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
 	     i++) {
 		(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
                                    XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
 	}
 
 	/* Disable the receiver */
-	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_NWCTRL_OFFSET);
-	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_NWCTRL_OFFSET);
+    Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 			   XEMACPS_NWCTRL_OFFSET, Reg);
 
 	/* Sync default options with hardware but leave receiver and
@@ -418,17 +418,17 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
  ******************************************************************************/
 void XEmacPs_StubHandler(void)
 {
-	Xil_AssertVoidAlways();
+    Xil_AssertVoidAlways();
 }
 
 /*****************************************************************************/
 /**
 * This function sets the start address of the transmit/receive buffer queue.
 *
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	QPtr is the address of the Queue to be written
-* @param	QueueNum is the Buffer Queue Index
-* @param	Direction indicates Transmit/Receive
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    QPtr is the address of the Queue to be written
+* @param    QueueNum is the Buffer Queue Index
+* @param    Direction indicates Transmit/Receive
 *
 * @note
 * The buffer queue addresses has to be set before starting the transfer, so
@@ -439,40 +439,40 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
 			 u16 Direction)
 {
 	/* Assert bad arguments and conditions */
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
         /* If already started, then there is nothing to do */
         if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
                 return;
         }
 
-	if (QueueNum == 0x00U) {
-		if (Direction == XEMACPS_SEND) {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_TXQBASE_OFFSET,
+    if (QueueNum == 0x00U) {
+	    if (Direction == XEMACPS_SEND) {
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_TXQBASE_OFFSET,
 				(QPtr & ULONG64_LO_MASK));
 		} else {
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_RXQBASE_OFFSET,
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_RXQBASE_OFFSET,
 				(QPtr & ULONG64_LO_MASK));
 		}
 	}
 	 else {
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_TXQ1BASE_OFFSET,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+		    XEMACPS_TXQ1BASE_OFFSET,
 			(QPtr & ULONG64_LO_MASK));
 	}
 #ifdef __aarch64__
-	if (Direction == XEMACPS_SEND) {
+    if (Direction == XEMACPS_SEND) {
 		/* Set the MSB of TX Queue start address */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_MSBBUF_TXQBASE_OFFSET,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_MSBBUF_TXQBASE_OFFSET,
 				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
 	} else {
 		/* Set the MSB of RX Queue start address */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				XEMACPS_MSBBUF_RXQBASE_OFFSET,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			    XEMACPS_MSBBUF_RXQBASE_OFFSET,
 				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
 	}
 #endif

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h

@@ -265,7 +265,7 @@
  *		       removed. It is expected that all BDs are allocated in
  *		       from uncached area.
  * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- *				to 0x1fff. This fixes the CR#744902.
+ *			    to 0x1fff. This fixes the CR#744902.
  *			  Made changes in example file xemacps_example.h to fix compilation
  *			  issues with iarcc compiler.
  * 2.0   adk  10/12/13 Updated as per the New Tcl API's
@@ -412,8 +412,8 @@ extern "C" {
 /**< Enable the TX checksum offload
  *   This option defaults to enabled (set) */
 
-#define XEMACPS_JUMBO_ENABLE_OPTION	0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
+#define XEMACPS_JUMBO_ENABLE_OPTION    0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION    0x00008000U
 
 #define XEMACPS_DEFAULT_OPTIONS                     \
     ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
@@ -463,10 +463,10 @@ extern "C" {
 
 /* DMACR Bust length hash defines */
 
-#define XEMACPS_SINGLE_BURST	0x00000001
-#define XEMACPS_4BYTE_BURST		0x00000004
-#define XEMACPS_8BYTE_BURST		0x00000008
-#define XEMACPS_16BYTE_BURST	0x00000010
+#define XEMACPS_SINGLE_BURST    0x00000001
+#define XEMACPS_4BYTE_BURST	    0x00000004
+#define XEMACPS_8BYTE_BURST	    0x00000008
+#define XEMACPS_16BYTE_BURST    0x00000010
 
 
 /**************************** Type Definitions ******************************/
@@ -507,12 +507,12 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
  * This typedef contains configuration information for a device.
  */
 typedef struct {
-	u16 DeviceId;	/**< Unique ID  of device */
-	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
-	u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+    u16 DeviceId;	/**< Unique ID  of device */
+    UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+    u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
 				* describes whether Cache Coherent or not */
 #if defined  (XCLOCKING)
-	u32 RefClk;	/**< Input clock */
+    u32 RefClk;	/**< Input clock */
 #endif
 } XEmacPs_Config;
 
@@ -523,26 +523,26 @@ typedef struct {
  * to a structure of this type is then passed to the driver API functions.
  */
 typedef struct XEmacPs_Instance {
-	XEmacPs_Config Config;	/* Hardware configuration */
-	u32 IsStarted;		/* Device is currently started */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 Options;		/* Current options word */
-
-	XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
-	XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
-
-	XEmacPs_Handler SendHandler;
-	XEmacPs_Handler RecvHandler;
-	void *SendRef;
-	void *RecvRef;
-
-	XEmacPs_ErrHandler ErrorHandler;
-	void *ErrorRef;
-	u32 Version;
-	u32 RxBufMask;
-	u32 MaxMtuSize;
-	u32 MaxFrameSize;
-	u32 MaxVlanFrameSize;
+    XEmacPs_Config Config;	/* Hardware configuration */
+    u32 IsStarted;		/* Device is currently started */
+    u32 IsReady;		/* Device is initialized and ready */
+    u32 Options;		/* Current options word */
+
+    XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
+    XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
+
+    XEmacPs_Handler SendHandler;
+    XEmacPs_Handler RecvHandler;
+    void *SendRef;
+    void *RecvRef;
+
+    XEmacPs_ErrHandler ErrorHandler;
+    void *ErrorRef;
+    u32 Version;
+    u32 RxBufMask;
+    u32 MaxMtuSize;
+    u32 MaxFrameSize;
+    u32 MaxVlanFrameSize;
 
 } XEmacPs;
 
@@ -598,8 +598,8 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IntEnable(InstancePtr, Mask)                            \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IER_OFFSET,                                     \
+    XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+	    XEMACPS_IER_OFFSET,                                     \
 		((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
@@ -619,8 +619,8 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IntDisable(InstancePtr, Mask)                           \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IDR_OFFSET,                                     \
+    XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+	    XEMACPS_IDR_OFFSET,                                     \
 		((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
@@ -640,8 +640,8 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IER_OFFSET,                                \
+    XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+	    XEMACPS_INTQ1_IER_OFFSET,                                \
 		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
@@ -661,8 +661,8 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
-	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IDR_OFFSET,                               \
+    XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+	    XEMACPS_INTQ1_IDR_OFFSET,                               \
 		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
@@ -750,7 +750,7 @@ typedef struct XEmacPs_Instance {
 * @note
 *
 * Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* 					u16 Low)
+* 				    u16 Low)
 *
 *****************************************************************************/
 #define XEmacPs_SetRXWatermark(InstancePtr, High, Low)                     \
@@ -797,7 +797,7 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
  * DMA only and FIFO is not supported. This DMA does not support coalescing.
  */
 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-			void *FuncPointer, void *CallBackRef);
+		    void *FuncPointer, void *CallBackRef);
 void XEmacPs_IntrHandler(void *XEmacPsPtr);
 
 /*
@@ -816,7 +816,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
 
 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
-				XEmacPs_MdcDiv Divisor);
+			    XEmacPs_MdcDiv Divisor);
 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
 LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c

@@ -176,49 +176,49 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
 LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
 			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
 {
-	u32 i;
-	UINTPTR BdVirtAddr;
-	UINTPTR BdPhyAddr;
-	UINTPTR VirtAddrLoc = VirtAddr;
+    u32 i;
+    UINTPTR BdVirtAddr;
+    UINTPTR BdPhyAddr;
+    UINTPTR VirtAddrLoc = VirtAddr;
 
 	/* In case there is a failure prior to creating list, make sure the
 	 * following attributes are 0 to prevent calls to other functions
 	 * from doing anything.
 	 */
-	RingPtr->AllCnt = 0U;
-	RingPtr->FreeCnt = 0U;
-	RingPtr->HwCnt = 0U;
-	RingPtr->PreCnt = 0U;
-	RingPtr->PostCnt = 0U;
+    RingPtr->AllCnt = 0U;
+    RingPtr->FreeCnt = 0U;
+    RingPtr->HwCnt = 0U;
+    RingPtr->PreCnt = 0U;
+    RingPtr->PostCnt = 0U;
 
 	/* Make sure Alignment parameter meets minimum requirements */
-	if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
-		return (LONG)(XST_INVALID_PARAM);
+    if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Make sure Alignment is a power of 2 */
-	if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
-		return (LONG)(XST_INVALID_PARAM);
+    if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Make sure PhysAddr and VirtAddr are on same Alignment */
-	if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
-		return (LONG)(XST_INVALID_PARAM);
+    if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Is BdCount reasonable? */
-	if (BdCount == 0x00000000U) {
-		return (LONG)(XST_INVALID_PARAM);
+    if (BdCount == 0x00000000U) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Figure out how many bytes will be between the start of adjacent BDs */
-	RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+    RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
 
 	/* Must make sure the ring doesn't span address 0x00000000. If it does,
 	 * then the next/prev BD traversal macros will fail.
 	 */
-	if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
 	/* Initial ring setup:
@@ -227,30 +227,30 @@ LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
 	 */
 	(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
 
-	BdVirtAddr = VirtAddrLoc;
-	BdPhyAddr = PhysAddr + RingPtr->Separation;
-	for (i = 1U; i < BdCount; i++) {
-		BdVirtAddr += RingPtr->Separation;
-		BdPhyAddr += RingPtr->Separation;
+    BdVirtAddr = VirtAddrLoc;
+    BdPhyAddr = PhysAddr + RingPtr->Separation;
+    for (i = 1U; i < BdCount; i++) {
+	    BdVirtAddr += RingPtr->Separation;
+	    BdPhyAddr += RingPtr->Separation;
 	}
 
 	/* Setup and initialize pointers and counters */
-	RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
-	RingPtr->BaseBdAddr = VirtAddrLoc;
-	RingPtr->PhysBaseAddr = PhysAddr;
-	RingPtr->HighBdAddr = BdVirtAddr;
-	RingPtr->Length =
+    RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+    RingPtr->BaseBdAddr = VirtAddrLoc;
+    RingPtr->PhysBaseAddr = PhysAddr;
+    RingPtr->HighBdAddr = BdVirtAddr;
+    RingPtr->Length =
 		((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
-	RingPtr->AllCnt = (u32)BdCount;
-	RingPtr->FreeCnt = (u32)BdCount;
-	RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
-	RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
-	RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
-
-	return (LONG)(XST_SUCCESS);
+    RingPtr->AllCnt = (u32)BdCount;
+    RingPtr->FreeCnt = (u32)BdCount;
+    RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+    RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+    RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+    RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+    RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+    RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+    return (LONG)(XST_SUCCESS);
 }
 
 
@@ -281,47 +281,47 @@ LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
 LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
 			 u8 Direction)
 {
-	u32 i;
-	UINTPTR CurBd;
+    u32 i;
+    UINTPTR CurBd;
 
 	/* Can't do this function if there isn't a ring */
-	if (RingPtr->AllCnt == 0x00000000U) {
-		return (LONG)(XST_DMA_SG_NO_LIST);
+    if (RingPtr->AllCnt == 0x00000000U) {
+	    return (LONG)(XST_DMA_SG_NO_LIST);
 	}
 
 	/* Can't do this function with the channel running */
-	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-		return (LONG)(XST_DEVICE_IS_STARTED);
+    if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+	    return (LONG)(XST_DEVICE_IS_STARTED);
 	}
 
 	/* Can't do this function with some of the BDs in use */
-	if (RingPtr->FreeCnt != RingPtr->AllCnt) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
-	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-		return (LONG)(XST_INVALID_PARAM);
+    if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Starting from the top of the ring, save BD.Next, overwrite the entire
 	 * BD with the template, then restore BD.Next
 	 */
-	CurBd = RingPtr->BaseBdAddr;
-	for (i = 0U; i < RingPtr->AllCnt; i++) {
-		memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
-	CurBd += RingPtr->Separation;
+    CurBd = RingPtr->BaseBdAddr;
+    for (i = 0U; i < RingPtr->AllCnt; i++) {
+	    memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+    CurBd += RingPtr->Separation;
 	}
 
-	CurBd -= RingPtr->Separation;
+    CurBd -= RingPtr->Separation;
 
-	if (Direction == XEMACPS_RECV) {
-		XEmacPs_BdSetRxWrap(CurBd);
+    if (Direction == XEMACPS_RECV) {
+	    XEmacPs_BdSetRxWrap(CurBd);
 	}
-	else {
-		XEmacPs_BdSetTxWrap(CurBd);
+    else {
+	    XEmacPs_BdSetTxWrap(CurBd);
 	}
 
-	return (LONG)(XST_SUCCESS);
+    return (LONG)(XST_SUCCESS);
 }
 
 
@@ -400,19 +400,19 @@ LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
 LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
 			 XEmacPs_Bd ** BdSetPtr)
 {
-	LONG Status;
+    LONG Status;
 	/* Enough free BDs available for the request? */
-	if (RingPtr->FreeCnt < NumBd) {
-		Status = (LONG)(XST_FAILURE);
+    if (RingPtr->FreeCnt < NumBd) {
+	    Status = (LONG)(XST_FAILURE);
 	} else {
 	/* Set the return argument and move FreeHead forward */
 	*BdSetPtr = RingPtr->FreeHead;
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
-	RingPtr->FreeCnt -= NumBd;
-	RingPtr->PreCnt += NumBd;
-		Status = (LONG)(XST_SUCCESS);
+    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+    RingPtr->FreeCnt -= NumBd;
+    RingPtr->PreCnt += NumBd;
+	    Status = (LONG)(XST_SUCCESS);
 	}
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -480,22 +480,22 @@ LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
 LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
 			   XEmacPs_Bd * BdSetPtr)
 {
-	LONG Status;
+    LONG Status;
 	(void) BdSetPtr;
-	Xil_AssertNonvoid(RingPtr != NULL);
-	Xil_AssertNonvoid(BdSetPtr != NULL);
+    Xil_AssertNonvoid(RingPtr != NULL);
+    Xil_AssertNonvoid(BdSetPtr != NULL);
 
 	/* Enough BDs in the free state for the request? */
-	if (RingPtr->PreCnt < NumBd) {
-		Status = (LONG)(XST_FAILURE);
+    if (RingPtr->PreCnt < NumBd) {
+	    Status = (LONG)(XST_FAILURE);
 	} else {
 	/* Set the return argument and move FreeHead backward */
-		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
-	RingPtr->FreeCnt += NumBd;
-	RingPtr->PreCnt -= NumBd;
-		Status = (LONG)(XST_SUCCESS);
+	    XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+    RingPtr->FreeCnt += NumBd;
+    RingPtr->PreCnt -= NumBd;
+	    Status = (LONG)(XST_SUCCESS);
 	}
-	return Status;
+    return Status;
 }
 
 
@@ -526,33 +526,33 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr)
+		    XEmacPs_Bd * BdSetPtr)
 {
-	XEmacPs_Bd *CurBdPtr;
-	u32 i;
-	LONG Status;
+    XEmacPs_Bd *CurBdPtr;
+    u32 i;
+    LONG Status;
 	/* if no bds to process, simply return. */
-	if (0U == NumBd){
-		Status = (LONG)(XST_SUCCESS);
+    if (0U == NumBd){
+	    Status = (LONG)(XST_SUCCESS);
 	} else {
 	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
-	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
-			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+    if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+		    Status = (LONG)(XST_DMA_SG_LIST_ERROR);
 		} else {
-	CurBdPtr = BdSetPtr;
-			for (i = 0U; i < NumBd; i++) {
-				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+    CurBdPtr = BdSetPtr;
+		    for (i = 0U; i < NumBd; i++) {
+			    CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
 	}
 	/* Adjust ring pointers & counters */
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
-	RingPtr->PreCnt -= NumBd;
-	RingPtr->HwTail = CurBdPtr;
-	RingPtr->HwCnt += NumBd;
+    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+    RingPtr->PreCnt -= NumBd;
+    RingPtr->HwTail = CurBdPtr;
+    RingPtr->HwCnt += NumBd;
 
-			Status = (LONG)(XST_SUCCESS);
+		    Status = (LONG)(XST_SUCCESS);
 		}
 	}
-	return Status;
+    return Status;
 }
 
 
@@ -625,25 +625,25 @@ LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
 u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 				 XEmacPs_Bd ** BdSetPtr)
 {
-	XEmacPs_Bd *CurBdPtr;
-	u32 BdStr = 0U;
-	u32 BdCount;
-	u32 BdPartialCount;
-	u32 Sop = 0U;
-	u32 Status;
-	u32 BdLimitLoc = BdLimit;
-	CurBdPtr = RingPtr->HwHead;
-	BdCount = 0U;
-	BdPartialCount = 0U;
+    XEmacPs_Bd *CurBdPtr;
+    u32 BdStr = 0U;
+    u32 BdCount;
+    u32 BdPartialCount;
+    u32 Sop = 0U;
+    u32 Status;
+    u32 BdLimitLoc = BdLimit;
+    CurBdPtr = RingPtr->HwHead;
+    BdCount = 0U;
+    BdPartialCount = 0U;
 
 	/* If no BDs in work group, then there's nothing to search */
-	if (RingPtr->HwCnt == 0x00000000U) {
+    if (RingPtr->HwCnt == 0x00000000U) {
 		*BdSetPtr = NULL;
-		Status = 0U;
+	    Status = 0U;
 	} else {
 
-		if (BdLimitLoc > RingPtr->HwCnt){
-			BdLimitLoc = RingPtr->HwCnt;
+	    if (BdLimitLoc > RingPtr->HwCnt){
+		    BdLimitLoc = RingPtr->HwCnt;
 	}
 	/* Starting at HwHead, keep moving forward in the list until:
 	 *  - A BD is encountered with its new/used bit set which means
@@ -651,31 +651,31 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
 	 *  - The number of requested BDs has been processed
 	 */
-		while (BdCount < BdLimitLoc) {
+	    while (BdCount < BdLimitLoc) {
 		/* Read the status */
-			if(CurBdPtr != NULL){
-		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+		    if(CurBdPtr != NULL){
+	    BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
 			}
 
-			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
-				Sop = 1U;
+		    if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+			    Sop = 1U;
 			}
-			if (Sop == 0x00000001U) {
-			BdCount++;
-			BdPartialCount++;
+		    if (Sop == 0x00000001U) {
+		    BdCount++;
+		    BdPartialCount++;
 		}
 
 		/* hardware has processed this BD so check the "last" bit.
 		 * If it is clear, then there are more BDs for the current
 		 * packet. Keep a count of these partial packet BDs.
 		 */
-			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
-				Sop = 0U;
-				BdPartialCount = 0U;
+		    if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+			    Sop = 0U;
+			    BdPartialCount = 0U;
 		}
 
 		/* Move on to next BD in work group */
-		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	    CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
 	}
 
 	/* Subtract off any partial packet BDs found */
@@ -684,18 +684,18 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 	/* If BdCount is non-zero then BDs were found to return. Set return
 	 * parameters, update pointers and counters, return success
 	 */
-		if (BdCount > 0x00000000U) {
+	    if (BdCount > 0x00000000U) {
 		*BdSetPtr = RingPtr->HwHead;
-		RingPtr->HwCnt -= BdCount;
-		RingPtr->PostCnt += BdCount;
-		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-			Status = (BdCount);
+	    RingPtr->HwCnt -= BdCount;
+	    RingPtr->PostCnt += BdCount;
+	    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+		    Status = (BdCount);
 		} else {
 			*BdSetPtr = NULL;
-			Status = 0U;
+		    Status = 0U;
 	}
 	}
-	return Status;
+    return Status;
 }
 
 
@@ -769,20 +769,20 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 				 XEmacPs_Bd ** BdSetPtr)
 {
-	XEmacPs_Bd *CurBdPtr;
-	u32 BdStr = 0U;
-	u32 BdCount;
-	u32 BdPartialCount;
-	u32 Status;
+    XEmacPs_Bd *CurBdPtr;
+    u32 BdStr = 0U;
+    u32 BdCount;
+    u32 BdPartialCount;
+    u32 Status;
 
-	CurBdPtr = RingPtr->HwHead;
-	BdCount = 0U;
-	BdPartialCount = 0U;
+    CurBdPtr = RingPtr->HwHead;
+    BdCount = 0U;
+    BdPartialCount = 0U;
 
 	/* If no BDs in work group, then there's nothing to search */
-	if (RingPtr->HwCnt == 0x00000000U) {
+    if (RingPtr->HwCnt == 0x00000000U) {
 		*BdSetPtr = NULL;
-		Status = 0U;
+	    Status = 0U;
 	} else {
 
 	/* Starting at HwHead, keep moving forward in the list until:
@@ -791,51 +791,51 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
 	 *  - The number of requested BDs has been processed
 	 */
-	while (BdCount < BdLimit) {
+    while (BdCount < BdLimit) {
 
 		/* Read the status */
-			if(CurBdPtr!=NULL){
-		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+		    if(CurBdPtr!=NULL){
+	    BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
 			}
-			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
-			break;
+		    if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+		    break;
 		}
 
-		BdCount++;
+	    BdCount++;
 
 		/* hardware has processed this BD so check the "last" bit. If
                  * it is clear, then there are more BDs for the current packet.
                  * Keep a count of these partial packet BDs.
 		 */
-			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
-				BdPartialCount = 0U;
+		    if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+			    BdPartialCount = 0U;
 			} else {
-			BdPartialCount++;
+		    BdPartialCount++;
 		}
 
 		/* Move on to next BD in work group */
-		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	    CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
 	}
 
 	/* Subtract off any partial packet BDs found */
-	BdCount -= BdPartialCount;
+    BdCount -= BdPartialCount;
 
 	/* If BdCount is non-zero then BDs were found to return. Set return
 	 * parameters, update pointers and counters, return success
 	 */
-		if (BdCount > 0x00000000U) {
+	    if (BdCount > 0x00000000U) {
 		*BdSetPtr = RingPtr->HwHead;
-		RingPtr->HwCnt -= BdCount;
-		RingPtr->PostCnt += BdCount;
-		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-			Status = (BdCount);
+	    RingPtr->HwCnt -= BdCount;
+	    RingPtr->PostCnt += BdCount;
+	    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+		    Status = (BdCount);
 	}
-	else {
+    else {
 		*BdSetPtr = NULL;
-			Status = 0U;
+		    Status = 0U;
 	}
 }
-	return Status;
+    return Status;
 }
 
 
@@ -860,25 +860,25 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr)
+		    XEmacPs_Bd * BdSetPtr)
 {
-	LONG Status;
+    LONG Status;
 	/* if no bds to process, simply return. */
-	if (0x00000000U == NumBd){
-		Status = (LONG)(XST_SUCCESS);
+    if (0x00000000U == NumBd){
+	    Status = (LONG)(XST_SUCCESS);
 	} else {
 	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
-	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
-			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+    if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+		    Status = (LONG)(XST_DMA_SG_LIST_ERROR);
 		} else {
 	/* Update pointers and counters */
-	RingPtr->FreeCnt += NumBd;
-	RingPtr->PostCnt -= NumBd;
-	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
-			Status = (LONG)(XST_SUCCESS);
+    RingPtr->FreeCnt += NumBd;
+    RingPtr->PostCnt -= NumBd;
+    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+		    Status = (LONG)(XST_SUCCESS);
 		}
 	}
-	return Status;
+    return Status;
 }
 
 
@@ -912,89 +912,89 @@ LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
  *****************************************************************************/
 LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
 {
-	UINTPTR AddrV, AddrP;
-	u32 i;
+    UINTPTR AddrV, AddrP;
+    u32 i;
 
-	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-		return (LONG)(XST_INVALID_PARAM);
+    if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+	    return (LONG)(XST_INVALID_PARAM);
 	}
 
 	/* Is the list created */
-	if (RingPtr->AllCnt == 0x00000000U) {
-		return (LONG)(XST_DMA_SG_NO_LIST);
+    if (RingPtr->AllCnt == 0x00000000U) {
+	    return (LONG)(XST_DMA_SG_NO_LIST);
 	}
 
 	/* Can't check if channel is running */
-	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-		return (LONG)(XST_IS_STARTED);
+    if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+	    return (LONG)(XST_IS_STARTED);
 	}
 
 	/* RunState doesn't make sense */
-	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
 	/* Verify internal pointers point to correct memory space */
-	AddrV = (UINTPTR) RingPtr->FreeHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    AddrV = (UINTPTR) RingPtr->FreeHead;
+    if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
-	AddrV = (UINTPTR) RingPtr->PreHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    AddrV = (UINTPTR) RingPtr->PreHead;
+    if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
-	AddrV = (UINTPTR) RingPtr->HwHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    AddrV = (UINTPTR) RingPtr->HwHead;
+    if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
-	AddrV = (UINTPTR) RingPtr->HwTail;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    AddrV = (UINTPTR) RingPtr->HwTail;
+    if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
-	AddrV = (UINTPTR) RingPtr->PostHead;
-	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+    AddrV = (UINTPTR) RingPtr->PostHead;
+    if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
 	/* Verify internal counters add up */
-	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+    if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
 	     RingPtr->PostCnt) != RingPtr->AllCnt) {
-		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	    return (LONG)(XST_DMA_SG_LIST_ERROR);
 	}
 
 	/* Verify BDs are linked correctly */
-	AddrV = RingPtr->BaseBdAddr;
-	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+    AddrV = RingPtr->BaseBdAddr;
+    AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
 
-	for (i = 1U; i < RingPtr->AllCnt; i++) {
+    for (i = 1U; i < RingPtr->AllCnt; i++) {
 		/* Check BDA for this BD. It should point to next physical addr */
-		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
+	    if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+		    return (LONG)(XST_DMA_SG_LIST_ERROR);
 		}
 
 		/* Move on to next BD */
-		AddrV += RingPtr->Separation;
-		AddrP += RingPtr->Separation;
+	    AddrV += RingPtr->Separation;
+	    AddrP += RingPtr->Separation;
 	}
 
 	/* Last BD should have wrap bit set */
-	if (XEMACPS_SEND == Direction) {
-		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
+    if (XEMACPS_SEND == Direction) {
+	    if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+		    return (LONG)(XST_DMA_SG_LIST_ERROR);
 		}
 	}
-	else {			/* XEMACPS_RECV */
-		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
-			return (LONG)(XST_DMA_SG_LIST_ERROR);
+    else {			/* XEMACPS_RECV */
+	    if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+		    return (LONG)(XST_DMA_SG_LIST_ERROR);
 		}
 	}
 
 	/* No problems found */
-	return (LONG)(XST_SUCCESS);
+    return (LONG)(XST_SUCCESS);
 }
 
 /*****************************************************************************/
@@ -1012,13 +1012,13 @@ LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
 static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
 {
     u32 DataValueRx;
-	u32 *TempPtr;
+    u32 *TempPtr;
 
-	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
-	TempPtr = (u32 *)BdPtr;
-	if(TempPtr != NULL) {
-		DataValueRx = *TempPtr;
-		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+    BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+    TempPtr = (u32 *)BdPtr;
+    if(TempPtr != NULL) {
+	    DataValueRx = *TempPtr;
+	    DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
 		*TempPtr = DataValueRx;
 	}
 }
@@ -1038,13 +1038,13 @@ static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
 static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
 {
     u32 DataValueTx;
-	u32 *TempPtr;
+    u32 *TempPtr;
 
-	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
-	TempPtr = (u32 *)BdPtr;
-	if(TempPtr != NULL) {
-		DataValueTx = *TempPtr;
-		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+    BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+    TempPtr = (u32 *)BdPtr;
+    if(TempPtr != NULL) {
+	    DataValueTx = *TempPtr;
+	    DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
 		*TempPtr = DataValueTx;
 	}
 }
@@ -1066,11 +1066,11 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
  *****************************************************************************/
 void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
 {
-	RingPtr->FreeHead = virtaddrloc;
-	RingPtr->PreHead = virtaddrloc;
-	RingPtr->HwHead = virtaddrloc;
-	RingPtr->HwTail = virtaddrloc;
-	RingPtr->PostHead = virtaddrloc;
+    RingPtr->FreeHead = virtaddrloc;
+    RingPtr->PreHead = virtaddrloc;
+    RingPtr->HwHead = virtaddrloc;
+    RingPtr->HwTail = virtaddrloc;
+    RingPtr->PostHead = virtaddrloc;
 }
 
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h

@@ -40,28 +40,28 @@ extern "C" {
 
 /** This is an internal structure used to maintain the DMA list */
 typedef struct {
-	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
-	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
-	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
-	u32 Length;	 /**< Total size of ring in bytes */
-	u32 RunState;	 /**< Flag to indicate DMA is started */
-	u32 Separation;	 /**< Number of bytes between the starting address
+    UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+    UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+    UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+    u32 Length;	 /**< Total size of ring in bytes */
+    u32 RunState;	 /**< Flag to indicate DMA is started */
+    u32 Separation;	 /**< Number of bytes between the starting address
                                   of adjacent BDs */
-	XEmacPs_Bd *FreeHead;
+    XEmacPs_Bd *FreeHead;
 			     /**< First BD in the free group */
-	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
-	XEmacPs_Bd *HwHead; /**< First BD in the work group */
-	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
-	XEmacPs_Bd *PostHead;
+    XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+    XEmacPs_Bd *HwHead; /**< First BD in the work group */
+    XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+    XEmacPs_Bd *PostHead;
 			     /**< First BD in the post-work group */
-	XEmacPs_Bd *BdaRestart;
+    XEmacPs_Bd *BdaRestart;
 			     /**< BDA to load when channel is started */
 
-	volatile u32 HwCnt;    /**< Number of BDs in work group */
-	u32 PreCnt;     /**< Number of BDs in pre-work group */
-	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
-	u32 PostCnt;    /**< Number of BDs in post-work group */
-	u32 AllCnt;     /**< Total Number of BDs for channel */
+    volatile u32 HwCnt;    /**< Number of BDs in work group */
+    u32 PreCnt;     /**< Number of BDs in pre-work group */
+    u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+    u32 PostCnt;    /**< Number of BDs in post-work group */
+    u32 AllCnt;     /**< Total Number of BDs for channel */
 } XEmacPs_BdRing;
 
 
@@ -195,9 +195,9 @@ LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
 LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
 			   XEmacPs_Bd * BdSetPtr);
 LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr);
+		    XEmacPs_Bd * BdSetPtr);
 LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			XEmacPs_Bd * BdSetPtr);
+		    XEmacPs_Bd * BdSetPtr);
 u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 				 XEmacPs_Bd ** BdSetPtr);
 u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c

@@ -6,9 +6,9 @@
 * DO NOT EDIT.
 *
 * Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT 
+* SPDX-License-Identifier: MIT
 
-* 
+*
 * Description: Driver configuration
 *
 *******************************************************************/
@@ -23,9 +23,9 @@
 XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
 {
 	{
-		XPAR_PSU_ETHERNET_3_DEVICE_ID,
-		XPAR_PSU_ETHERNET_3_BASEADDR,
-		XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
+	    XPAR_PSU_ETHERNET_3_DEVICE_ID,
+	    XPAR_PSU_ETHERNET_3_BASEADDR,
+	    XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
 	}
 };
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c

@@ -44,11 +44,11 @@
 * This function perform the reset sequence to the given emacps interface by
 * configuring the appropriate control bits in the emacps specific registers.
 * the emacps reset sequence involves the following steps
-*	Disable all the interuupts
-*	Clear the status registers
-*	Disable Rx and Tx engines
-*	Update the Tx and Rx descriptor queue registers with reset values
-*	Update the other relevant control registers with reset value
+*    Disable all the interuupts
+*    Clear the status registers
+*    Disable Rx and Tx engines
+*    Update the Tx and Rx descriptor queue registers with reset values
+*    Update the other relevant control registers with reset value
 *
 * @param   BaseAddr of the interface
 *
@@ -60,38 +60,38 @@
 ******************************************************************************/
 void XEmacPs_ResetHw(u32 BaseAddr)
 {
-	u32 RegVal;
+    u32 RegVal;
 
 	/* Disable the interrupts  */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
 
 	/* Stop transmission,disable loopback and Stop tx and Rx engines */
-	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
-	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+    RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+    RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
 				(u32)XEMACPS_NWCTRL_RXEN_MASK|
 				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
 				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
 	/* Clear the statistic registers, flush the packets in DPRAM*/
-	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
-				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+    RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+			    XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
 	/* Clear the interrupt status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
 	/* Clear the tx status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
 									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
 									(u32)XEMACPS_TXSR_TXGO_MASK));
 	/* Clear the rx status */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
-								XEMACPS_RXSR_FRAMERX_MASK);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+							    XEMACPS_RXSR_FRAMERX_MASK);
 	/* Clear the tx base address */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
 	/* Clear the rx base address */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
 	/* Update the network config register with reset value */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
 	/* Update the hash address registers with reset value */
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
-	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+    XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h

@@ -89,7 +89,7 @@ extern "C" {
  * @{
  */
 typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
-	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+    MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
 } XEmacPs_MdcDiv;
 
 /*@}*/
@@ -276,29 +276,29 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 						      nanosecond counter */
 
 #define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
-							reg */
+						    reg */
 #define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
-							reg */
+						    reg */
 #define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
-							reg */
+						    reg */
 #define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
-							reg */
+						    reg */
 #define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
-							reg */
+						    reg */
 #define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
-							reg */
+						    reg */
 #define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
-							reg */
+						    reg */
 #define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
-							reg */
+						    reg */
 
 /* Define some bit positions for registers. */
 
 /** @name network control register bit definitions
  * @{
  */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
-							Rx SRAM */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK    0x00040000U /**< Flush a packet from
+						    Rx SRAM */
 #define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
                                                          pause frame */
 #define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
@@ -382,23 +382,23 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 /** @name DMA control register bit definitions
  * @{
  */
-#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
-													size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
-												size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+#define XEMACPS_DMACR_ADDR_WIDTH_64	    0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK	    0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK	    0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK	    0x00FF0000U /**< Mask bit for RX buffer
+												    size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 	    16U	/**< Shift bit for RX buffer
+											    size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK	    0x00000800U /**< enable/disable TX
 													    checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+#define XEMACPS_DMACR_TXSIZE_MASK	    0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK	    0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK	    0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK	    0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST    0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST    0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST    0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST    0x00000010U /**< 16 bytes AHB bursts */
 /*@}*/
 
 /** @name transmit status register bit definitions
@@ -435,7 +435,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
                                        (u32)XEMACPS_RXSR_RXOVR_MASK | \
                                        (u32)XEMACPS_RXSR_BUFFNA_MASK)
 
-#define XEMACPS_SR_ALL_MASK	0xFFFFFFFFU /**< Mask for full register */
+#define XEMACPS_SR_ALL_MASK    0xFFFFFFFFU /**< Mask for full register */
 
 /*@}*/
 
@@ -443,8 +443,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
  * @name Interrupt Q1 status register bit definitions
  * @{
  */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK    0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK    0x00000040U /**< Transmit AMBA Error */
 
 #define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
 					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
@@ -457,15 +457,15 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
  * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
  * @{
  */
-#define XEMACPS_IXR_PTPPSTX_MASK	0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK	0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK	0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK	0x00400000U /**< PTP Pdelay_req RXed */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK    0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK    0x00400000U /**< PTP Pdelay_req RXed */
 
-#define XEMACPS_IXR_PTPSTX_MASK		0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK	0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK		0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK	0x00040000U /**< PTP Delay_req RXed */
+#define XEMACPS_IXR_PTPSTX_MASK	    0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK	    0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req RXed */
 
 #define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
 #define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
@@ -511,9 +511,9 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 /** @name RX watermark bit definitions
  * @{
  */
-#define XEMACPS_RXWM_HIGH_MASK		0x0000FFFFU	/**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK		0xFFFF0000U	/**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK	16U	/**< Shift for RXWM low */
+#define XEMACPS_RXWM_HIGH_MASK	    0x0000FFFFU	/**< RXWM high mask */
+#define XEMACPS_RXWM_LOW_MASK	    0xFFFF0000U	/**< RXWM low mask */
+#define XEMACPS_RXWM_LOW_SHFT_MSK    16U	/**< Shift for RXWM low */
 /*@}*/
 
 /* Transmit buffer descriptor status words offset

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c

@@ -77,34 +77,34 @@
  *
  *****************************************************************************/
 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-			void *FuncPointer, void *CallBackRef)
+		    void *FuncPointer, void *CallBackRef)
 {
-	LONG Status;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(FuncPointer != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-	switch (HandlerType) {
-	case XEMACPS_HANDLER_DMASEND:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-		InstancePtr->SendRef = CallBackRef;
-		break;
-	case XEMACPS_HANDLER_DMARECV:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-		InstancePtr->RecvRef = CallBackRef;
-		break;
-	case XEMACPS_HANDLER_ERROR:
-		Status = (LONG)(XST_SUCCESS);
-		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
-		InstancePtr->ErrorRef = CallBackRef;
-		break;
-	default:
-		Status = (LONG)(XST_INVALID_PARAM);
-		break;
+    LONG Status;
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(FuncPointer != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+    switch (HandlerType) {
+    case XEMACPS_HANDLER_DMASEND:
+	    Status = (LONG)(XST_SUCCESS);
+	    InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+	    InstancePtr->SendRef = CallBackRef;
+	    break;
+    case XEMACPS_HANDLER_DMARECV:
+	    Status = (LONG)(XST_SUCCESS);
+	    InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+	    InstancePtr->RecvRef = CallBackRef;
+	    break;
+    case XEMACPS_HANDLER_ERROR:
+	    Status = (LONG)(XST_SUCCESS);
+	    InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+	    InstancePtr->ErrorRef = CallBackRef;
+	    break;
+    default:
+	    Status = (LONG)(XST_INVALID_PARAM);
+	    break;
 	}
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -121,93 +121,93 @@ LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
 ******************************************************************************/
 void XEmacPs_IntrHandler(void *XEmacPsPtr)
 {
-	u32 RegISR;
-	u32 RegSR;
-	u32 RegCtrl;
-	u32 RegQ1ISR = 0U;
-	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+    u32 RegISR;
+    u32 RegSR;
+    u32 RegCtrl;
+    u32 RegQ1ISR = 0U;
+    XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
 	/* This ISR will try to handle as many interrupts as it can in a single
 	 * call. However, in most of the places where the user's error handler
          * is called, this ISR exits because it is expected that the user will
          * reset the device in nearly all instances.
 	 */
-	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+    RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_ISR_OFFSET);
 
 	/* Read Transmit Q1 ISR */
 
-	if (InstancePtr->Version > 2)
-		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+    if (InstancePtr->Version > 2)
+	    RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_INTQ1_STS_OFFSET);
 
 	/* Clear the interrupt status register */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 			   RegISR);
 
 	/* Receive complete interrupt */
-	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+    if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
 		/* Clear RX status register RX complete indication but preserve
 		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_RXSR_OFFSET,
 				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
 				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
-		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	    InstancePtr->RecvHandler(InstancePtr->RecvRef);
 	}
 
 	/* Transmit Q1 complete interrupt */
-	if ((InstancePtr->Version > 2) &&
+    if ((InstancePtr->Version > 2) &&
 			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 		/* Clear TX status register TX complete indication but preserve
 		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_INTQ1_STS_OFFSET,
 				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_TXSR_OFFSET,
 				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-		InstancePtr->SendHandler(InstancePtr->SendRef);
+	    InstancePtr->SendHandler(InstancePtr->SendRef);
 	}
 
 	/* Transmit complete interrupt */
-	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+    if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
 		/* Clear TX status register TX complete indication but preserve
 		 * error bits if there is any */
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_TXSR_OFFSET,
 				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-		InstancePtr->SendHandler(InstancePtr->SendRef);
+	    InstancePtr->SendHandler(InstancePtr->SendRef);
 	}
 
 	/* Receive error conditions interrupt */
-	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+    if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
 		/* Clear RX status register */
-		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+	    RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 					  XEMACPS_RXSR_OFFSET);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_RXSR_OFFSET, RegSR);
 
 		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
 		 * register to flush a packet out of Rx SRAM upon
 		 * an error for receive buffer not available. */
-		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
-			RegCtrl =
-			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XEMACPS_NWCTRL_OFFSET);
-			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+	    if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+		    RegCtrl =
+		    XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					    XEMACPS_NWCTRL_OFFSET);
+		    RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_NWCTRL_OFFSET, RegCtrl);
 		}
 
-		if(RegSR != 0) {
-			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
-						XEMACPS_RECV, RegSR);
+	    if(RegSR != 0) {
+		    InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					    XEMACPS_RECV, RegSR);
 		}
 	}
 
@@ -220,9 +220,9 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
 			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
             ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 			/* Clear Interrupt Q1 status register */
-			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
-			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+		    InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 					  RegQ1ISR);
 	   }
 
@@ -230,11 +230,11 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
         if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
             (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
 		/* Clear TX status register */
-		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+	    RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 					  XEMACPS_TXSR_OFFSET);
-		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 				   XEMACPS_TXSR_OFFSET, RegSR);
-		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+	    InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 					  RegSR);
 	}
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c

@@ -56,16 +56,16 @@ extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
 ******************************************************************************/
 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
 {
-	XEmacPs_Config *CfgPtr = NULL;
-	u32 i;
+    XEmacPs_Config *CfgPtr = NULL;
+    u32 i;
 
-	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
-		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
-			CfgPtr = &XEmacPs_ConfigTable[i];
-			break;
+    for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+	    if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+		    CfgPtr = &XEmacPs_ConfigTable[i];
+		    break;
 		}
 	}
 
-	return (XEmacPs_Config *)(CfgPtr);
+    return (XEmacPs_Config *)(CfgPtr);
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c

@@ -25,7 +25,7 @@
 *		      for output pins on all banks during initialization.
 * 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 * 3.1   aru  07/13/18 Resolved doxygen reported warnings. CR# 1006331.
 * 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
 * 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
@@ -61,50 +61,50 @@ extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
 * All members of the XGpioPs instance structure are initialized and
 * StubHandlers are assigned to the Bank Status Handlers.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	ConfigPtr points to the XGpioPs device configuration structure.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. If the address translation is not used then the
-*		physical address should be passed.
-*		Unexpected errors may occur if the address mapping is changed
-*		after this function is invoked.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    ConfigPtr points to the XGpioPs device configuration structure.
+* @param    EffectiveAddr is the device base address in the virtual memory
+*	    address space. If the address translation is not used then the
+*	    physical address should be passed.
+*	    Unexpected errors may occur if the address mapping is changed
+*	    after this function is invoked.
 *
-* @return	XST_SUCCESS always.
+* @return    XST_SUCCESS always.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
-				u32 EffectiveAddr)
+			    u32 EffectiveAddr)
 {
-	s32 Status = XST_SUCCESS;
-	u8 i;
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
-	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+    s32 Status = XST_SUCCESS;
+    u8 i;
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+    Xil_AssertNonvoid(EffectiveAddr != (u32)0);
 	/*
 	 * Set some default values for instance data, don't indicate the device
 	 * is ready to use until everything has been initialized successfully.
 	 */
-	InstancePtr->IsReady = 0U;
-	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
-	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
-	InstancePtr->Platform = XGetPlatform_Info();
+    InstancePtr->IsReady = 0U;
+    InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+    InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+    InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
+    InstancePtr->Platform = XGetPlatform_Info();
 
 	/* Initialize the Bank data based on platform */
-	if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+    if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
 		/*
-		 *	Max pins in the ZynqMP GPIO device
-		 *	0 - 25,  Bank 0
-		 *	26 - 51, Bank 1
-		 *	52 - 77, Bank 2
-		 *	78 - 109, Bank 3
-		 *	110 - 141, Bank 4
-		 *	142 - 173, Bank 5
+		 *    Max pins in the ZynqMP GPIO device
+		 *    0 - 25,  Bank 0
+		 *    26 - 51, Bank 1
+		 *    52 - 77, Bank 2
+		 *    78 - 109, Bank 3
+		 *    110 - 141, Bank 4
+		 *    142 - 173, Bank 5
 		 */
-		InstancePtr->MaxPinNum = (u32)174;
-		InstancePtr->MaxBanks = (u8)6;
+	    InstancePtr->MaxPinNum = (u32)174;
+	    InstancePtr->MaxBanks = (u8)6;
 	}
         else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
         {
@@ -131,21 +131,21 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
         }
         else {
 		/*
-		 *	Max pins in the GPIO device
-		 *	0 - 31,  Bank 0
-		 *	32 - 53, Bank 1
-		 *	54 - 85, Bank 2
-		 *	86 - 117, Bank 3
+		 *    Max pins in the GPIO device
+		 *    0 - 31,  Bank 0
+		 *    32 - 53, Bank 1
+		 *    54 - 85, Bank 2
+		 *    86 - 117, Bank 3
 		 */
-		InstancePtr->MaxPinNum = (u32)118;
-		InstancePtr->MaxBanks = (u8)4;
+	    InstancePtr->MaxPinNum = (u32)118;
+	    InstancePtr->MaxBanks = (u8)4;
 	}
 
 	/*
 	 * By default, interrupts are not masked in GPIO. Disable
 	 * interrupts for all pins in all the 4 banks.
 	 */
-	for (i=(u8)0U;i<InstancePtr->MaxBanks;i++) {
+    for (i=(u8)0U;i<InstancePtr->MaxBanks;i++) {
                 if (InstancePtr->Platform == XPLAT_VERSAL){
                         if(InstancePtr->PmcGpio == (u32)FALSE)
                         {
@@ -171,16 +171,16 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
                 }
                 else
                 {
-		XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+	    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
 					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
                 }
 	}
 
 	/* Indicate the component is now ready to use. */
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
-	return Status;
+    return Status;
 }
 
 /****************************************************************************/
@@ -188,20 +188,20 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
 *
 * Read the Data register of the specified GPIO bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
-* @return	Current value of the Data register.
+* @return    Current value of the Data register.
 *
-* @note		This function is used for reading the state of all the GPIO pins
-*		of specified bank.
+* @note	    This function is used for reading the state of all the GPIO pins
+*	    of specified bank.
 *
 *****************************************************************************/
 u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
 {
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -211,7 +211,7 @@ u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
         }
 #endif
 
-	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
 				 XGPIOPS_DATA_RO_OFFSET);
 }
@@ -221,33 +221,33 @@ u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
 *
 * Read Data from the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the data has to be read.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*		See xgpiops.h for the mapping of the pin numbers in the banks.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the data has to be read.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*	    See xgpiops.h for the mapping of the pin numbers in the banks.
 *
-* @return	Current value of the Pin (0 or 1).
+* @return    Current value of the Pin (0 or 1).
 *
-* @note		This function is used for reading the state of the specified
-*		GPIO pin.
+* @note	    This function is used for reading the state of the specified
+*	    GPIO pin.
 *
 *****************************************************************************/
 u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
+    u8 Bank;
+    u8 PinNumber;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
-	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
 				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
 
@@ -258,21 +258,21 @@ u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * Write to the Data register of the specified GPIO bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	Data is the value to be written to the Data register.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    Data is the value to be written to the Data register.
 *
-* @return	None.
+* @return    None.
 *
-* @note		This function is used for writing to all the GPIO pins of
-*		the bank. The previous state of the pins is not maintained.
+* @note	    This function is used for writing to all the GPIO pins of
+*	    the bank. The previous state of the pins is not maintained.
 *
 *****************************************************************************/
 void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -282,7 +282,7 @@ void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
 			  XGPIOPS_DATA_OFFSET, Data);
 }
@@ -292,52 +292,52 @@ void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
 *
 * Write data to the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number to which the Data is to be written.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param	Data is the data to be written to the specified pin (0 or 1).
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number to which the Data is to be written.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    Data is the data to be written to the specified pin (0 or 1).
 *
-* @return	None.
+* @return    None.
 *
-* @note		This function does a masked write to the specified pin of
-*		the specified GPIO bank. The previous state of other pins
-*		is maintained.
+* @note	    This function does a masked write to the specified pin of
+*	    the specified GPIO bank. The previous state of other pins
+*	    is maintained.
 *
 *****************************************************************************/
 void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
 {
-	u32 RegOffset;
-	u32 Value;
-	u8 Bank;
-	u8 PinNumber;
-	u32 DataVar = Data;
+    u32 RegOffset;
+    u32 Value;
+    u8 Bank;
+    u8 PinNumber;
+    u32 DataVar = Data;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	if (PinNumber > 15U) {
+    if (PinNumber > 15U) {
 		/* There are only 16 data bits in bit maskable register. */
-		PinNumber -= (u8)16;
-		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	    PinNumber -= (u8)16;
+	    RegOffset = XGPIOPS_DATA_MSW_OFFSET;
 	} else {
-		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	    RegOffset = XGPIOPS_DATA_LSW_OFFSET;
 	}
 
 	/*
 	 * Get the 32 bit value to be written to the Mask/Data register where
 	 * the upper 16 bits is the mask and lower 16 bits is the data.
 	 */
-	DataVar &= (u32)0x01;
-	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    DataVar &= (u32)0x01;
+    Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
 			  RegOffset, Value);
 
@@ -350,24 +350,24 @@ void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
 *
 * Set the Direction of the pins of the specified GPIO Bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	Direction is the 32 bit mask of the Pin direction to be set for
-*		all the pins in the Bank. Bits with 0 are set to Input mode,
-*		bits with 1 are	set to Output Mode.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    Direction is the 32 bit mask of the Pin direction to be set for
+*	    all the pins in the Bank. Bits with 0 are set to Input mode,
+*	    bits with 1 are    set to Output Mode.
 *
-* @return	None.
+* @return    None.
 *
-* @note		This function is used for setting the direction of all the pins
-*		in the specified bank. The previous state of the pins is
-*		not maintained.
+* @note	    This function is used for setting the direction of all the pins
+*	    in the specified bank. The previous state of the pins is
+*	    not maintained.
 *
 *****************************************************************************/
 void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -377,7 +377,7 @@ void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_DIRM_OFFSET, Direction);
 }
@@ -387,43 +387,43 @@ void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
 *
 * Set the Direction of the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number to which the Data is to be written.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param	Direction is the direction to be set for the specified pin.
-*		Valid values are 0 for Input Direction, 1 for Output Direction.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number to which the Data is to be written.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    Direction is the direction to be set for the specified pin.
+*	    Valid values are 0 for Input Direction, 1 for Output Direction.
 *
-* @return	None.
+* @return    None.
 *
 *****************************************************************************/
 void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 DirModeReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 DirModeReg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-	Xil_AssertVoid(Direction <= (u32)1);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(Direction <= (u32)1);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
-	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				      XGPIOPS_DIRM_OFFSET);
 
-	if (Direction!=(u32)0) { /*  Output Direction */
-		DirModeReg |= ((u32)1 << (u32)PinNumber);
+    if (Direction!=(u32)0) { /*  Output Direction */
+	    DirModeReg |= ((u32)1 << (u32)PinNumber);
 	} else { /* Input Direction */
-		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	    DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
 	}
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			 XGPIOPS_DIRM_OFFSET, DirModeReg);
 }
@@ -433,20 +433,20 @@ void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
 *
 * Get the Direction of the pins of the specified GPIO Bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
-* @return	Returns a 32 bit mask of the Direction register. Bits with 0 are
-* 		in Input mode, bits with 1 are in Output Mode.
+* @return    Returns a 32 bit mask of the Direction register. Bits with 0 are
+* 	    in Input mode, bits with 1 are in Output Mode.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
 {
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -456,9 +456,9 @@ u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
         }
 #endif
 
-	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				XGPIOPS_DIRM_OFFSET);
+			    XGPIOPS_DIRM_OFFSET);
 }
 
 /****************************************************************************/
@@ -466,35 +466,35 @@ u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
 *
 * Get the Direction of the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the Direction is to be
-*		retrieved.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the Direction is to be
+*	    retrieved.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @return	Direction of the specified pin.
+* @return    Direction of the specified pin.
 *		- 0 for Input Direction
 *		- 1 for Output Direction
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
+    u8 Bank;
+    u8 PinNumber;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
 }
@@ -504,24 +504,24 @@ u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * Set the Output Enable of the pins of the specified GPIO Bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
-*		all the pins in the Bank. The Output Enable of bits with 0 are
-*		disabled, the Output Enable of bits with 1 are enabled.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    OpEnable is the 32 bit mask of the Output Enables to be set for
+*	    all the pins in the Bank. The Output Enable of bits with 0 are
+*	    disabled, the Output Enable of bits with 1 are enabled.
 *
-* @return	None.
+* @return    None.
 *
-* @note		This function is used for setting the Output Enables of all the
-*		pins in the specified bank. The previous state of the Output
-*		Enables is not maintained.
+* @note	    This function is used for setting the Output Enables of all the
+*	    pins in the specified bank. The previous state of the Output
+*	    Enables is not maintained.
 *
 *****************************************************************************/
 void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -531,7 +531,7 @@ void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_OUTEN_OFFSET, OpEnable);
 }
@@ -541,48 +541,48 @@ void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
 *
 * Set the Output Enable of the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number to which the Data is to be written.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param	OpEnable specifies whether the Output Enable for the specified
-*		pin should be enabled.
-*		Valid values are 0 for Disabling Output Enable,
-*		1 for Enabling Output Enable.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number to which the Data is to be written.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    OpEnable specifies whether the Output Enable for the specified
+*	    pin should be enabled.
+*	    Valid values are 0 for Disabling Output Enable,
+*	    1 for Enabling Output Enable.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 OpEnableReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 OpEnableReg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-	Xil_AssertVoid(OpEnable <= (u32)1);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(OpEnable <= (u32)1);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				       XGPIOPS_OUTEN_OFFSET);
 
-	if (OpEnable != (u32)0) { /*  Enable Output Enable */
-		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+    if (OpEnable != (u32)0) { /*  Enable Output Enable */
+	    OpEnableReg |= ((u32)1 << (u32)PinNumber);
 	} else { /* Disable Output Enable */
-		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	    OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
 	}
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
 }
@@ -591,21 +591,21 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
 *
 * Get the Output Enable status of the pins of the specified GPIO Bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
-* @return	Returns a a 32 bit mask of the Output Enable register.
-*		Bits with 0 are in Disabled state, bits with 1 are in
-*		Enabled State.
+* @return    Returns a a 32 bit mask of the Output Enable register.
+*	    Bits with 0 are in Disabled state, bits with 1 are in
+*	    Enabled State.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
 {
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -615,9 +615,9 @@ u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
         }
 #endif
 
-	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				XGPIOPS_OUTEN_OFFSET);
+			    XGPIOPS_OUTEN_OFFSET);
 }
 
 /****************************************************************************/
@@ -625,35 +625,35 @@ u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
 *
 * Get the Output Enable status of the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the Output Enable status is to
-*		be retrieved.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the Output Enable status is to
+*	    be retrieved.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @return	Output Enable of the specified pin.
+* @return    Output Enable of the specified pin.
 *		- 0 if Output Enable is disabled for this pin
 *		- 1 if Output Enable is enabled for this pin
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
+    u8 Bank;
+    u8 PinNumber;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
 }
@@ -664,14 +664,14 @@ u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 * Get the Bank number and the Pin number in the Bank, for the given PinNumber
 * in the GPIO device.
 *
-* @param	PinNumber is the Pin number in the GPIO device.
-* @param	BankNumber returns the Bank in which this GPIO pin is present.
-*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
-* @param	PinNumberInBank returns the Pin Number within the Bank.
+* @param    PinNumber is the Pin number in the GPIO device.
+* @param    BankNumber returns the Bank in which this GPIO pin is present.
+*	    Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param    PinNumberInBank returns the Pin Number within the Bank.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 #ifdef versal
@@ -680,29 +680,29 @@ void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber,
 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
 #endif
 {
-	u32 XGpioPsPinTable[6] = {0};
+    u32 XGpioPsPinTable[6] = {0};
 #ifdef versal
         u8 i=(u8)0;
 #endif
-	u32 Platform = XGetPlatform_Info();
+    u32 Platform = XGetPlatform_Info();
 
-	if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+    if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
 		/*
 		 * This structure defines the mapping of the pin numbers to the banks when
 		 * the driver APIs are used for working on the individual pins.
 		 */
 
-		XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
-		XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
-		XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
-		XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
-		XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
-		XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+	    XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+	    XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+	    XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+	    XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+	    XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+	    XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
 
 		*BankNumber = 0U;
-		while (*BankNumber < XGPIOPS_SIX) {
-			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
-				break;
+	    while (*BankNumber < XGPIOPS_SIX) {
+		    if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+			    break;
 			}
 			(*BankNumber)++;
 		}
@@ -760,20 +760,20 @@ void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
         }
 #endif
         else {
-		XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
-		XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
-		XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
-		XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+	    XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+	    XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+	    XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+	    XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
 
 		*BankNumber = 0U;
-		while (*BankNumber < XGPIOPS_FOUR) {
-			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
-				break;
+	    while (*BankNumber < XGPIOPS_FOUR) {
+		    if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+			    break;
 			}
 			(*BankNumber)++;
 		}
 	}
-	if (*BankNumber == (u8)0) {
+    if (*BankNumber == (u8)0) {
 		*PinNumberInBank = PinNumber;
 	}
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h

@@ -67,10 +67,10 @@
 *		      for output pins on all banks during initialization.
 * 1.02a hk   08/22/13 Added low level reset API
 * 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 2.2    sk	 10/13/14 Used Pin number in Bank instead of pin number
 * 					  passed to APIs. CR# 822636
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 *       ms   03/17/17 Added readme.txt file in examples folder for doxygen
 *                     generation.
 *       ms   04/05/17 Added tabspace for return statements in functions of
@@ -89,9 +89,9 @@
 * 3.5   sne  03/14/19 Added Versal support.
 * 3.6   mus  04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
 *                     sync with standalone BSP
-* 3.6	sne  06/12/19 Fixed IAR compiler warning.
+* 3.6    sne  06/12/19 Fixed IAR compiler warning.
 * 3.6   sne  08/14/19 Added interrupt handler support on versal.
-* 3.7	sne  12/04/19 Reverted versal examples support.
+* 3.7    sne  12/04/19 Reverted versal examples support.
 *
 * </pre>
 *
@@ -116,43 +116,43 @@ extern "C" {
  * The following constants define the interrupt types that can be set for each
  * GPIO pin.
  */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING    0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING    0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH    0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH    0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW    0x04U  /**< Interrupt on low level */
 /*@}*/
 
 #define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+#define XGPIOPS_BANK0		    0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1		    0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2		    0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3		    0x03U  /**< GPIO Bank 3 */
 
 #ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#define XGPIOPS_BANK4		    0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5		    0x05U  /**< GPIO Bank 5 */
 #endif
 
-#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
-										*	Zynq Ultrascale+ MP GPIO device
+#define XGPIOPS_MAX_BANKS_ZYNQMP	    0x06U  /**< Max banks in a
+										*    Zynq Ultrascale+ MP GPIO device
 										*/
-#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+#define XGPIOPS_MAX_BANKS	    0x04U  /**< Max banks in a Zynq GPIO device */
 
 #define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
-						  *	Zynq Ultrascale+ MP GPIO device
+						  *    Zynq Ultrascale+ MP GPIO device
 					      * 0 - 25,  Bank 0
 					      * 26 - 51, Bank 1
-					      *	52 - 77, Bank 2
-					      *	78 - 109, Bank 3
-					      *	110 - 141, Bank 4
-					      *	142 - 173, Bank 5
+					      *    52 - 77, Bank 2
+					      *    78 - 109, Bank 3
+					      *    110 - 141, Bank 4
+					      *    142 - 173, Bank 5
 					      */
 #define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
 					      * 0 - 31,  Bank 0
 					      * 32 - 53, Bank 1
-					      *	54 - 85, Bank 2
-					      *	86 - 117, Bank 3
+					      *    54 - 85, Bank 2
+					      *    86 - 117, Bank 3
 					      */
 
 /**************************** Type Definitions *******************************/
@@ -165,13 +165,13 @@ extern "C" {
  * driven mode. The handler executes in an interrupt context such that minimal
  * processing should be performed.
  *
- * @param	CallBackRef is a callback reference passed in by the upper layer
- *		when setting the callback functions for a GPIO bank. It is
- *		passed back to the upper layer when the callback is invoked. Its
- *		type is not important to the driver component, so it is a void
- *		pointer.
- * @param	Bank is the bank for which the interrupt status has changed.
- * @param	Status is the Interrupt status of the GPIO bank.
+ * @param    CallBackRef is a callback reference passed in by the upper layer
+ *	    when setting the callback functions for a GPIO bank. It is
+ *	    passed back to the upper layer when the callback is invoked. Its
+ *	    type is not important to the driver component, so it is a void
+ *	    pointer.
+ * @param    Bank is the bank for which the interrupt status has changed.
+ * @param    Status is the Interrupt status of the GPIO bank.
  *
  *****************************************************************************/
 typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
@@ -180,8 +180,8 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
  * This typedef contains configuration information for a device.
  */
 typedef struct {
-	u16 DeviceId;		/**< Unique ID of device */
-	u32 BaseAddr;		/**< Register base address */
+    u16 DeviceId;		/**< Unique ID of device */
+    u32 BaseAddr;		/**< Register base address */
 } XGpioPs_Config;
 
 /**
@@ -190,13 +190,13 @@ typedef struct {
  * to a variable of this type is then passed to the driver API functions.
  */
 typedef struct {
-	XGpioPs_Config GpioConfig;	/**< Device configuration */
-	u32 IsReady;			/**< Device is initialized and ready */
-	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
-	void *CallBackRef; 		/**< Callback ref for bank handlers */
-	u32 Platform;			/**< Platform data */
-	u32 MaxPinNum;			/**< Max pins in the GPIO device */
-	u8 MaxBanks;			/**< Max banks in a GPIO device */
+    XGpioPs_Config GpioConfig;	/**< Device configuration */
+    u32 IsReady;			/**< Device is initialized and ready */
+    XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+    void *CallBackRef; 		/**< Callback ref for bank handlers */
+    u32 Platform;			/**< Platform data */
+    u32 MaxPinNum;			/**< Max pins in the GPIO device */
+    u8 MaxBanks;			/**< Max banks in a GPIO device */
         u32 PmcGpio;                    /**< Flag for accessing PS GPIO for versal*/
 } XGpioPs;
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c

@@ -6,9 +6,9 @@
 * DO NOT EDIT.
 *
 * Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT 
+* SPDX-License-Identifier: MIT
 
-* 
+*
 * Description: Driver configuration
 *
 *******************************************************************/
@@ -23,8 +23,8 @@
 XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
 {
 	{
-		XPAR_PSU_GPIO_0_DEVICE_ID,
-		XPAR_PSU_GPIO_0_BASEADDR
+	    XPAR_PSU_GPIO_0_DEVICE_ID,
+	    XPAR_PSU_GPIO_0_BASEADDR
 	}
 };
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c

@@ -19,7 +19,7 @@
 * ----- ---- -------- -----------------------------------------------
 * 1.02a hk   08/22/13 First Release
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 * 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
 *                     in safety mode and modified the code such as
 *                     Use of mixed mode arithmetic,Declared the pointer param
@@ -52,19 +52,19 @@
 * This function resets the GPIO module by writing reset values to
 * all registers
 *
-* @param	Base address of GPIO module
+* @param    Base address of GPIO module
 *
-* @return	None
+* @return    None
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 void XGpioPs_ResetHw(u32 BaseAddress)
 {
-	u32 BankCount;
-	u32 Platform,MaxBanks;
+    u32 BankCount;
+    u32 Platform,MaxBanks;
 
-	Platform = XGetPlatform_Info();
+    Platform = XGetPlatform_Info();
         if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
                 MaxBanks = (u32)6;
         }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h

@@ -23,7 +23,7 @@
 * 1.02a hk   08/22/13 Added low level reset API function prototype and
 *                     related constant definitions
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 3.1    kvn  04/13/15 Corrected reset values of banks.
 * 3.5   sne  03/14/19 Added versal support.
 * </pre>
 *
@@ -106,33 +106,33 @@ extern "C" {
 *
 * This macro reads the given register.
 *
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the register offset to be read.
+* @param    BaseAddr is the base address of the device.
+* @param    RegOffset is the register offset to be read.
 *
-* @return	The 32-bit value of the register
+* @return    The 32-bit value of the register
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 #define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
-		Xil_In32((BaseAddr) + (u32)(RegOffset))
+	    Xil_In32((BaseAddr) + (u32)(RegOffset))
 
 /****************************************************************************/
 /**
 *
 * This macro writes to the given register.
 *
-* @param	BaseAddr is the base address of the device.
-* @param	RegOffset is the offset of the register to be written.
-* @param	Data is the 32-bit value to write to the register.
+* @param    BaseAddr is the base address of the device.
+* @param    RegOffset is the offset of the register to be written.
+* @param    Data is the 32-bit value to write to the register.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
-		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+	    Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
 
 /************************** Function Prototypes ******************************/
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c

@@ -18,10 +18,10 @@
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a sv   01/18/10 First Release
-* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 2.2    sk	 10/13/14 Used Pin number in Bank instead of pin number
 * 					  passed to API's. CR# 822636
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 * 3.1   aru  07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
 * 3.4   aru  08/09/18 Ressolved cppcheck warnings.
 * 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
@@ -32,7 +32,7 @@
 *                     Literal value requires a U suffix.
 * 3.5   sne  03/14/19 Added Versal support.
 * 3.5   sne  03/20/19 Fixed multiple interrupts problem CR#1024556.
-* 3.6	sne  06/12/19 Fixed IAR compiler warning.
+* 3.6    sne  06/12/19 Fixed IAR compiler warning.
 * 3.6   sne  08/14/19 Added interrupt handler support on versal.
 *
 * </pre>
@@ -61,22 +61,22 @@ void StubHandler(const void *CallBackRef, u32 Bank, u32 Status);
 * This function enables the interrupts for the specified pins in the specified
 * bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	Mask is the bit mask of the pins for which interrupts are to
-*		be enabled. Bit positions of 1 will be enabled. Bit positions
-*		of 0 will keep the previous setting.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    Mask is the bit mask of the pins for which interrupts are to
+*	    be enabled. Bit positions of 1 will be enabled. Bit positions
+*	    of 0 will keep the previous setting.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -86,7 +86,7 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTEN_OFFSET, Mask);
 }
@@ -96,34 +96,34 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 *
 * This function enables the interrupt for the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the interrupt is to be enabled.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the interrupt is to be enabled.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 IntrReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 IntrReg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrReg = ((u32)1 << (u32)PinNumber);
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg = ((u32)1 << (u32)PinNumber);
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTEN_OFFSET, IntrReg);
 }
@@ -134,23 +134,23 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 * This function disables the interrupts for the specified pins in the specified
 * bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	Mask is the bit mask of the pins for which interrupts are
-*		to be disabled. Bit positions of 1 will be disabled. Bit
-*		positions of 0 will keep the previous setting.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    Mask is the bit mask of the pins for which interrupts are
+*	    to be disabled. Bit positions of 1 will be disabled. Bit
+*	    positions of 0 will keep the previous setting.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
                 Xil_AssertVoid(Bank != XGPIOPS_TWO);
@@ -159,7 +159,7 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTDIS_OFFSET, Mask);
 }
@@ -169,34 +169,34 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 *
 * This function disables the interrupts for the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the interrupt is to be disabled.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the interrupt is to be disabled.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 IntrReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 IntrReg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrReg = ((u32)1 << (u32)PinNumber);
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg = ((u32)1 << (u32)PinNumber);
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTDIS_OFFSET, IntrReg);
 }
@@ -206,24 +206,24 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * This function returns the interrupt enable status for a bank.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
-* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
-*		indicate that the interrupt for that pin is enabled, bit
-*		positions with 0 indicate that the interrupt for that pin is
-*		disabled.
+* @return    Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*	    indicate that the interrupt for that pin is enabled, bit
+*	    positions with 0 indicate that the interrupt for that pin is
+*	    disabled.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
 {
-	u32 IntrMask;
+    u32 IntrMask;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -233,10 +233,10 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
         }
 #endif
 
-	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				    XGPIOPS_INTMASK_OFFSET);
-	return (~IntrMask);
+    return (~IntrMask);
 }
 
 /****************************************************************************/
@@ -244,40 +244,40 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
 *
 * This function returns whether interrupts are enabled for the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the interrupt enable status
-*		is to be known.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the interrupt enable status
+*	    is to be known.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return
 *		- TRUE if the interrupt is enabled.
 *		- FALSE if the interrupt is disabled.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 IntrReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 IntrReg;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				    XGPIOPS_INTMASK_OFFSET);
 
-	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+    return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
 }
 
 /****************************************************************************/
@@ -285,19 +285,19 @@ u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * This function returns interrupt status read from Interrupt Status Register.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
-* @return	The value read from Interrupt Status Register.
+* @return    The value read from Interrupt Status Register.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
 {
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
         Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
@@ -307,9 +307,9 @@ u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
         }
 #endif
 
-	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				XGPIOPS_INTSTS_OFFSET);
+			    XGPIOPS_INTSTS_OFFSET);
 }
 
 /****************************************************************************/
@@ -317,40 +317,40 @@ u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
 *
 * This function returns interrupt enable status of the specified pin.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the interrupt enable status
-*		is to be known.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the interrupt enable status
+*	    is to be known.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return
 *		- TRUE if the interrupt has occurred.
 *		- FALSE if the interrupt has not occurred.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 IntrReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 IntrReg;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				   XGPIOPS_INTSTS_OFFSET);
 
-	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+    return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
 }
 
 /****************************************************************************/
@@ -360,21 +360,21 @@ u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
 * function should be called after the software has serviced the interrupts
 * that are pending.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	Mask is the mask of the interrupts to be cleared. Bit positions
-*		of 1 will be cleared. Bit positions of 0 will not change the
-*		previous interrupt status.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    Mask is the mask of the interrupts to be cleared. Bit positions
+*	    of 1 will be cleared. Bit positions of 0 will not change the
+*	    previous interrupt status.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
                 Xil_AssertVoid(Bank != XGPIOPS_TWO);
@@ -384,7 +384,7 @@ void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 #endif
 
 	/* Clear the currently pending interrupts. */
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTSTS_OFFSET, Mask);
 }
@@ -395,37 +395,37 @@ void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 * This function clears the specified pending interrupt. This function should be
 * called after the software has serviced the interrupts that are pending.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	Pin is the pin number for which the interrupt status is to be
-*		cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    Pin is the pin number for which the interrupt status is to be
+*	    cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u8 Bank;
-	u8 PinNumber;
-	u32 IntrReg;
+    u8 Bank;
+    u8 PinNumber;
+    u32 IntrReg;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
 	/* Clear the specified pending interrupts. */
-	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				   XGPIOPS_INTSTS_OFFSET);
 
-	IntrReg &= ((u32)1 << PinNumber);
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrReg &= ((u32)1 << PinNumber);
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTSTS_OFFSET, IntrReg);
 }
@@ -436,34 +436,34 @@ void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
 * This function is used for setting the Interrupt Type, Interrupt Polarity and
 * Interrupt On Any for the specified GPIO Bank pins.
 *
-* @param	InstancePtr is a pointer to an XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	IntrType is the 32 bit mask of the interrupt type.
-*		0 means Level Sensitive and 1 means Edge Sensitive.
-* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
-*		0 means Active Low or Falling Edge and 1 means Active High or
-*		Rising Edge.
-* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
-*		edge triggered interrupts. 0 means trigger on single edge using
-*		the configured interrupt polarity and 1 means  trigger on both
-*		edges.
-*
-* @return	None.
-*
-* @note		This function is used for setting the interrupt related
-*		properties of all the pins in the specified bank. The previous
-*		state of the pins is not maintained.
-*		To change the Interrupt properties of a single GPIO pin, use the
-*		function XGpioPs_SetPinIntrType().
+* @param    InstancePtr is a pointer to an XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    IntrType is the 32 bit mask of the interrupt type.
+*	    0 means Level Sensitive and 1 means Edge Sensitive.
+* @param    IntrPolarity is the 32 bit mask of the interrupt polarity.
+*	    0 means Active Low or Falling Edge and 1 means Active High or
+*	    Rising Edge.
+* @param    IntrOnAny is the 32 bit mask of the interrupt trigger for
+*	    edge triggered interrupts. 0 means trigger on single edge using
+*	    the configured interrupt polarity and 1 means  trigger on both
+*	    edges.
+*
+* @return    None.
+*
+* @note	    This function is used for setting the interrupt related
+*	    properties of all the pins in the specified bank. The previous
+*	    state of the pins is not maintained.
+*	    To change the Interrupt properties of a single GPIO pin, use the
+*	    function XGpioPs_SetPinIntrType().
 *
 *****************************************************************************/
 void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
 			  u32 IntrPolarity, u32 IntrOnAny)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
                 Xil_AssertVoid(Bank != XGPIOPS_TWO);
@@ -472,15 +472,15 @@ void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
         }
 #endif
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTTYPE_OFFSET, IntrType);
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
 }
@@ -491,31 +491,31 @@ void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
 * This function is used for getting the Interrupt Type, Interrupt Polarity and
 * Interrupt On Any for the specified GPIO Bank pins.
 *
-* @param	InstancePtr is a pointer to an XGpioPs instance.
-* @param	Bank is the bank number of the GPIO to operate on.
-*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param	IntrType returns the 32 bit mask of the interrupt type.
-*		0 means Level Sensitive and 1 means Edge Sensitive.
-* @param	IntrPolarity returns the 32 bit mask of the interrupt
-*		polarity. 0 means Active Low or Falling Edge and 1 means
-*		Active High or Rising Edge.
-* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
-*		edge triggered interrupts. 0 means trigger on single edge using
-*		the configured interrupt polarity and 1 means trigger on both
-*		edges.
+* @param    InstancePtr is a pointer to an XGpioPs instance.
+* @param    Bank is the bank number of the GPIO to operate on.
+*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param    IntrType returns the 32 bit mask of the interrupt type.
+*	    0 means Level Sensitive and 1 means Edge Sensitive.
+* @param    IntrPolarity returns the 32 bit mask of the interrupt
+*	    polarity. 0 means Active Low or Falling Edge and 1 means
+*	    Active High or Rising Edge.
+* @param    IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*	    edge triggered interrupts. 0 means trigger on single edge using
+*	    the configured interrupt polarity and 1 means trigger on both
+*	    edges.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
 			  u32 *IntrPolarity, u32 *IntrOnAny)
 
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
 #ifdef versal
         if(InstancePtr->PmcGpio == TRUE) {
                 Xil_AssertVoid(Bank != XGPIOPS_TWO);
@@ -542,86 +542,86 @@ void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
 *
 * This function is used for setting the IRQ Type of a single GPIO pin.
 *
-* @param	InstancePtr is a pointer to an XGpioPs instance.
-* @param	Pin is the pin number whose IRQ type is to be set.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
-*		defined in xgpiops.h to specify the IRQ type.
+* @param    InstancePtr is a pointer to an XGpioPs instance.
+* @param    Pin is the pin number whose IRQ type is to be set.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*	    defined in xgpiops.h to specify the IRQ type.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 *****************************************************************************/
 void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
 {
-	u32 IntrTypeReg;
-	u32 IntrPolReg;
-	u32 IntrOnAnyReg;
-	u8 Bank;
-	u8 PinNumber;
+    u32 IntrTypeReg;
+    u32 IntrPolReg;
+    u32 IntrOnAnyReg;
+    u8 Bank;
+    u8 PinNumber;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				       XGPIOPS_INTTYPE_OFFSET);
 
-	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				      XGPIOPS_INTPOL_OFFSET);
 
-	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-					XGPIOPS_INTANY_OFFSET);
-
-	switch (IrqType) {
-		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
-			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-			IntrPolReg |= ((u32)1 << (u32)PinNumber);
-			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
-			break;
-		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
-			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
-			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
-			break;
-		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
-			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
-			break;
-		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
-			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
-			IntrPolReg |= ((u32)1 << (u32)PinNumber);
-			break;
-		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
-			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
-			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
-			break;
-		default:
+				    XGPIOPS_INTANY_OFFSET);
+
+    switch (IrqType) {
+	    case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+		    IntrPolReg |= ((u32)1 << (u32)PinNumber);
+		    IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+		    break;
+	    case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+		    IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+		    IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+		    break;
+	    case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+		    IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+		    break;
+	    case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+		    IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+		    IntrPolReg |= ((u32)1 << (u32)PinNumber);
+		    break;
+	    case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+		    IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+		    IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+		    break;
+	    default:
 			/**< Default statement is added for MISRA C compliance. */
-			break;
+		    break;
 	}
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
 
-	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
 }
@@ -631,72 +631,72 @@ void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
 *
 * This function returns the IRQ Type of a given GPIO pin.
 *
-* @param	InstancePtr is a pointer to an XGpioPs instance.
-* @param	Pin is the pin number whose IRQ type is to be obtained.
-*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param    InstancePtr is a pointer to an XGpioPs instance.
+* @param    Pin is the pin number whose IRQ type is to be obtained.
+*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @return	None.
+* @return    None.
 *
-* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
-*		returned by this function.
+* @note	    Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*	    returned by this function.
 *
 *****************************************************************************/
 u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
 {
-	u32 IntrType;
-	u32 IntrPol;
-	u32 IntrOnAny;
-	u8 Bank;
-	u8 PinNumber;
-	u8 IrqType;
+    u32 IntrType;
+    u32 IntrPol;
+    u32 IntrOnAny;
+    u8 Bank;
+    u8 PinNumber;
+    u8 IrqType;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
 	/* Get the Bank number and Pin number within the bank. */
 #ifdef versal
-	XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
-	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+    XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+    IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
 
-	if (IntrType == ((u32)1 << PinNumber)) {
+    if (IntrType == ((u32)1 << PinNumber)) {
 
-		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+	    IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
 
-		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+	    IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
 
 
-		if (IntrOnAny == ((u32)1 << PinNumber)) {
-			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+	    if (IntrOnAny == ((u32)1 << PinNumber)) {
+		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
 		} else if (IntrPol == ((u32)1 << PinNumber)) {
-			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
 		} else {
-			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
 		}
 	} else {
 
-		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+	    IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
 				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
 				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
 
-		if (IntrPol == ((u32)1 << PinNumber)) {
-			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+	    if (IntrPol == ((u32)1 << PinNumber)) {
+		    IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
 		} else {
-			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		    IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
 		}
 	}
 
-	return IrqType;
+    return IrqType;
 }
 
 /*****************************************************************************/
@@ -705,28 +705,28 @@ u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
 * This function sets the status callback function. The callback function is
 * called by the  XGpioPs_IntrHandler when an interrupt occurs.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
-* @param	CallBackRef is the upper layer callback reference passed back
-*		when the callback function is invoked.
-* @param	FuncPointer is the pointer to the callback function.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
+* @param    CallBackRef is the upper layer callback reference passed back
+*	    when the callback function is invoked.
+* @param    FuncPointer is the pointer to the callback function.
 *
 *
-* @return	None.
+* @return    None.
 *
-* @note		The handler is called within interrupt context, so it should do
-*		its work quickly and queue potentially time-consuming work to a
-*		task-level thread.
+* @note	    The handler is called within interrupt context, so it should do
+*	    its work quickly and queue potentially time-consuming work to a
+*	    task-level thread.
 *
 ******************************************************************************/
 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
 				 XGpioPs_Handler FuncPointer)
 {
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(FuncPointer != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(FuncPointer != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	InstancePtr->Handler = FuncPointer;
-	InstancePtr->CallBackRef = CallBackRef;
+    InstancePtr->Handler = FuncPointer;
+    InstancePtr->CallBackRef = CallBackRef;
 }
 
 /*****************************************************************************/
@@ -738,42 +738,42 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
 * handler set by the function XGpioPs_SetBankHandler(). The callback is called
 * when an interrupt
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
 *
-* @return	None.
+* @return    None.
 *
-* @note		This function does not save and restore the processor context
-*		such that the user must provide this processing.
+* @note	    This function does not save and restore the processor context
+*	    such that the user must provide this processing.
 *
 ******************************************************************************/
 void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
 {
-	u8 Bank;
-	u32 IntrStatus;
-	u32 IntrEnabled;
+    u8 Bank;
+    u32 IntrStatus;
+    u32 IntrEnabled;
 
-	Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+    for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
 #ifdef versal
-		if(InstancePtr->PmcGpio == TRUE) {
-			if(Bank == XGPIOPS_TWO) {
-				continue;
+	    if(InstancePtr->PmcGpio == TRUE) {
+		    if(Bank == XGPIOPS_TWO) {
+			    continue;
 			}
 		} else {
-			if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
-				continue;
+		    if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
+			    continue;
 			}
 		}
 #endif
-		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
-		IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
-		if ((IntrStatus & IntrEnabled) != (u32)0) {
-			XGpioPs_IntrClear(InstancePtr, Bank,
+	    IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+	    IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
+	    if ((IntrStatus & IntrEnabled) != (u32)0) {
+		    XGpioPs_IntrClear(InstancePtr, Bank,
 					(IntrStatus & IntrEnabled));
-			InstancePtr->Handler(InstancePtr->
-					CallBackRef, Bank,
+		    InstancePtr->Handler(InstancePtr->
+				    CallBackRef, Bank,
 					(IntrStatus & IntrEnabled));
 		}
 	}
@@ -785,13 +785,13 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
 * This is a stub for the status callback. The stub is here in case the upper
 * layers do not set the handler.
 *
-* @param	CallBackRef is a pointer to the upper layer callback reference
-* @param	Bank is the GPIO Bank in which an interrupt occurred.
-* @param	Status is the Interrupt status of the GPIO bank.
+* @param    CallBackRef is a pointer to the upper layer callback reference
+* @param    Bank is the GPIO Bank in which an interrupt occurred.
+* @param    Status is the Interrupt status of the GPIO bank.
 *
-* @return	None.
+* @return    None.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 void StubHandler(const void *CallBackRef, u32 Bank, u32 Status)
@@ -800,6 +800,6 @@ void StubHandler(const void *CallBackRef, u32 Bank, u32 Status)
 	(void) Bank;
 	(void) Status;
 
-	Xil_AssertVoidAlways();
+    Xil_AssertVoidAlways();
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c

@@ -52,7 +52,7 @@
 * This function runs a self-test on the GPIO driver/device. This function
 * does a register read/write test on some of the Interrupt Registers.
 *
-* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param    InstancePtr is a pointer to the XGpioPs instance.
 *
 * @return
 *		- XST_SUCCESS if the self-test passed.
@@ -62,51 +62,51 @@
 ******************************************************************************/
 s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
 {
-	s32 Status = XST_SUCCESS;
-	u32 IntrEnabled;
-	u32 CurrentIntrType = 0U;
-	u32 CurrentIntrPolarity = 0U;
-	u32 CurrentIntrOnAny = 0U;
-	u32 IntrType = 0U;
-	u32 IntrPolarity = 0U;
-	u32 IntrOnAny = 0U;
-	u32 IntrTestValue = 0x22U;
-
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    s32 Status = XST_SUCCESS;
+    u32 IntrEnabled;
+    u32 CurrentIntrType = 0U;
+    u32 CurrentIntrPolarity = 0U;
+    u32 CurrentIntrOnAny = 0U;
+    u32 IntrType = 0U;
+    u32 IntrPolarity = 0U;
+    u32 IntrOnAny = 0U;
+    u32 IntrTestValue = 0x22U;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/* Disable the Interrupts for Bank 0 . */
-	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
-	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+    IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+    XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
 
 	/*
 	 * Get the Current Interrupt properties for Bank 0.
 	 * Set them to a known value, read it back and compare.
 	 */
-	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+    XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
 			     &CurrentIntrPolarity, &CurrentIntrOnAny);
 
-	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+    XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
 			     IntrTestValue, IntrTestValue);
 
-	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+    XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
 			     &IntrPolarity, &IntrOnAny);
 
-	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+    if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
 	    (IntrOnAny != IntrTestValue)) {
 
-		Status = XST_FAILURE;
+	    Status = XST_FAILURE;
 	}
 
 	/*
 	 * Restore the contents of all the interrupt registers modified in this
 	 * test.
 	 */
-	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+    XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
 			     CurrentIntrPolarity, CurrentIntrOnAny);
 
-	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+    XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
 
-	return Status;
+    return Status;
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c

@@ -13,7 +13,7 @@
 * This file contains the implementation of the XGpioPs driver's static
 * initialization functionality.
 *
-* @note		None.
+* @note	    None.
 *
 * <pre>
 *
@@ -50,26 +50,26 @@ extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
 * ID. The table XGpioPs_ConfigTable[] contains the configuration information
 * for each device in the system.
 *
-* @param	DeviceId is the unique device ID of the device being looked up.
+* @param    DeviceId is the unique device ID of the device being looked up.
 *
-* @return	A pointer to the configuration table entry corresponding to the
-*		given device ID, or NULL if no match is found.
+* @return    A pointer to the configuration table entry corresponding to the
+*	    given device ID, or NULL if no match is found.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
 {
-	XGpioPs_Config *CfgPtr = NULL;
-	u32 Index;
+    XGpioPs_Config *CfgPtr = NULL;
+    u32 Index;
 
-	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
-		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XGpioPs_ConfigTable[Index];
-			break;
+    for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+	    if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+		    CfgPtr = &XGpioPs_ConfigTable[Index];
+		    break;
 		}
 	}
 
-	return (XGpioPs_Config *)CfgPtr;
+    return (XGpioPs_Config *)CfgPtr;
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c

@@ -24,14 +24,14 @@
 * 2.2   hk     07/28/14 Make changes to enable use of data cache.
 * 2.3   sk     09/23/14 Send command for relative card address
 *                       when re-initialization is done.CR# 819614.
-*						Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.4	sk	   12/04/14 Added support for micro SD without
-* 						WP/CD. CR# 810655.
-*						Checked for DAT Inhibit mask instead of CMD
-* 						Inhibit mask in Cmd Transfer API.
-*						Added Support for SD Card v1.0
-* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*					    Use XSdPs_Change_ClkFreq API whenever changing
+*					    clock.CR# 816586.
+* 2.4    sk	   12/04/14 Added support for micro SD without
+* 					    WP/CD. CR# 810655.
+*					    Checked for DAT Inhibit mask instead of CMD
+* 					    Inhibit mask in Cmd Transfer API.
+*					    Added Support for SD Card v1.0
+* 2.5     sg	   07/09/15 Added SD 3.0 features
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
 * 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -102,96 +102,96 @@
 * Initializes a specific XSdPs instance such that the driver is ready to use.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ConfigPtr is a reference to a structure containing information
-*		about a specific SD device. This function initializes an
-*		InstancePtr object for a specific device specified by the
-*		contents of Config.
-* @param	EffectiveAddr is the device base address in the virtual memory
-*		address space. The caller is responsible for keeping the address
-*		mapping from EffectiveAddr to the device physical base address
-*		unchanged once this function is invoked. Unexpected errors may
-*		occur if the address mapping changes after this function is
-*		called. If address translation is not used, use
-*		ConfigPtr->Config.BaseAddress for this device.
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    ConfigPtr is a reference to a structure containing information
+*	    about a specific SD device. This function initializes an
+*	    InstancePtr object for a specific device specified by the
+*	    contents of Config.
+* @param    EffectiveAddr is the device base address in the virtual memory
+*	    address space. The caller is responsible for keeping the address
+*	    mapping from EffectiveAddr to the device physical base address
+*	    unchanged once this function is invoked. Unexpected errors may
+*	    occur if the address mapping changes after this function is
+*	    called. If address translation is not used, use
+*	    ConfigPtr->Config.BaseAddress for this device.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_DEVICE_IS_STARTED if the device is already started.
-*		It must be stopped to re-initialize.
+*	    It must be stopped to re-initialize.
 *
-* @note		This function initializes the host controller.
-*		Initial clock of 400KHz is set.
-*		Voltage of 3.3V is selected as that is supported by host.
-*		Interrupts status is enabled and signal disabled by default.
-*		Default data direction is card to host and
-*		32 bit ADMA2 is selected. Default Block size is 512 bytes.
+* @note	    This function initializes the host controller.
+*	    Initial clock of 400KHz is set.
+*	    Voltage of 3.3V is selected as that is supported by host.
+*	    Interrupts status is enabled and signal disabled by default.
+*	    Default data direction is card to host and
+*	    32 bit ADMA2 is selected. Default Block size is 512 bytes.
 *
 ******************************************************************************/
 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-				u32 EffectiveAddr)
+			    u32 EffectiveAddr)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(ConfigPtr != NULL);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
 
 #if defined  (XCLOCKING)
-	InstancePtr->Config.RefClk = ConfigPtr->RefClk;
-	Xil_ClockEnable(InstancePtr->Config.RefClk);
+    InstancePtr->Config.RefClk = ConfigPtr->RefClk;
+    Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 	/* If this API is getting called twice, return value accordingly */
-	if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
-		Status = (s32)XST_DEVICE_IS_STARTED;
-		goto RETURN_PATH ;
+    if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
+	    Status = (s32)XST_DEVICE_IS_STARTED;
+	    goto RETURN_PATH ;
 	}
 
 	/* Set some default values. */
-	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
-	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
-	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
-	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
-	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
-	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
-	InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
-	InstancePtr->SectorCount = 0U;
-	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
-	InstancePtr->OTapDelay = 0U;
-	InstancePtr->ITapDelay = 0U;
-	InstancePtr->Dma64BitAddr = 0U;
-	InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
+    InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+    InstancePtr->Config.BaseAddress = EffectiveAddr;
+    InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+    InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+    InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+    InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+    InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+    InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+    InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+    InstancePtr->SectorCount = 0U;
+    InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+    InstancePtr->OTapDelay = 0U;
+    InstancePtr->ITapDelay = 0U;
+    InstancePtr->Dma64BitAddr = 0U;
+    InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
 
 	/* Host Controller version is read. */
-	InstancePtr->HC_Version =
+    InstancePtr->HC_Version =
 			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+		    XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
 
 	/*
 	 * Read capabilities register and update it in Instance pointer.
 	 * It is sufficient to read this once on power on.
 	 */
-	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-						XSDPS_CAPS_OFFSET);
+    InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					    XSDPS_CAPS_OFFSET);
 
 	/* Reset the SD bus lines */
-	Status = XSdPs_ResetConfig(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
+    Status = XSdPs_ResetConfig(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH ;
 	}
 
 	/* Configure the SD Host Controller */
-	XSdPs_HostConfig(InstancePtr);
+    XSdPs_HostConfig(InstancePtr);
 
-	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
-	return Status;
+    return Status;
 
 }
 
@@ -202,69 +202,69 @@ RETURN_PATH:
 * Initialize Card with Identification mode sequence
 *
 *
-* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param    InstancePtr is a pointer to the instance to be worked on.
 *
 * @return
 * 		- XST_SUCCESS if initialization was successful
 * 		- XST_FAILURE if failure - could be because
-* 			a) SD is already initialized
-* 			b) There is no card inserted
-* 			c) One of the steps (commands) in the
+* 		    a) SD is already initialized
+* 		    b) There is no card inserted
+* 		    c) One of the steps (commands) in the
 *			   initialization cycle failed
 *
 *
 ******************************************************************************/
 s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/* Default settings */
-	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
-	InstancePtr->CardType = XSDPS_CARD_SD;
-	InstancePtr->Switch1v8 = 0U;
-	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+    InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+    InstancePtr->CardType = XSDPS_CARD_SD;
+    InstancePtr->Switch1v8 = 0U;
+    InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
 
 #if defined  (XCLOCKING)
-	Xil_ClockEnable(InstancePtr->Config.RefClk);
+    Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
 	/* Change the clock frequency to 400 KHz */
-	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
+    Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH ;
 	}
 
 	/* Identify the Card whether it is SD, MMC or eMMC */
-	Status = XSdPs_IdentifyCard(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_IdentifyCard(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Initialize the identified card */
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-		Status = XSdPs_SdCardInitialize(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+    if (InstancePtr->CardType == XSDPS_CARD_SD) {
+	    Status = XSdPs_SdCardInitialize(InstancePtr);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	} else {
-		Status = XSdPs_MmcCardInitialize(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_MmcCardInitialize(InstancePtr);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	}
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -272,48 +272,48 @@ RETURN_PATH:
 * @brief
 * This function performs SD read in polled mode.
 *
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Arg is the address passed by the user that is to be sent as
-* 		argument along with the command.
-* @param	BlkCnt - Block count passed by the user.
-* @param	Buff - Pointer to the data buffer for a DMA transfer.
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    Arg is the address passed by the user that is to be sent as
+* 	    argument along with the command.
+* @param    BlkCnt - Block count passed by the user.
+* @param    Buff - Pointer to the data buffer for a DMA transfer.
 *
 * @return
 * 		- XST_SUCCESS if initialization was successful
 * 		- XST_FAILURE if failure - could be because another transfer
-* 		is in progress or command or data inhibit is set
+* 	    is in progress or command or data inhibit is set
 *
 ******************************************************************************/
 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 #if defined  (XCLOCKING)
-	Xil_ClockEnable(InstancePtr->Config.RefClk);
+    Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
 	/* Setup the Read Transfer */
-	Status = XSdPs_SetupTransfer(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_SetupTransfer(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Read from the card */
-	Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -321,48 +321,48 @@ RETURN_PATH:
 * @brief
 * This function performs SD write in polled mode.
 *
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	Arg is the address passed by the user that is to be sent as
-* 		argument along with the command.
-* @param	BlkCnt - Block count passed by the user.
-* @param	Buff - Pointer to the data buffer for a DMA transfer.
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    Arg is the address passed by the user that is to be sent as
+* 	    argument along with the command.
+* @param    BlkCnt - Block count passed by the user.
+* @param    Buff - Pointer to the data buffer for a DMA transfer.
 *
 * @return
 * 		- XST_SUCCESS if initialization was successful
 * 		- XST_FAILURE if failure - could be because another transfer
-* 		is in progress or command or data inhibit is set
+* 	    is in progress or command or data inhibit is set
 *
 ******************************************************************************/
 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 #if defined  (XCLOCKING)
-	Xil_ClockEnable(InstancePtr->Config.RefClk);
+    Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
 	/* Setup the Write Transfer */
-	Status = XSdPs_SetupTransfer(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_SetupTransfer(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Write to the card */
-	Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -372,49 +372,49 @@ RETURN_PATH:
 * API to idle the SDIO Interface
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param    InstancePtr is a pointer to the XSdPs instance.
 *
-* @return	None
+* @return    None
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Idle(XSdPs *InstancePtr)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 #if defined  (XCLOCKING)
-	Xil_ClockEnable(InstancePtr->Config.RefClk);
+    Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
 	/* Check if the bus is idle */
-	Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
+    Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
 										| XSDPS_PSR_INHIBIT_DAT_MASK
 										| XSDPS_PSR_DAT_ACTIVE_MASK);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH ;
 	}
 
 	/* Disable the Bus Power */
-	XSdPs_DisableBusPower(InstancePtr);
+    XSdPs_DisableBusPower(InstancePtr);
 
 	/* Reset Command and Data Lines */
-	Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
+    Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH ;
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
-	Xil_ClockDisable(InstancePtr->Config.RefClk);
+    Xil_ClockDisable(InstancePtr->Config.RefClk);
 #endif
-	return Status;
+    return Status;
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h

@@ -83,14 +83,14 @@
 * 2.2   hk     07/28/14 Make changes to enable use of data cache.
 * 2.3   sk     09/23/14 Send command for relative card address
 *                       when re-initialization is done.CR# 819614.
-*						Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.4	sk	   12/04/14 Added support for micro SD without
-* 						WP/CD. CR# 810655.
-*						Checked for DAT Inhibit mask instead of CMD
-* 						Inhibit mask in Cmd Transfer API.
-*						Added Support for SD Card v1.0
-* 2.5 	sg		07/09/15 Added SD 3.0 features
+*					    Use XSdPs_Change_ClkFreq API whenever changing
+*					    clock.CR# 816586.
+* 2.4    sk	   12/04/14 Added support for micro SD without
+* 					    WP/CD. CR# 810655.
+*					    Checked for DAT Inhibit mask instead of CMD
+* 					    Inhibit mask in Cmd Transfer API.
+*					    Added Support for SD Card v1.0
+* 2.5     sg	    07/09/15 Added SD 3.0 features
 *       kvn     07/15/15 Modified the code according to MISRAC-2012.
 * 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
 * 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -119,7 +119,7 @@
 *       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
 *       sk     03/20/17 Add support for EL1 non-secure mode.
 * 3.3   mn     05/17/17 Add support for 64bit DMA addressing
-* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*     mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
 *       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
 *                       information.
 *       mn     09/06/17 Resolved compilation errors with IAR toolchain
@@ -155,38 +155,38 @@ extern "C" {
 
 /************************** Constant Definitions *****************************/
 
-#define XSDPS_CT_ERROR	0x2L	/**< Command timeout flag */
-#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
-#define MAX_TIMEOUT		0x1FFFFFFFU		/**< Maximum Timeout */
-#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
-#define XSDPS_RESPOCR_READY	0x80000000U
-#define XSDPS_ACMD41_HCS	0x40000000U
-#define XSDPS_ACMD41_3V3	0x00300000U
-#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
-#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
-#define HIGH_SPEED_SUPPORT	0x2U
-#define UHS_SDR12_SUPPORT	0x1U
-#define UHS_SDR25_SUPPORT	0x2U
-#define UHS_SDR50_SUPPORT	0x4U
-#define UHS_SDR104_SUPPORT	0x8U
-#define UHS_DDR50_SUPPORT	0x10U
-#define WIDTH_4_BIT_SUPPORT	0x4U
-#define SD_CLK_25_MHZ		25000000U
-#define SD_CLK_19_MHZ		19000000U
-#define SD_CLK_26_MHZ		26000000U
-#define EXT_CSD_DEVICE_TYPE_BYTE	196U
-#define EXT_CSD_SEC_COUNT_BYTE1		212U
-#define EXT_CSD_SEC_COUNT_BYTE2		213U
-#define EXT_CSD_SEC_COUNT_BYTE3		214U
-#define EXT_CSD_SEC_COUNT_BYTE4		215U
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
-#define CSD_SPEC_VER_3		0x3U
-#define SCR_SPEC_VER_3		0x80U
-#define ADDRESS_BEYOND_32BIT	0x100000000U
+#define XSDPS_CT_ERROR    0x2L	/**< Command timeout flag */
+#define MAX_TUNING_COUNT    40U		/**< Maximum Tuning count */
+#define MAX_TIMEOUT	    0x1FFFFFFFU		/**< Maximum Timeout */
+#define XSDPS_CMD8_VOL_PATTERN    0x1AAU
+#define XSDPS_RESPOCR_READY    0x80000000U
+#define XSDPS_ACMD41_HCS    0x40000000U
+#define XSDPS_ACMD41_3V3    0x00300000U
+#define XSDPS_CMD1_HIGH_VOL    0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL    0x00FF8010U
+#define HIGH_SPEED_SUPPORT    0x2U
+#define UHS_SDR12_SUPPORT    0x1U
+#define UHS_SDR25_SUPPORT    0x2U
+#define UHS_SDR50_SUPPORT    0x4U
+#define UHS_SDR104_SUPPORT    0x8U
+#define UHS_DDR50_SUPPORT    0x10U
+#define WIDTH_4_BIT_SUPPORT    0x4U
+#define SD_CLK_25_MHZ	    25000000U
+#define SD_CLK_19_MHZ	    19000000U
+#define SD_CLK_26_MHZ	    26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE    196U
+#define EXT_CSD_SEC_COUNT_BYTE1	    212U
+#define EXT_CSD_SEC_COUNT_BYTE2	    213U
+#define EXT_CSD_SEC_COUNT_BYTE3	    214U
+#define EXT_CSD_SEC_COUNT_BYTE4	    215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED		    0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED    0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED    0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200	    0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200	    0x20U
+#define CSD_SPEC_VER_3	    0x3U
+#define SCR_SPEC_VER_3	    0x80U
+#define ADDRESS_BEYOND_32BIT    0x100000000U
 
 /**************************** Type Definitions *******************************/
 
@@ -196,25 +196,25 @@ typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
  * This typedef contains configuration information for the device.
  */
 typedef struct {
-	u16 DeviceId;			/**< Unique ID  of device */
-	u32 BaseAddress;		/**< Base address of the device */
-	u32 InputClockHz;		/**< Input clock frequency */
-	u32 CardDetect;			/**< Card Detect */
-	u32 WriteProtect;			/**< Write Protect */
-	u32 BusWidth;			/**< Bus Width */
-	u32 BankNumber;			/**< MIO Bank selection for SD */
-	u32 HasEMIO;			/**< If SD is connected to EMIO */
-	u8 IsCacheCoherent; 		/**< If SD is Cache Coherent or not */
+    u16 DeviceId;			/**< Unique ID  of device */
+    u32 BaseAddress;		/**< Base address of the device */
+    u32 InputClockHz;		/**< Input clock frequency */
+    u32 CardDetect;			/**< Card Detect */
+    u32 WriteProtect;			/**< Write Protect */
+    u32 BusWidth;			/**< Bus Width */
+    u32 BankNumber;			/**< MIO Bank selection for SD */
+    u32 HasEMIO;			/**< If SD is connected to EMIO */
+    u8 IsCacheCoherent; 		/**< If SD is Cache Coherent or not */
 #if defined  (XCLOCKING)
-	u32 RefClk;			/**< Input clocks */
+    u32 RefClk;			/**< Input clocks */
 #endif
 } XSdPs_Config;
 
 /* ADMA2 32-Bit descriptor table */
 typedef struct {
-	u16 Attribute;		/**< Attributes of descriptor */
-	u16 Length;		/**< Length of current dma transfer */
-	u32 Address;		/**< Address of current dma transfer */
+    u16 Attribute;		/**< Attributes of descriptor */
+    u16 Length;		/**< Length of current dma transfer */
+    u32 Address;		/**< Address of current dma transfer */
 #ifdef __ICCARM__
 #pragma data_alignment = 32
 } XSdPs_Adma2Descriptor32;
@@ -224,9 +224,9 @@ typedef struct {
 
 /* ADMA2 64-Bit descriptor table */
 typedef struct {
-	u16 Attribute;		/**< Attributes of descriptor */
-	u16 Length;		/**< Length of current dma transfer */
-	u64 Address;		/**< Address of current dma transfer */
+    u16 Attribute;		/**< Attributes of descriptor */
+    u16 Length;		/**< Length of current dma transfer */
+    u64 Address;		/**< Address of current dma transfer */
 #ifdef __ICCARM__
 #pragma data_alignment = 32
 } XSdPs_Adma2Descriptor64;
@@ -240,28 +240,28 @@ typedef struct {
  * to a variable of this type is then passed to the driver API functions.
  */
 typedef struct {
-	XSdPs_Config Config;	/**< Configuration structure */
-	u32 IsReady;		/**< Device is initialized and ready */
-	u32 Host_Caps;		/**< Capabilities of host controller */
-	u32 Host_CapsExt;	/**< Extended Capabilities */
-	u32 HCS;		/**< High capacity support in card */
-	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
-	u8  Card_Version;	/**< Card version */
-	u8  HC_Version;		/**< Host controller version */
-	u8  BusWidth;		/**< Current operating bus width */
-	u32 BusSpeed;		/**< Current operating bus speed */
-	u8  Switch1v8;		/**< 1.8V Switch support */
-	u32 CardID[4];		/**< Card ID Register */
-	u32 RelCardAddr;	/**< Relative Card Address */
-	u32 CardSpecData[4];	/**< Card Specific Data Register */
-	u32 SectorCount;		/**< Sector Count */
-	u32 SdCardConfig;	/**< Sd Card Configuration Register */
-	u32 Mode;			/**< Bus Speed Mode */
-	u32 OTapDelay;		/**< Output Tap Delay */
-	u32 ITapDelay;		/**< Input Tap Delay */
-	u64 Dma64BitAddr;	/**< 64 Bit DMA Address */
-	u16 TransferMode;	/**< Transfer Mode */
-	u32 SlcrBaseAddr;	/**< SLCR base address*/
+    XSdPs_Config Config;	/**< Configuration structure */
+    u32 IsReady;		/**< Device is initialized and ready */
+    u32 Host_Caps;		/**< Capabilities of host controller */
+    u32 Host_CapsExt;	/**< Extended Capabilities */
+    u32 HCS;		/**< High capacity support in card */
+    u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+    u8  Card_Version;	/**< Card version */
+    u8  HC_Version;		/**< Host controller version */
+    u8  BusWidth;		/**< Current operating bus width */
+    u32 BusSpeed;		/**< Current operating bus speed */
+    u8  Switch1v8;		/**< 1.8V Switch support */
+    u32 CardID[4];		/**< Card ID Register */
+    u32 RelCardAddr;	/**< Relative Card Address */
+    u32 CardSpecData[4];	/**< Card Specific Data Register */
+    u32 SectorCount;		/**< Sector Count */
+    u32 SdCardConfig;	/**< Sd Card Configuration Register */
+    u32 Mode;			/**< Bus Speed Mode */
+    u32 OTapDelay;		/**< Output Tap Delay */
+    u32 ITapDelay;		/**< Input Tap Delay */
+    u64 Dma64BitAddr;	/**< 64 Bit DMA Address */
+    u16 TransferMode;	/**< Transfer Mode */
+    u32 SlcrBaseAddr;	/**< SLCR base address*/
 } XSdPs;
 
 /***************** Macros (Inline Functions) Definitions *********************/
@@ -269,7 +269,7 @@ typedef struct {
 /************************** Function Prototypes ******************************/
 XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-				u32 EffectiveAddr);
+			    u32 EffectiveAddr);
 s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c

@@ -6,9 +6,9 @@
 * DO NOT EDIT.
 *
 * Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT 
+* SPDX-License-Identifier: MIT
 
-* 
+*
 * Description: Driver configuration
 *
 *******************************************************************/
@@ -23,26 +23,26 @@
 XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
 {
 	{
-		XPAR_PSU_SD_0_DEVICE_ID,
-		XPAR_PSU_SD_0_BASEADDR,
-		XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
-		XPAR_PSU_SD_0_HAS_CD,
-		XPAR_PSU_SD_0_HAS_WP,
-		XPAR_PSU_SD_0_BUS_WIDTH,
-		XPAR_PSU_SD_0_MIO_BANK,
-		XPAR_PSU_SD_0_HAS_EMIO,
-		XPAR_PSU_SD_0_IS_CACHE_COHERENT
+	    XPAR_PSU_SD_0_DEVICE_ID,
+	    XPAR_PSU_SD_0_BASEADDR,
+	    XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
+	    XPAR_PSU_SD_0_HAS_CD,
+	    XPAR_PSU_SD_0_HAS_WP,
+	    XPAR_PSU_SD_0_BUS_WIDTH,
+	    XPAR_PSU_SD_0_MIO_BANK,
+	    XPAR_PSU_SD_0_HAS_EMIO,
+	    XPAR_PSU_SD_0_IS_CACHE_COHERENT
 	},
 	{
-		XPAR_PSU_SD_1_DEVICE_ID,
-		XPAR_PSU_SD_1_BASEADDR,
-		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
-		XPAR_PSU_SD_1_HAS_CD,
-		XPAR_PSU_SD_1_HAS_WP,
-		XPAR_PSU_SD_1_BUS_WIDTH,
-		XPAR_PSU_SD_1_MIO_BANK,
-		XPAR_PSU_SD_1_HAS_EMIO,
-		XPAR_PSU_SD_1_IS_CACHE_COHERENT
+	    XPAR_PSU_SD_1_DEVICE_ID,
+	    XPAR_PSU_SD_1_BASEADDR,
+	    XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+	    XPAR_PSU_SD_1_HAS_CD,
+	    XPAR_PSU_SD_1_HAS_WP,
+	    XPAR_PSU_SD_1_BUS_WIDTH,
+	    XPAR_PSU_SD_1_MIO_BANK,
+	    XPAR_PSU_SD_1_HAS_EMIO,
+	    XPAR_PSU_SD_1_IS_CACHE_COHERENT
 	}
 };
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c

@@ -22,8 +22,8 @@
 * 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
 *                       Add sleep for microblaze designs. CR# 781117.
 * 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-*						clock.CR# 816586.
-* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*					    clock.CR# 816586.
+* 2.5     sg	   07/09/15 Added SD 3.0 features
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
 *                       of SDR50, SDR104 and HS200.
@@ -43,8 +43,8 @@
 *       vns    03/13/17 Fixed MISRAC mandatory violation
 *       sk     03/20/17 Add support for EL1 non-secure mode.
 * 3.3   mn     07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
-*       mn     08/07/17	Properly set OTAPDLY value by clearing previous bit
-* 			settings
+*       mn     08/07/17    Properly set OTAPDLY value by clearing previous bit
+* 		    settings
 *       mn     08/17/17 Added CCI support for A53 and disabled data cache
 *                       operations when it is enabled.
 *       mn     08/22/17 Updated for Word Access System support
@@ -79,33 +79,33 @@
 * API to change clock freq to given value.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	SelFreq - Clock frequency in Hz.
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    SelFreq - Clock frequency in Hz.
 *
-* @return	None
+* @return    None
 *
-* @note		This API will change clock frequency to the value less than
-*		or equal to the given value using the permissible dividors.
+* @note	    This API will change clock frequency to the value less than
+*	    or equal to the given value using the permissible dividors.
 *
 ******************************************************************************/
 s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+    if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
 		/* Program the Tap delays */
-		XSdPs_SetTapDelay(InstancePtr);
+	    XSdPs_SetTapDelay(InstancePtr);
 	}
 
-	Status = XSdPs_SetClock(InstancePtr, SelFreq);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdPs_SetClock(InstancePtr, SelFreq);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -113,41 +113,41 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 * @brief
 * Update Block size for read/write operations.
 *
-* @param	InstancePtr is a pointer to the instance to be worked on.
-* @param	BlkSize - Block size passed by the user.
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    BlkSize - Block size passed by the user.
 *
-* @return	None
+* @return    None
 *
 ******************************************************************************/
 s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK
+    Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK
 											| XSDPS_PSR_INHIBIT_DAT_MASK
 											| XSDPS_PSR_WR_ACTIVE_MASK
 											| XSDPS_PSR_RD_ACTIVE_MASK));
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH ;
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH ;
 	}
 
 	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Set block size to the value passed */
-	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+    XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
 			 BlkSize & XSDPS_BLK_SIZE_MASK);
 
 RETURN_PATH:
-	return Status;
+    return Status;
 }
 
 /*****************************************************************************/
@@ -157,64 +157,64 @@ RETURN_PATH:
 * API to get bus width support by card.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	SCR - buffer to store SCR register returned by card.
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    SCR - buffer to store SCR register returned by card.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
 {
-	s32 Status;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
+    s32 Status;
+    u16 BlkCnt;
+    u16 BlkSize;
+    s32 LoopCnt;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
-		ReadBuff[LoopCnt] = 0U;
+    for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+	    ReadBuff[LoopCnt] = 0U;
 	}
 
 	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+		    InstancePtr->RelCardAddr, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
-	BlkCnt = XSDPS_SCR_BLKCNT;
-	BlkSize = XSDPS_SCR_BLKSIZE;
+    BlkCnt = XSDPS_SCR_BLKCNT;
+    BlkSize = XSDPS_SCR_BLKSIZE;
 
-	XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
+    XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
 
-	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Check for transfer done */
-	Status = XSdps_CheckTransferDone(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdps_CheckTransferDone(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	if (InstancePtr->Config.IsCacheCoherent == 0U) {
-		Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+    if (InstancePtr->Config.IsCacheCoherent == 0U) {
+	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
 				(INTPTR)BlkCnt * BlkSize);
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -225,99 +225,99 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
 * API to set bus width to 4-bit in card and host
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 {
-	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
+    s32 Status;
+    u32 StatusReg;
+    u32 Arg;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/*
 	 * check for bus width for 3.0 controller and return if
 	 * bus width is <4
 	 */
-	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+    if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
 			(InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
-		Status = XST_SUCCESS;
-		goto RETURN_PATH;
+	    Status = XST_SUCCESS;
+	    goto RETURN_PATH;
 	}
 
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+    if (InstancePtr->CardType == XSDPS_CARD_SD) {
 
-		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
-				0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+			    0U);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 
-		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	} else {
-		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-			if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-				Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+	    if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		    if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+			    Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
 			} else {
-				Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+			    Arg = XSDPS_MMC_8_BIT_BUS_ARG;
 			}
 		} else {
-			if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-				Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+		    if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+			    Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
 			} else {
-				Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+			    Arg = XSDPS_MMC_4_BIT_BUS_ARG;
 			}
 		}
 
-		Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	}
 
-	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+    usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
-	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL1_OFFSET);
+    StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				    XSDPS_HOST_CTRL1_OFFSET);
 
 	/* Width setting in controller */
-	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+    if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+	    StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
 	} else {
-		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	    StatusReg |= XSDPS_HC_WIDTH_MASK;
 	}
 
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL1_OFFSET,
+    XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+		    XSDPS_HOST_CTRL1_OFFSET,
 			(u8)StatusReg);
 
-	if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL2_OFFSET);
-		StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
-		StatusReg |= InstancePtr->Mode;
-		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
+    if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+	    StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				    XSDPS_HOST_CTRL2_OFFSET);
+	    StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
+	    StatusReg |= InstancePtr->Mode;
+	    XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				    XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -328,60 +328,60 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 * API to get bus speed supported by card.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ReadBuff - buffer to store function group support data
-*		returned by card.
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    ReadBuff - buffer to store function group support data
+*	    returned by card.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 {
-	s32 Status;
-	u32 Arg;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
+    s32 Status;
+    u32 Arg;
+    u16 BlkCnt;
+    u16 BlkSize;
+    s32 LoopCnt;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
-		ReadBuff[LoopCnt] = 0U;
+    for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+	    ReadBuff[LoopCnt] = 0U;
 	}
 
-	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
-	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+    BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+    BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
 
-	XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
+    XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
 
-	Arg = XSDPS_SWITCH_CMD_HS_GET;
+    Arg = XSDPS_SWITCH_CMD_HS_GET;
 
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Check for transfer done */
-	Status = XSdps_CheckTransferDone(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdps_CheckTransferDone(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	if (InstancePtr->Config.IsCacheCoherent == 0U) {
-		Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+    if (InstancePtr->Config.IsCacheCoherent == 0U) {
+	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
 				(INTPTR)BlkCnt * BlkSize);
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -392,59 +392,59 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 * API to get SD card status information.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	SdStatReg - buffer to store status data returned by card.
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    SdStatReg - buffer to store status data returned by card.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
 {
-	s32 Status;
-	u16 BlkCnt;
-	u16 BlkSize;
+    s32 Status;
+    u16 BlkCnt;
+    u16 BlkSize;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/* Send block write command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+		    InstancePtr->RelCardAddr, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
-	BlkCnt = XSDPS_SD_STATUS_BLKCNT;
-	BlkSize = XSDPS_SD_STATUS_BLKSIZE;
+    BlkCnt = XSDPS_SD_STATUS_BLKCNT;
+    BlkSize = XSDPS_SD_STATUS_BLKSIZE;
 
-	XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, SdStatReg);
+    XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, SdStatReg);
 
-	Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Check for transfer done */
-	Status = XSdps_CheckTransferDone(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdps_CheckTransferDone(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	if (InstancePtr->Config.IsCacheCoherent == 0U) {
-		Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
+    if (InstancePtr->Config.IsCacheCoherent == 0U) {
+	    Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
 				(INTPTR)BlkCnt * BlkSize);
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 }
 
 /*****************************************************************************/
@@ -454,65 +454,65 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
 * API to set high speed in card and host. Changes clock in host accordingly.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 {
-	s32 Status;
-	u32 StatusReg;
+    s32 Status;
+    u32 StatusReg;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	if (InstancePtr->CardType == XSDPS_CARD_SD) {
-		Status = XSdPs_Change_SdBusSpeed(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+    if (InstancePtr->CardType == XSDPS_CARD_SD) {
+	    Status = XSdPs_Change_SdBusSpeed(InstancePtr);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	} else {
-		Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	}
 
-	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
-	if ((InstancePtr->Mode == XSDPS_HS200_MODE) ||
+    if ((InstancePtr->Mode == XSDPS_HS200_MODE) ||
 		(InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
 		(InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
-		Status = XSdPs_Execute_Tuning(InstancePtr);
-		if (Status != XST_SUCCESS) {
-			Status = XST_FAILURE;
-			goto RETURN_PATH;
+	    Status = XSdPs_Execute_Tuning(InstancePtr);
+	    if (Status != XST_SUCCESS) {
+		    Status = XST_FAILURE;
+		    goto RETURN_PATH;
 		}
 	}
 
-	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+    usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
-	StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-					XSDPS_HOST_CTRL1_OFFSET);
-	StatusReg |= XSDPS_HC_SPEED_MASK;
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+    StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				    XSDPS_HOST_CTRL1_OFFSET);
+    StatusReg |= XSDPS_HC_SPEED_MASK;
+    XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+		    XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -523,58 +523,58 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 * API to get EXT_CSD register of eMMC.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	ReadBuff - buffer to store EXT_CSD
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    ReadBuff - buffer to store EXT_CSD
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 {
-	s32 Status;
-	u32 Arg = 0U;
-	u16 BlkCnt;
-	u16 BlkSize;
-	s32 LoopCnt;
+    s32 Status;
+    u32 Arg = 0U;
+    u16 BlkCnt;
+    u16 BlkSize;
+    s32 LoopCnt;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
-		ReadBuff[LoopCnt] = 0U;
+    for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+	    ReadBuff[LoopCnt] = 0U;
 	}
 
-	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
-	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+    BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+    BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
 
-	XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
+    XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
 
 	/* Send SEND_EXT_CSD command */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Check for transfer done */
-	Status = XSdps_CheckTransferDone(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdps_CheckTransferDone(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	if (InstancePtr->Config.IsCacheCoherent == 0U) {
-		Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+    if (InstancePtr->Config.IsCacheCoherent == 0U) {
+	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
 				(INTPTR)BlkCnt * BlkSize);
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -585,39 +585,39 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 * API to write EXT_CSD register of eMMC.
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
-* @param	Arg is the argument to be sent along with the command
+* @param    InstancePtr is a pointer to the XSdPs instance.
+* @param    Arg is the argument to be sent along with the command
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
 	/* Check for transfer done */
-	Status = XSdps_CheckTransferDone(InstancePtr);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
+    Status = XSdps_CheckTransferDone(InstancePtr);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -628,39 +628,39 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
 * API to send pullup command to card before using DAT line 3(using 4-bit bus)
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Pullup(XSdPs *InstancePtr)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-			InstancePtr->RelCardAddr, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+		    InstancePtr->RelCardAddr, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
-	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
-	if (Status != XST_SUCCESS) {
-		Status = XST_FAILURE;
-		goto RETURN_PATH;
+    Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+    if (Status != XST_SUCCESS) {
+	    Status = XST_FAILURE;
+	    goto RETURN_PATH;
 	}
 
-	Status = XST_SUCCESS;
+    Status = XST_SUCCESS;
 
-	RETURN_PATH:
-		return Status;
+    RETURN_PATH:
+	    return Status;
 
 }
 
@@ -671,28 +671,28 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr)
 * Selects card and sets default block size
 *
 *
-* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *		- XSDPS_CT_ERROR if Command Transfer fail.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 s32 XSdPs_Select_Card (XSdPs *InstancePtr)
 {
-	s32 Status;
+    s32 Status;
 
-	Xil_AssertNonvoid(InstancePtr != NULL);
-	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/* Send CMD7 - Select card */
-	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
-			InstancePtr->RelCardAddr, 0U);
+    Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+		    InstancePtr->RelCardAddr, 0U);
 
-	return Status;
+    return Status;
 }
 
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c

@@ -48,28 +48,28 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
 * Looks up the device configuration based on the unique device ID. A table
 * contains the configuration info for each device in the system.
 *
-* @param	DeviceId contains the ID of the device to look up the
-*		configuration for.
+* @param    DeviceId contains the ID of the device to look up the
+*	    configuration for.
 *
 * @return
 *
 * A pointer to the configuration found or NULL if the specified device ID was
 * not found. See xsdps.h for the definition of XSdPs_Config.
 *
-* @note		None.
+* @note	    None.
 *
 ******************************************************************************/
 XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
 {
-	XSdPs_Config *CfgPtr = NULL;
-	u32 Index;
+    XSdPs_Config *CfgPtr = NULL;
+    u32 Index;
 
-	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
-		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
-			CfgPtr = &XSdPs_ConfigTable[Index];
-			break;
+    for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+	    if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+		    CfgPtr = &XSdPs_ConfigTable[Index];
+		    break;
 		}
 	}
-	return (XSdPs_Config *)CfgPtr;
+    return (XSdPs_Config *)CfgPtr;
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h

@@ -13,15 +13,15 @@ extern "C" {
 
 static inline void usleep(unsigned long useconds)
 {
-	rt_uint32_t milliseconds = useconds/1000;
-	useconds = useconds%1000;
-	if (milliseconds) rt_thread_mdelay(milliseconds);
-	if (useconds) rt_hw_us_delay(useconds);
+    rt_uint32_t milliseconds = useconds/1000;
+    useconds = useconds%1000;
+    if (milliseconds) rt_thread_mdelay(milliseconds);
+    if (useconds) rt_hw_us_delay(useconds);
 }
 
 static inline void sleep(unsigned int seconds)
 {
-	rt_thread_delay(seconds*RT_TICK_PER_SECOND);
+    rt_thread_delay(seconds*RT_TICK_PER_SECOND);
 }
 
 #ifdef __cplusplus

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h

@@ -52,34 +52,34 @@ extern "C" {
 #include <netif/ethernetif.h>
 
 struct xemac_s {
-	enum xemac_types type;
-	int  topology_index;
-	void *state;
+    enum xemac_types type;
+    int  topology_index;
+    void *state;
 #if 0
     sys_sem_t sem_rx_data_available;
 #else
-	struct eth_device *rt_eth_device;
+    struct eth_device *rt_eth_device;
 #endif
 #if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
-	TimerHandle_t xTimer;
+    TimerHandle_t xTimer;
 #endif
 };
 
 enum ethernet_link_status {
-	ETH_LINK_UNDEFINED = 0,
-	ETH_LINK_UP,
-	ETH_LINK_DOWN,
-	ETH_LINK_NEGOTIATING
+    ETH_LINK_UNDEFINED = 0,
+    ETH_LINK_UP,
+    ETH_LINK_DOWN,
+    ETH_LINK_NEGOTIATING
 };
 
 void eth_link_detect(struct netif *netif);
-void 		lwip_raw_init();
-int 		xemacif_input(struct netif *netif);
-void 		xemacif_input_thread(struct netif *netif);
-struct netif *	xemac_add(struct netif *netif,
-	ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
-	unsigned char *mac_ethernet_address,
-	unsigned mac_baseaddr);
+void 	    lwip_raw_init();
+int 	    xemacif_input(struct netif *netif);
+void 	    xemacif_input_thread(struct netif *netif);
+struct netif *    xemac_add(struct netif *netif,
+    ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+    unsigned char *mac_ethernet_address,
+    unsigned mac_baseaddr);
 #if defined (__arm__) || defined (__aarch64__)
 void xemacpsif_resetrx_on_no_rxdata(struct netif *netif);
 #endif

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h

@@ -72,24 +72,24 @@ extern "C" {
 #define ZYNQMP_EMACPS_2_BASEADDR 0xFF0D0000
 #define ZYNQMP_EMACPS_3_BASEADDR 0xFF0E0000
 
-#define CRL_APB_GEM0_REF_CTRL	0xFF5E0050
-#define CRL_APB_GEM1_REF_CTRL	0xFF5E0054
-#define CRL_APB_GEM2_REF_CTRL	0xFF5E0058
-#define CRL_APB_GEM3_REF_CTRL	0xFF5E005C
+#define CRL_APB_GEM0_REF_CTRL    0xFF5E0050
+#define CRL_APB_GEM1_REF_CTRL    0xFF5E0054
+#define CRL_APB_GEM2_REF_CTRL    0xFF5E0058
+#define CRL_APB_GEM3_REF_CTRL    0xFF5E005C
 
-#define CRL_APB_GEM_DIV0_MASK	0x00003F00
-#define CRL_APB_GEM_DIV0_SHIFT	8
-#define CRL_APB_GEM_DIV1_MASK	0x003F0000
-#define CRL_APB_GEM_DIV1_SHIFT	16
+#define CRL_APB_GEM_DIV0_MASK    0x00003F00
+#define CRL_APB_GEM_DIV0_SHIFT    8
+#define CRL_APB_GEM_DIV1_MASK    0x003F0000
+#define CRL_APB_GEM_DIV1_SHIFT    16
 
 #define VERSAL_EMACPS_0_BASEADDR 0xFF0C0000
 #define VERSAL_EMACPS_1_BASEADDR 0xFF0D0000
 
-#define VERSAL_CRL_GEM0_REF_CTRL	0xFF5E0118
-#define VERSAL_CRL_GEM1_REF_CTRL	0xFF5E011C
+#define VERSAL_CRL_GEM0_REF_CTRL    0xFF5E0118
+#define VERSAL_CRL_GEM1_REF_CTRL    0xFF5E011C
 
-#define VERSAL_CRL_GEM_DIV_MASK		0x0003FF00
-#define VERSAL_CRL_APB_GEM_DIV_SHIFT	8
+#define VERSAL_CRL_GEM_DIV_MASK	    0x0003FF00
+#define VERSAL_CRL_APB_GEM_DIV_SHIFT    8
 
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
 #if defined (USE_JUMBO_FRAMES)
@@ -97,40 +97,40 @@ extern "C" {
 #endif
 #endif
 
-#define GEM_VERSION_ZYNQMP	7
-#define GEM_VERSION_VERSAL	0x107
+#define GEM_VERSION_ZYNQMP    7
+#define GEM_VERSION_VERSAL    0x107
 
 #define MAX_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE)
 
-void 	xemacpsif_setmac(u32_t index, u8_t *addr);
-u8_t*	xemacpsif_getmac(u32_t index);
-err_t 	xemacpsif_init(struct netif *netif);
-s32_t 	xemacpsif_input(struct netif *netif);
+void     xemacpsif_setmac(u32_t index, u8_t *addr);
+u8_t*    xemacpsif_getmac(u32_t index);
+err_t     xemacpsif_init(struct netif *netif);
+s32_t     xemacpsif_input(struct netif *netif);
 
 /* xaxiemacif_hw.c */
-void 	xemacps_error_handler(XEmacPs * Temac);
+void     xemacps_error_handler(XEmacPs * Temac);
 
 /* structure within each netif, encapsulating all information required for
  * using a particular temac instance
  */
 typedef struct {
-	XEmacPs emacps;
+    XEmacPs emacps;
 
 	/* queue to store overflow packets */
-	pq_queue_t *recv_q;
-	pq_queue_t *send_q;
+    pq_queue_t *recv_q;
+    pq_queue_t *send_q;
 
 	/* pointers to memory holding buffer descriptors (used only with SDMA) */
-	void *rx_bdspace;
-	void *tx_bdspace;
+    void *rx_bdspace;
+    void *tx_bdspace;
 
-	unsigned int last_rx_frms_cntr;
+    unsigned int last_rx_frms_cntr;
 
 } xemacpsif_s;
 
 extern xemacpsif_s xemacpsif;
 
-s32_t	is_tx_space_available(xemacpsif_s *emac);
+s32_t    is_tx_space_available(xemacpsif_s *emac);
 
 /* xemacpsif_dma.c */
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h

@@ -38,14 +38,14 @@ extern "C" {
 #define PQ_QUEUE_SIZE 4096
 
 typedef struct {
-	void *data[PQ_QUEUE_SIZE];
-	int head, tail, len;
+    void *data[PQ_QUEUE_SIZE];
+    int head, tail, len;
 } pq_queue_t;
 
-pq_queue_t*	pq_create_queue();
-int 		pq_enqueue(pq_queue_t *q, void *p);
-void*		pq_dequeue(pq_queue_t *q);
-int		pq_qlength(pq_queue_t *q);
+pq_queue_t*    pq_create_queue();
+int 	    pq_enqueue(pq_queue_t *q, void *p);
+void*	    pq_dequeue(pq_queue_t *q);
+int	    pq_qlength(pq_queue_t *q);
 
 #ifdef __cplusplus
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h

@@ -38,12 +38,12 @@ extern "C" {
 enum xemac_types { xemac_type_unknown = -1, xemac_type_xps_emaclite, xemac_type_xps_ll_temac, xemac_type_axi_ethernet, xemac_type_emacps };
 
 struct xtopology_t {
-	unsigned emac_baseaddr;
-	enum xemac_types emac_type;
-	unsigned intc_baseaddr;
-	unsigned intc_emac_intr;	/* valid only for xemac_type_xps_emaclite */
-	unsigned scugic_baseaddr; /* valid only for Zynq */
-	unsigned scugic_emac_intr; /* valid only for GEM */
+    unsigned emac_baseaddr;
+    enum xemac_types emac_type;
+    unsigned intc_baseaddr;
+    unsigned intc_emac_intr;	/* valid only for xemac_type_xps_emaclite */
+    unsigned scugic_baseaddr; /* valid only for Zynq */
+    unsigned scugic_emac_intr; /* valid only for GEM */
 };
 
 extern int xtopology_n_emacs;

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c

@@ -83,12 +83,12 @@ u32_t phyaddrforemac;
 void
 lwip_raw_init()
 {
-	ip_init();	/* Doesn't do much, it should be called to handle future changes. */
+    ip_init();	/* Doesn't do much, it should be called to handle future changes. */
 #if LWIP_UDP
-	udp_init();	/* Clears the UDP PCB list. */
+    udp_init();	/* Clears the UDP PCB list. */
 #endif
 #if LWIP_TCP
-	tcp_init();	/* Clears the TCP PCB list and clears some internal TCP timers. */
+    tcp_init();	/* Clears the TCP PCB list and clears some internal TCP timers. */
 			/* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
 			/* predefined regular intervals after this initialization. */
 #endif
@@ -97,27 +97,27 @@ lwip_raw_init()
 static enum xemac_types
 find_mac_type(unsigned base)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < xtopology_n_emacs; i++) {
-		if (xtopology[i].emac_baseaddr == base)
-			return xtopology[i].emac_type;
+    for (i = 0; i < xtopology_n_emacs; i++) {
+	    if (xtopology[i].emac_baseaddr == base)
+		    return xtopology[i].emac_type;
 	}
 
-	return xemac_type_unknown;
+    return xemac_type_unknown;
 }
 
 int
 xtopology_find_index(unsigned base)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < xtopology_n_emacs; i++) {
-		if (xtopology[i].emac_baseaddr == base)
-			return i;
+    for (i = 0; i < xtopology_n_emacs; i++) {
+	    if (xtopology[i].emac_baseaddr == base)
+		    return i;
 	}
 
-	return -1;
+    return -1;
 }
 
 /*
@@ -128,72 +128,72 @@ xtopology_find_index(unsigned base)
  */
 struct netif *
 xemac_add(struct netif *netif,
-	ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
-	unsigned char *mac_ethernet_address,
-	unsigned mac_baseaddr)
+    ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+    unsigned char *mac_ethernet_address,
+    unsigned mac_baseaddr)
 {
-	int i;
+    int i;
 
 #ifdef OS_IS_FREERTOS
 	/* Start thread to detect link periodically for Hot Plug autodetect */
-	sys_thread_new("link_detect_thread", link_detect_thread, netif,
-			THREAD_STACKSIZE, tskIDLE_PRIORITY);
+    sys_thread_new("link_detect_thread", link_detect_thread, netif,
+		    THREAD_STACKSIZE, tskIDLE_PRIORITY);
 #endif
 
 	/* set mac address */
-	netif->hwaddr_len = 6;
-	for (i = 0; i < 6; i++)
-		netif->hwaddr[i] = mac_ethernet_address[i];
+    netif->hwaddr_len = 6;
+    for (i = 0; i < 6; i++)
+	    netif->hwaddr[i] = mac_ethernet_address[i];
 
 	/* initialize based on MAC type */
-		switch (find_mac_type(mac_baseaddr)) {
-			case xemac_type_xps_emaclite:
+	    switch (find_mac_type(mac_baseaddr)) {
+		    case xemac_type_xps_emaclite:
 #ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
-				return netif_add(netif, ipaddr, netmask, gw,
+			    return netif_add(netif, ipaddr, netmask, gw,
 					(void*)(UINTPTR)mac_baseaddr,
-					xemacliteif_init,
+				    xemacliteif_init,
 #if NO_SYS
-					ethernet_input
+				    ethernet_input
 #else
-					tcpip_input
+				    tcpip_input
 #endif
 					);
 #else
-				return NULL;
+			    return NULL;
 #endif
-			case xemac_type_axi_ethernet:
+		    case xemac_type_axi_ethernet:
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
-				return netif_add(netif, ipaddr, netmask, gw,
+			    return netif_add(netif, ipaddr, netmask, gw,
 					(void*)(UINTPTR)mac_baseaddr,
-					xaxiemacif_init,
+				    xaxiemacif_init,
 #if NO_SYS
-					ethernet_input
+				    ethernet_input
 #else
-					tcpip_input
+				    tcpip_input
 #endif
 					);
 #else
-				return NULL;
+			    return NULL;
 #endif
 #if defined (__arm__) || defined (__aarch64__)
-			case xemac_type_emacps:
+		    case xemac_type_emacps:
 #ifdef XLWIP_CONFIG_INCLUDE_GEM
-				return netif_add(netif, ipaddr, netmask, gw,
+			    return netif_add(netif, ipaddr, netmask, gw,
 						(void*)(UINTPTR)mac_baseaddr,
-						xemacpsif_init,
+					    xemacpsif_init,
 #if NO_SYS
-						ethernet_input
+					    ethernet_input
 #else
-						tcpip_input
+					    tcpip_input
 #endif
 
 						);
 #endif
 #endif
-			default:
-				xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
-						mac_baseaddr);
-				return NULL;
+		    default:
+			    xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
+					    mac_baseaddr);
+			    return NULL;
 	}
 }
 
@@ -206,16 +206,16 @@ xemac_add(struct netif *netif,
 void
 xemacif_input_thread(struct netif *netif)
 {
-	struct xemac_s *emac = (struct xemac_s *)netif->state;
-	while (1) {
+    struct xemac_s *emac = (struct xemac_s *)netif->state;
+    while (1) {
 		/* sleep until there are packets to process
 		 * This semaphore is set by the packet receive interrupt
 		 * routine.
 		 */
-		sys_sem_wait(&emac->sem_rx_data_available);
+	    sys_sem_wait(&emac->sem_rx_data_available);
 
 		/* move all received packets to lwIP */
-		xemacif_input(netif);
+	    xemacif_input(netif);
 	}
 }
 #endif
@@ -223,210 +223,210 @@ xemacif_input_thread(struct netif *netif)
 int
 xemacif_input(struct netif *netif)
 {
-	struct xemac_s *emac = (struct xemac_s *)netif->state;
+    struct xemac_s *emac = (struct xemac_s *)netif->state;
 
-	int n_packets = 0;
+    int n_packets = 0;
 
-	switch (emac->type) {
-		case xemac_type_xps_emaclite:
+    switch (emac->type) {
+	    case xemac_type_xps_emaclite:
 #ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
-			n_packets = xemacliteif_input(netif);
-			break;
+		    n_packets = xemacliteif_input(netif);
+		    break;
 #else
 			// print("incorrect configuration: xps_ethernetlite drivers not present?");
-			while(1);
-			return 0;
+		    while(1);
+		    return 0;
 #endif
-		case xemac_type_axi_ethernet:
+	    case xemac_type_axi_ethernet:
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
-			n_packets = xaxiemacif_input(netif);
-			break;
+		    n_packets = xaxiemacif_input(netif);
+		    break;
 #else
 			// print("incorrect configuration: axi_ethernet drivers not present?");
-			while(1);
-			return 0;
+		    while(1);
+		    return 0;
 #endif
 #if defined (__arm__) || defined (__aarch64__)
-		case xemac_type_emacps:
+	    case xemac_type_emacps:
 #ifdef XLWIP_CONFIG_INCLUDE_GEM
-			n_packets = xemacpsif_input(netif);
-			break;
+		    n_packets = xemacpsif_input(netif);
+		    break;
 #else
-			xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
-			while(1);
-			return 0;
+		    xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
+		    while(1);
+		    return 0;
 #endif
 #endif
-		default:
+	    default:
 			// print("incorrect configuration: unknown temac type");
-			while(1);
-			return 0;
+		    while(1);
+		    return 0;
 	}
 
-	return n_packets;
+    return n_packets;
 }
 
 #if defined(XLWIP_CONFIG_INCLUDE_GEM)
 u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_LINK_STATUS)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_LINK_STATUS)
+	    return 1;
+    return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
 static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_LINK_STATUS)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_LINK_STATUS)
+	    return 1;
+    return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
 static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_LINK_STATUS)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_LINK_STATUS)
+	    return 1;
+    return 0;
 }
 #endif
 
 #if defined(XLWIP_CONFIG_INCLUDE_GEM)
 u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+	    return 1;
+    return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
 static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+	    return 1;
+    return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
 static u32_t phy_autoneg_status(XEmacLite *xemacp, u32_t phy_addr)
 {
-	u16_t status;
+    u16_t status;
 
 	/* Read Phy Status register twice to get the confirmation of the current
 	 * link status.
 	 */
-	XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
-	if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-		return 1;
-	return 0;
+    if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+	    return 1;
+    return 0;
 }
 #endif
 
 void eth_link_detect(struct netif *netif)
 {
-	u32_t link_speed, phy_link_status;
-	struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+    u32_t link_speed, phy_link_status;
+    struct xemac_s *xemac = (struct xemac_s *)(netif->state);
 
 #if defined(XLWIP_CONFIG_INCLUDE_GEM)
-	xemacpsif_s *xemacs = (xemacpsif_s *)(xemac->state);
-	XEmacPs *xemacp = &xemacs->emacps;
+    xemacpsif_s *xemacs = (xemacpsif_s *)(xemac->state);
+    XEmacPs *xemacp = &xemacs->emacps;
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
-	xaxiemacif_s *xemacs = (xaxiemacif_s *)(xemac->state);
-	XAxiEthernet *xemacp = &xemacs->axi_ethernet;
+    xaxiemacif_s *xemacs = (xaxiemacif_s *)(xemac->state);
+    XAxiEthernet *xemacp = &xemacs->axi_ethernet;
 #elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
-	xemacliteif_s *xemacs = (xemacliteif_s *)(xemac->state);
-	XEmacLite *xemacp = xemacs->instance;
+    xemacliteif_s *xemacs = (xemacliteif_s *)(xemac->state);
+    XEmacLite *xemacp = xemacs->instance;
 #endif
 
-	if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
+    if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
 			(eth_link_status == ETH_LINK_UNDEFINED))
-		return;
-
-	phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
-
-	if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
-		eth_link_status = ETH_LINK_DOWN;
-
-	switch (eth_link_status) {
-		case ETH_LINK_UNDEFINED:
-		case ETH_LINK_UP:
-			return;
-		case ETH_LINK_DOWN:
-			netif_set_link_down(netif);
-			eth_link_status = ETH_LINK_NEGOTIATING;
-			xil_printf("Ethernet Link down\r\n");
-			break;
-		case ETH_LINK_NEGOTIATING:
-			if (phy_link_status &&
-				phy_autoneg_status(xemacp, phyaddrforemac)) {
+	    return;
+
+    phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
+
+    if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
+	    eth_link_status = ETH_LINK_DOWN;
+
+    switch (eth_link_status) {
+	    case ETH_LINK_UNDEFINED:
+	    case ETH_LINK_UP:
+		    return;
+	    case ETH_LINK_DOWN:
+		    netif_set_link_down(netif);
+		    eth_link_status = ETH_LINK_NEGOTIATING;
+		    xil_printf("Ethernet Link down\r\n");
+		    break;
+	    case ETH_LINK_NEGOTIATING:
+		    if (phy_link_status &&
+			    phy_autoneg_status(xemacp, phyaddrforemac)) {
 
 				/* Initiate Phy setup to get link speed */
 #if defined(XLWIP_CONFIG_INCLUDE_GEM)
-				link_speed = phy_setup_emacps(xemacp,
-								phyaddrforemac);
-				XEmacPs_SetOperatingSpeed(xemacp, link_speed);
+			    link_speed = phy_setup_emacps(xemacp,
+							    phyaddrforemac);
+			    XEmacPs_SetOperatingSpeed(xemacp, link_speed);
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
-				link_speed = phy_setup_axiemac(xemacp);
-				XAxiEthernet_SetOperatingSpeed(xemacp,
+			    link_speed = phy_setup_axiemac(xemacp);
+			    XAxiEthernet_SetOperatingSpeed(xemacp,
 							       link_speed);
 #endif
-				netif_set_link_up(netif);
-				eth_link_status = ETH_LINK_UP;
-				xil_printf("Ethernet Link up\r\n");
+			    netif_set_link_up(netif);
+			    eth_link_status = ETH_LINK_UP;
+			    xil_printf("Ethernet Link up\r\n");
 			}
-			break;
+		    break;
 	}
 }
 
 #ifdef OS_IS_FREERTOS
 void link_detect_thread(void *p)
 {
-	struct netif *netif = (struct netif *) p;
+    struct netif *netif = (struct netif *) p;
 
-	while (1) {
+    while (1) {
 		/* Call eth_link_detect() every second to detect Ethernet link
 		 * change.
 		 */
-		eth_link_detect(netif);
-		vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
+	    eth_link_detect(netif);
+	    vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
 	}
 }
 #endif

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h

@@ -44,7 +44,7 @@
 
 
 #define ADVERTISE_100_AND_10        (ADVERTISE_10FULL | ADVERTISE_100FULL | \
-					ADVERTISE_10HALF | ADVERTISE_100HALF)
+				    ADVERTISE_10HALF | ADVERTISE_100HALF)
 #define ADVERTISE_100               (ADVERTISE_100FULL | ADVERTISE_100HALF)
 #define ADVERTISE_10                (ADVERTISE_10FULL | ADVERTISE_10HALF)
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c

@@ -76,14 +76,14 @@
 
 #if LWIP_IGMP
 static err_t xemacpsif_mac_filter_update (struct netif *netif,
-							ip_addr_t *group, u8_t action);
+						    ip_addr_t *group, u8_t action);
 
 static u8_t xemacps_mcast_entry_mask = 0;
 #endif
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
 static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif,
-							ip_addr_t *group, u8_t action);
+						    ip_addr_t *group, u8_t action);
 
 static u8_t xemacps_mld6_mcast_entry_mask;
 #endif
@@ -101,29 +101,29 @@ int32_t lExpireCounter = 0;
  * this function also assumes that there are available BD's
  */
 err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif,
-													struct pbuf *p)
+												    struct pbuf *p)
 {
-	XStatus status = 0;
+    XStatus status = 0;
 
 #if ETH_PAD_SIZE
-	pbuf_header(p, -ETH_PAD_SIZE);	/* drop the padding word */
+    pbuf_header(p, -ETH_PAD_SIZE);	/* drop the padding word */
 #endif
-	status = emacps_sgsend(xemacpsif, p);
-	if (status != XST_SUCCESS) {
+    status = emacps_sgsend(xemacpsif, p);
+    if (status != XST_SUCCESS) {
 #if LINK_STATS
-	lwip_stats.link.drop++;
+    lwip_stats.link.drop++;
 #endif
 	}
 
 #if ETH_PAD_SIZE
-	pbuf_header(p, ETH_PAD_SIZE);	/* reclaim the padding word */
+    pbuf_header(p, ETH_PAD_SIZE);	/* reclaim the padding word */
 #endif
 
 #if LINK_STATS
-	lwip_stats.link.xmit++;
+    lwip_stats.link.xmit++;
 #endif /* LINK_STATS */
 
-	return ERR_OK;
+    return ERR_OK;
 
 }
 
@@ -138,36 +138,36 @@ err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif,
 
 static err_t low_level_output(struct netif *netif, struct pbuf *p)
 {
-	SYS_ARCH_DECL_PROTECT(lev);
+    SYS_ARCH_DECL_PROTECT(lev);
     err_t err;
     s32_t freecnt;
     XEmacPs_BdRing *txring;
 
-	struct xemac_s *xemac = (struct xemac_s *)(netif->state);
-	xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+    struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+    xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
 
-	SYS_ARCH_PROTECT(lev);
+    SYS_ARCH_PROTECT(lev);
 
 	/* check if space is available to send */
     freecnt = is_tx_space_available(xemacpsif);
     if (freecnt <= 5) {
-	txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
-		process_sent_bds(xemacpsif, txring);
+    txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+	    process_sent_bds(xemacpsif, txring);
 	}
 
     if (is_tx_space_available(xemacpsif)) {
-		_unbuffered_low_level_output(xemacpsif, p);
-		err = ERR_OK;
+	    _unbuffered_low_level_output(xemacpsif, p);
+	    err = ERR_OK;
 	} else {
 #if LINK_STATS
-		lwip_stats.link.drop++;
+	    lwip_stats.link.drop++;
 #endif
-		rt_kprintf("pack dropped, no space\r\n");
-		err = ERR_MEM;
+	    rt_kprintf("pack dropped, no space\r\n");
+	    err = ERR_MEM;
 	}
 
-	SYS_ARCH_UNPROTECT(lev);
-	return err;
+    SYS_ARCH_UNPROTECT(lev);
+    return err;
 }
 
 /*
@@ -179,17 +179,17 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
  */
 static struct pbuf * low_level_input(struct netif *netif)
 {
-	struct xemac_s *xemac = (struct xemac_s *)(netif->state);
-	xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
-	struct pbuf *p;
+    struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+    xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+    struct pbuf *p;
 
 	/* see if there is data to process */
-	if (pq_qlength(xemacpsif->recv_q) == 0)
-		return NULL;
+    if (pq_qlength(xemacpsif->recv_q) == 0)
+	    return NULL;
 
 	/* return one packet from receive q */
-	p = (struct pbuf *)pq_dequeue(xemacpsif->recv_q);
-	return p;
+    p = (struct pbuf *)pq_dequeue(xemacpsif->recv_q);
+    return p;
 }
 
 /*
@@ -202,10 +202,10 @@ static struct pbuf * low_level_input(struct netif *netif)
  */
 
 static err_t xemacpsif_output(struct netif *netif, struct pbuf *p,
-		const ip_addr_t *ipaddr)
+	    const ip_addr_t *ipaddr)
 {
 	/* resolve hardware address, then send (or queue) packet */
-	return etharp_output(netif, p, ipaddr);
+    return etharp_output(netif, p, ipaddr);
 }
 
 /*
@@ -223,60 +223,60 @@ static err_t xemacpsif_output(struct netif *netif, struct pbuf *p,
 
 s32_t xemacpsif_input(struct netif *netif)
 {
-	struct eth_hdr *ethhdr;
-	struct pbuf *p;
-	SYS_ARCH_DECL_PROTECT(lev);
+    struct eth_hdr *ethhdr;
+    struct pbuf *p;
+    SYS_ARCH_DECL_PROTECT(lev);
 
 #ifdef OS_IS_FREERTOS
-	while (1)
+    while (1)
 #endif
 	{
 		/* move received packet into a new pbuf */
-		SYS_ARCH_PROTECT(lev);
-		p = low_level_input(netif);
-		SYS_ARCH_UNPROTECT(lev);
+	    SYS_ARCH_PROTECT(lev);
+	    p = low_level_input(netif);
+	    SYS_ARCH_UNPROTECT(lev);
 
 		/* no packet could be read, silently ignore this */
-		if (p == NULL) {
-			return 0;
+	    if (p == NULL) {
+		    return 0;
 		}
 
 		/* points to packet payload, which starts with an Ethernet header */
-		ethhdr = p->payload;
+	    ethhdr = p->payload;
 
 	#if LINK_STATS
-		lwip_stats.link.recv++;
+	    lwip_stats.link.recv++;
 	#endif /* LINK_STATS */
 
-		switch (htons(ethhdr->type)) {
+	    switch (htons(ethhdr->type)) {
 			/* IP or ARP packet? */
-			case ETHTYPE_IP:
-			case ETHTYPE_ARP:
+		    case ETHTYPE_IP:
+		    case ETHTYPE_ARP:
 	#if LWIP_IPV6
 			/*IPv6 Packet?*/
-			case ETHTYPE_IPV6:
+		    case ETHTYPE_IPV6:
 	#endif
 	#if PPPOE_SUPPORT
 				/* PPPoE packet? */
-			case ETHTYPE_PPPOEDISC:
-			case ETHTYPE_PPPOE:
+		    case ETHTYPE_PPPOEDISC:
+		    case ETHTYPE_PPPOE:
 	#endif /* PPPOE_SUPPORT */
 				/* full packet send to tcpip_thread to process */
-				if (netif->input(p, netif) != ERR_OK) {
-					LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n"));
-					pbuf_free(p);
-					p = NULL;
+			    if (netif->input(p, netif) != ERR_OK) {
+				    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n"));
+				    pbuf_free(p);
+				    p = NULL;
 				}
-				break;
+			    break;
 
-			default:
-				pbuf_free(p);
-				p = NULL;
-				break;
+		    default:
+			    pbuf_free(p);
+			    p = NULL;
+			    break;
 		}
 	}
 
-	return 1;
+    return 1;
 }
 
 
@@ -284,419 +284,419 @@ s32_t xemacpsif_input(struct netif *netif)
 void vTimerCallback( TimerHandle_t pxTimer )
 {
 	/* Do something if the pxTimer parameter is NULL */
-	configASSERT(pxTimer);
+    configASSERT(pxTimer);
 
-	lExpireCounter++;
+    lExpireCounter++;
 	/* If the timer has expired 100 times then reset RX */
-	if(lExpireCounter >= RESETRXTIMEOUT) {
-		lExpireCounter = 0;
-		xemacpsif_resetrx_on_no_rxdata(NetIf);
+    if(lExpireCounter >= RESETRXTIMEOUT) {
+	    lExpireCounter = 0;
+	    xemacpsif_resetrx_on_no_rxdata(NetIf);
 	}
 }
  #endif
 
 static err_t low_level_init(struct netif *netif)
 {
-	UINTPTR mac_address = (UINTPTR)(netif->state);
-	struct xemac_s *xemac;
-	xemacpsif_s *xemacpsif;
-	u32 dmacrreg;
+    UINTPTR mac_address = (UINTPTR)(netif->state);
+    struct xemac_s *xemac;
+    xemacpsif_s *xemacpsif;
+    u32 dmacrreg;
 
-	s32_t status = XST_SUCCESS;
+    s32_t status = XST_SUCCESS;
 
-	NetIf = netif;
+    NetIf = netif;
 
-	xemacpsif = mem_malloc(sizeof *xemacpsif);
-	if (xemacpsif == NULL) {
-		LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
-		return ERR_MEM;
+    xemacpsif = mem_malloc(sizeof *xemacpsif);
+    if (xemacpsif == NULL) {
+	    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+	    return ERR_MEM;
 	}
 
-	xemac = mem_malloc(sizeof *xemac);
-	if (xemac == NULL) {
-		LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
-		return ERR_MEM;
+    xemac = mem_malloc(sizeof *xemac);
+    if (xemac == NULL) {
+	    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+	    return ERR_MEM;
 	}
 
-	xemac->state = (void *)xemacpsif;
-	xemac->topology_index = xtopology_find_index(mac_address);
-	xemac->type = xemac_type_emacps;
+    xemac->state = (void *)xemacpsif;
+    xemac->topology_index = xtopology_find_index(mac_address);
+    xemac->type = xemac_type_emacps;
 
-	xemacpsif->send_q = NULL;
-	xemacpsif->recv_q = pq_create_queue();
-	if (!xemacpsif->recv_q)
-		return ERR_MEM;
+    xemacpsif->send_q = NULL;
+    xemacpsif->recv_q = pq_create_queue();
+    if (!xemacpsif->recv_q)
+	    return ERR_MEM;
 
 	/* maximum transfer unit */
 #ifdef ZYNQMP_USE_JUMBO
-	netif->mtu = XEMACPS_MTU_JUMBO - XEMACPS_HDR_SIZE;
+    netif->mtu = XEMACPS_MTU_JUMBO - XEMACPS_HDR_SIZE;
 #else
-	netif->mtu = XEMACPS_MTU - XEMACPS_HDR_SIZE;
+    netif->mtu = XEMACPS_MTU - XEMACPS_HDR_SIZE;
 #endif
 
 #if LWIP_IGMP
-	netif->igmp_mac_filter = xemacpsif_mac_filter_update;
+    netif->igmp_mac_filter = xemacpsif_mac_filter_update;
 #endif
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
  netif->mld_mac_filter = xemacpsif_mld6_mac_filter_update;
 #endif
 
-	netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
-											NETIF_FLAG_LINK_UP;
+    netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
+										    NETIF_FLAG_LINK_UP;
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
-	netif->flags |= NETIF_FLAG_MLD6;
+    netif->flags |= NETIF_FLAG_MLD6;
 #endif
 
 #if LWIP_IGMP
-	netif->flags |= NETIF_FLAG_IGMP;
+    netif->flags |= NETIF_FLAG_IGMP;
 #endif
 
 #if 0
-	sys_sem_new(&xemac->sem_rx_data_available, 0);
+    sys_sem_new(&xemac->sem_rx_data_available, 0);
 #endif
 	/* obtain config of this emac */
-	mac_config = (XEmacPs_Config *)xemacps_lookup_config((unsigned)(UINTPTR)netif->state);
+    mac_config = (XEmacPs_Config *)xemacps_lookup_config((unsigned)(UINTPTR)netif->state);
 
 #if EL1_NONSECURE
 	/* Request device to indicate that this library is using it */
-	if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
-		Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_0, 1, 0, 100, 1, 0, 0);
+    if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
+	    Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_0, 1, 0, 100, 1, 0, 0);
 	}
-	if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
-		Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_1, 1, 0, 100, 1, 0, 0);
+    if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
+	    Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_1, 1, 0, 100, 1, 0, 0);
 	}
 #endif
 
-	status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
-						mac_config->BaseAddress);
-	if (status != XST_SUCCESS) {
-		xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+    status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
+					    mac_config->BaseAddress);
+    if (status != XST_SUCCESS) {
+	    xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
 	}
 
 	/* initialize the mac */
-	init_emacps(xemacpsif, netif);
+    init_emacps(xemacpsif, netif);
 
-	dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-														XEMACPS_DMACR_OFFSET);
-	dmacrreg = dmacrreg | (0x00000010);
-	XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-											XEMACPS_DMACR_OFFSET, dmacrreg);
+    dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+													    XEMACPS_DMACR_OFFSET);
+    dmacrreg = dmacrreg | (0x00000010);
+    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+										    XEMACPS_DMACR_OFFSET, dmacrreg);
 
 #if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
 	/* Freertos tick is 10ms by default; set period to the same */
-	xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);
-	if (xemac->xTimer == NULL) {
-		xil_printf("In %s:Timer creation failed....\r\n", __func__);
+    xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);
+    if (xemac->xTimer == NULL) {
+	    xil_printf("In %s:Timer creation failed....\r\n", __func__);
 	} else {
-		if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
-			xil_printf("In %s:Timer start failed....\r\n", __func__);
+	    if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
+		    xil_printf("In %s:Timer start failed....\r\n", __func__);
 		}
 	}
 #endif
-	setup_isr(xemac);
-	init_dma(xemac);
-	start_emacps(xemacpsif);
+    setup_isr(xemac);
+    init_dma(xemac);
+    start_emacps(xemacpsif);
 
 	/* replace the state in netif (currently the emac baseaddress)
 	 * with the mac instance pointer.
 	 */
-	netif->state = (void *)xemac;
+    netif->state = (void *)xemac;
 
-	return ERR_OK;
+    return ERR_OK;
 }
 
 void HandleEmacPsError(struct xemac_s *xemac)
 {
-	xemacpsif_s   *xemacpsif;
-	s32_t status = XST_SUCCESS;
-	u32 dmacrreg;
-
-	SYS_ARCH_DECL_PROTECT(lev);
-	SYS_ARCH_PROTECT(lev);
-
-	xemacpsif = (xemacpsif_s *)(xemac->state);
-	free_txrx_pbufs(xemacpsif);
-	status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
-						mac_config->BaseAddress);
-	if (status != XST_SUCCESS) {
-		xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+    xemacpsif_s   *xemacpsif;
+    s32_t status = XST_SUCCESS;
+    u32 dmacrreg;
+
+    SYS_ARCH_DECL_PROTECT(lev);
+    SYS_ARCH_PROTECT(lev);
+
+    xemacpsif = (xemacpsif_s *)(xemac->state);
+    free_txrx_pbufs(xemacpsif);
+    status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
+					    mac_config->BaseAddress);
+    if (status != XST_SUCCESS) {
+	    xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
 	}
 	/* initialize the mac */
-	init_emacps_on_error(xemacpsif, NetIf);
-	dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-														XEMACPS_DMACR_OFFSET);
-	dmacrreg = dmacrreg | (0x01000000);
-	XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-											XEMACPS_DMACR_OFFSET, dmacrreg);
-	setup_isr(xemac);
-	init_dma(xemac);
-	start_emacps(xemacpsif);
-
-	SYS_ARCH_UNPROTECT(lev);
+    init_emacps_on_error(xemacpsif, NetIf);
+    dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+													    XEMACPS_DMACR_OFFSET);
+    dmacrreg = dmacrreg | (0x01000000);
+    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+										    XEMACPS_DMACR_OFFSET, dmacrreg);
+    setup_isr(xemac);
+    init_dma(xemac);
+    start_emacps(xemacpsif);
+
+    SYS_ARCH_UNPROTECT(lev);
 }
 
 void HandleTxErrors(struct xemac_s *xemac)
 {
-	xemacpsif_s   *xemacpsif;
-	u32 netctrlreg;
-
-	SYS_ARCH_DECL_PROTECT(lev);
-	SYS_ARCH_PROTECT(lev);
-	xemacpsif = (xemacpsif_s *)(xemac->state);
-	netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-												XEMACPS_NWCTRL_OFFSET);
+    xemacpsif_s   *xemacpsif;
+    u32 netctrlreg;
+
+    SYS_ARCH_DECL_PROTECT(lev);
+    SYS_ARCH_PROTECT(lev);
+    xemacpsif = (xemacpsif_s *)(xemac->state);
+    netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+											    XEMACPS_NWCTRL_OFFSET);
     netctrlreg = netctrlreg & (~XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-									XEMACPS_NWCTRL_OFFSET, netctrlreg);
-	free_onlytx_pbufs(xemacpsif);
-
-	clean_dma_txdescs(xemac);
-	netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-													XEMACPS_NWCTRL_OFFSET);
-	netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-										XEMACPS_NWCTRL_OFFSET, netctrlreg);
-	SYS_ARCH_UNPROTECT(lev);
+    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+								    XEMACPS_NWCTRL_OFFSET, netctrlreg);
+    free_onlytx_pbufs(xemacpsif);
+
+    clean_dma_txdescs(xemac);
+    netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+												    XEMACPS_NWCTRL_OFFSET);
+    netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK);
+    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+									    XEMACPS_NWCTRL_OFFSET, netctrlreg);
+    SYS_ARCH_UNPROTECT(lev);
 }
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
 static u8_t xemacpsif_ip6_addr_ismulticast(ip6_addr_t* ip_addr)
 {
-	if(ip6_addr_ismulticast_linklocal(ip_addr)||
+    if(ip6_addr_ismulticast_linklocal(ip_addr)||
            ip6_addr_ismulticast_iflocal(ip_addr)   ||
            ip6_addr_ismulticast_adminlocal(ip_addr)||
            ip6_addr_ismulticast_sitelocal(ip_addr) ||
            ip6_addr_ismulticast_orglocal(ip_addr)  ||
            ip6_addr_ismulticast_global(ip_addr)) {
 	/*Return TRUE if IPv6 is Multicast type*/
-	return TRUE;
+    return TRUE;
 	} else {
-	return FALSE;
+    return FALSE;
 	}
 }
 
 static void xemacpsif_mld6_mac_hash_update (struct netif *netif, u8_t *ip_addr,
-		u8_t action)
+	    u8_t action)
 {
-	u8_t multicast_mac_addr[6];
-	struct xemac_s *xemac = (struct xemac_s *) (netif->state);
-	xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
-	XEmacPs_BdRing *txring;
-	txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
-
-	multicast_mac_addr[0] = LL_IP6_MULTICAST_ADDR_0;
-	multicast_mac_addr[1] = LL_IP6_MULTICAST_ADDR_1;
-	multicast_mac_addr[2] = ip_addr[12];
-	multicast_mac_addr[3] = ip_addr[13];
-	multicast_mac_addr[4] = ip_addr[14];
-	multicast_mac_addr[5] = ip_addr[15];
+    u8_t multicast_mac_addr[6];
+    struct xemac_s *xemac = (struct xemac_s *) (netif->state);
+    xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
+    XEmacPs_BdRing *txring;
+    txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+
+    multicast_mac_addr[0] = LL_IP6_MULTICAST_ADDR_0;
+    multicast_mac_addr[1] = LL_IP6_MULTICAST_ADDR_1;
+    multicast_mac_addr[2] = ip_addr[12];
+    multicast_mac_addr[3] = ip_addr[13];
+    multicast_mac_addr[4] = ip_addr[14];
+    multicast_mac_addr[5] = ip_addr[15];
 
 	/* Wait till all sent packets are acknowledged from HW */
-	while(txring->HwCnt);
+    while(txring->HwCnt);
 
-	SYS_ARCH_DECL_PROTECT(lev);
+    SYS_ARCH_DECL_PROTECT(lev);
 
-	SYS_ARCH_PROTECT(lev);
+    SYS_ARCH_PROTECT(lev);
 
 	/* Stop Ethernet */
-	XEmacPs_Stop(&xemacpsif->emacps);
+    XEmacPs_Stop(&xemacpsif->emacps);
 
-	if (action == NETIF_ADD_MAC_FILTER) {
+    if (action == NETIF_ADD_MAC_FILTER) {
 		/* Set Mulitcast mac address in hash table */
-		XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+	    XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
 
 	} else if (action == NETIF_DEL_MAC_FILTER) {
 		/* Remove Mulitcast mac address in hash table */
-		XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+	    XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
 	}
 
 	/* Reset DMA */
-	reset_dma(xemac);
+    reset_dma(xemac);
 
 	/* Start Ethernet */
-	XEmacPs_Start(&xemacpsif->emacps);
+    XEmacPs_Start(&xemacpsif->emacps);
 
-	SYS_ARCH_UNPROTECT(lev);
+    SYS_ARCH_UNPROTECT(lev);
 }
 
 static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif, ip_addr_t *group,
-		u8_t action)
+	    u8_t action)
 {
-	u8_t temp_mask;
-	unsigned int i;
-	u8_t * ip_addr = (u8_t *) group;
+    u8_t temp_mask;
+    unsigned int i;
+    u8_t * ip_addr = (u8_t *) group;
 
-	if(!(xemacpsif_ip6_addr_ismulticast((ip6_addr_t*) ip_addr))) {
-		LWIP_DEBUGF(NETIF_DEBUG,
+    if(!(xemacpsif_ip6_addr_ismulticast((ip6_addr_t*) ip_addr))) {
+	    LWIP_DEBUGF(NETIF_DEBUG,
                                 ("%s: The requested MAC address is not a multicast address.\r\n", __func__));								 LWIP_DEBUGF(NETIF_DEBUG,
 		                ("Multicast address add operation failure !!\r\n"));
                         return ERR_ARG;
 	}
-	if (action == NETIF_ADD_MAC_FILTER) {
-		for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-			temp_mask = (0x01) << i;
-			if ((xemacps_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
-				continue;
+    if (action == NETIF_ADD_MAC_FILTER) {
+	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+		    temp_mask = (0x01) << i;
+		    if ((xemacps_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
+			    continue;
 			}
-			xemacps_mld6_mcast_entry_mask |= temp_mask;
+		    xemacps_mld6_mcast_entry_mask |= temp_mask;
 
 			/* Update mac address in hash table */
-			xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+		    xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
 
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: Multicast MAC address successfully added.\r\n", __func__));
 
-			return ERR_OK;
+		    return ERR_OK;
 		}
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("%s: No multicast address registers left.\r\n", __func__));
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("Multicast MAC address add operation failure !!\r\n"));
-		return ERR_MEM;
+	    return ERR_MEM;
 	} else if (action == NETIF_DEL_MAC_FILTER) {
-		for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-			temp_mask = (0x01) << i;
-			if ((xemacps_mld6_mcast_entry_mask & temp_mask) != temp_mask) {
-				continue;
+	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+		    temp_mask = (0x01) << i;
+		    if ((xemacps_mld6_mcast_entry_mask & temp_mask) != temp_mask) {
+			    continue;
 			}
-			xemacps_mld6_mcast_entry_mask &= (~temp_mask);
+		    xemacps_mld6_mcast_entry_mask &= (~temp_mask);
 
 			/* Update mac address in hash table */
-			xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+		    xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
 
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: Multicast MAC address successfully removed.\r\n", __func__));
 
-			return ERR_OK;
+		    return ERR_OK;
 		}
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("%s: No multicast address registers present with\r\n", __func__));
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("the requested Multicast MAC address.\r\n"));
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("Multicast MAC address removal failure!!.\r\n"));
-		return ERR_MEM;
+	    return ERR_MEM;
 	}
-	return ERR_ARG;
+    return ERR_ARG;
 }
 #endif
 
 #if LWIP_IGMP
 static void xemacpsif_mac_hash_update (struct netif *netif, u8_t *ip_addr,
-		u8_t action)
+	    u8_t action)
 {
-	u8_t multicast_mac_addr[6];
-	struct xemac_s *xemac = (struct xemac_s *) (netif->state);
-	xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
-	XEmacPs_BdRing *txring;
-	txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
-
-	multicast_mac_addr[0] = 0x01;
-	multicast_mac_addr[1] = 0x00;
-	multicast_mac_addr[2] = 0x5E;
-	multicast_mac_addr[3] = ip_addr[1] & 0x7F;
-	multicast_mac_addr[4] = ip_addr[2];
-	multicast_mac_addr[5] = ip_addr[3];
+    u8_t multicast_mac_addr[6];
+    struct xemac_s *xemac = (struct xemac_s *) (netif->state);
+    xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
+    XEmacPs_BdRing *txring;
+    txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+
+    multicast_mac_addr[0] = 0x01;
+    multicast_mac_addr[1] = 0x00;
+    multicast_mac_addr[2] = 0x5E;
+    multicast_mac_addr[3] = ip_addr[1] & 0x7F;
+    multicast_mac_addr[4] = ip_addr[2];
+    multicast_mac_addr[5] = ip_addr[3];
 
 	/* Wait till all sent packets are acknowledged from HW */
-	while(txring->HwCnt);
+    while(txring->HwCnt);
 
-	SYS_ARCH_DECL_PROTECT(lev);
+    SYS_ARCH_DECL_PROTECT(lev);
 
-	SYS_ARCH_PROTECT(lev);
+    SYS_ARCH_PROTECT(lev);
 
 	/* Stop Ethernet */
-	XEmacPs_Stop(&xemacpsif->emacps);
+    XEmacPs_Stop(&xemacpsif->emacps);
 
-	if (action == IGMP_ADD_MAC_FILTER) {
+    if (action == IGMP_ADD_MAC_FILTER) {
 		/* Set Mulitcast mac address in hash table */
-		XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+	    XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
 
 	} else if (action == IGMP_DEL_MAC_FILTER) {
 		/* Remove Mulitcast mac address in hash table */
-		XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+	    XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
 	}
 
 	/* Reset DMA */
-	reset_dma(xemac);
+    reset_dma(xemac);
 
 	/* Start Ethernet */
-	XEmacPs_Start(&xemacpsif->emacps);
+    XEmacPs_Start(&xemacpsif->emacps);
 
-	SYS_ARCH_UNPROTECT(lev);
+    SYS_ARCH_UNPROTECT(lev);
 }
 
 static err_t xemacpsif_mac_filter_update (struct netif *netif, ip_addr_t *group,
-		u8_t action)
+	    u8_t action)
 {
-	u8_t temp_mask;
-	unsigned int i;
-	u8_t * ip_addr = (u8_t *) group;
+    u8_t temp_mask;
+    unsigned int i;
+    u8_t * ip_addr = (u8_t *) group;
 
-	if ((ip_addr[0] < 224) && (ip_addr[0] > 239)) {
-		LWIP_DEBUGF(NETIF_DEBUG,
+    if ((ip_addr[0] < 224) && (ip_addr[0] > 239)) {
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("%s: The requested MAC address is not a multicast address.\r\n", __func__));
-		LWIP_DEBUGF(NETIF_DEBUG,
+	    LWIP_DEBUGF(NETIF_DEBUG,
 				("Multicast address add operation failure !!\r\n"));
 
-		return ERR_ARG;
+	    return ERR_ARG;
 	}
 
-	if (action == IGMP_ADD_MAC_FILTER) {
+    if (action == IGMP_ADD_MAC_FILTER) {
 
-		for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-			temp_mask = (0x01) << i;
-			if ((xemacps_mcast_entry_mask & temp_mask) == temp_mask) {
-				continue;
+	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+		    temp_mask = (0x01) << i;
+		    if ((xemacps_mcast_entry_mask & temp_mask) == temp_mask) {
+			    continue;
 			}
-			xemacps_mcast_entry_mask |= temp_mask;
+		    xemacps_mcast_entry_mask |= temp_mask;
 
 			/* Update mac address in hash table */
-			xemacpsif_mac_hash_update(netif, ip_addr, action);
+		    xemacpsif_mac_hash_update(netif, ip_addr, action);
 
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: Multicast MAC address successfully added.\r\n", __func__));
 
-			return ERR_OK;
+		    return ERR_OK;
 		}
-		if (i == XEMACPS_MAX_MAC_ADDR) {
-			LWIP_DEBUGF(NETIF_DEBUG,
+	    if (i == XEMACPS_MAX_MAC_ADDR) {
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: No multicast address registers left.\r\n", __func__));
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("Multicast MAC address add operation failure !!\r\n"));
 
-			return ERR_MEM;
+		    return ERR_MEM;
 		}
 	} else if (action == IGMP_DEL_MAC_FILTER) {
-		for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-			temp_mask = (0x01) << i;
-			if ((xemacps_mcast_entry_mask & temp_mask) != temp_mask) {
-				continue;
+	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+		    temp_mask = (0x01) << i;
+		    if ((xemacps_mcast_entry_mask & temp_mask) != temp_mask) {
+			    continue;
 			}
-			xemacps_mcast_entry_mask &= (~temp_mask);
+		    xemacps_mcast_entry_mask &= (~temp_mask);
 
 			/* Update mac address in hash table */
-			xemacpsif_mac_hash_update(netif, ip_addr, action);
+		    xemacpsif_mac_hash_update(netif, ip_addr, action);
 
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: Multicast MAC address successfully removed.\r\n", __func__));
 
-			return ERR_OK;
+		    return ERR_OK;
 		}
-		if (i == XEMACPS_MAX_MAC_ADDR) {
-			LWIP_DEBUGF(NETIF_DEBUG,
+	    if (i == XEMACPS_MAX_MAC_ADDR) {
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("%s: No multicast address registers present with\r\n", __func__));
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("the requested Multicast MAC address.\r\n"));
-			LWIP_DEBUGF(NETIF_DEBUG,
+		    LWIP_DEBUGF(NETIF_DEBUG,
 					("Multicast MAC address removal failure!!.\r\n"));
 
-			return ERR_MEM;
+		    return ERR_MEM;
 		}
 	}
-	return ERR_OK;
+    return ERR_OK;
 }
 #endif
 
@@ -713,30 +713,30 @@ err_t xemacpsif_init(struct netif *netif)
 {
 #if LWIP_SNMP
 	/* ifType ethernetCsmacd(6) @see RFC1213 */
-	netif->link_type = 6;
+    netif->link_type = 6;
 	/* your link speed here */
-	netif->link_speed = ;
-	netif->ts = 0;
-	netif->ifinoctets = 0;
-	netif->ifinucastpkts = 0;
-	netif->ifinnucastpkts = 0;
-	netif->ifindiscards = 0;
-	netif->ifoutoctets = 0;
-	netif->ifoutucastpkts = 0;
-	netif->ifoutnucastpkts = 0;
-	netif->ifoutdiscards = 0;
+    netif->link_speed = ;
+    netif->ts = 0;
+    netif->ifinoctets = 0;
+    netif->ifinucastpkts = 0;
+    netif->ifinnucastpkts = 0;
+    netif->ifindiscards = 0;
+    netif->ifoutoctets = 0;
+    netif->ifoutucastpkts = 0;
+    netif->ifoutnucastpkts = 0;
+    netif->ifoutdiscards = 0;
 #endif
 
-	netif->name[0] = IFNAME0;
-	netif->name[1] = IFNAME1;
-	netif->output = xemacpsif_output;
-	netif->linkoutput = low_level_output;
+    netif->name[0] = IFNAME0;
+    netif->name[1] = IFNAME1;
+    netif->output = xemacpsif_output;
+    netif->linkoutput = low_level_output;
 #if LWIP_IPV6
-	netif->output_ip6 = ethip6_output;
+    netif->output_ip6 = ethip6_output;
 #endif
 
-	low_level_init(netif);
-	return ERR_OK;
+    low_level_init(netif);
+    return ERR_OK;
 }
 
 /*
@@ -752,8 +752,8 @@ err_t xemacpsif_init(struct netif *netif)
 
 void xemacpsif_resetrx_on_no_rxdata(struct netif *netif)
 {
-	struct xemac_s *xemac = (struct xemac_s *)(netif->state);
-	xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+    struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+    xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
 
-	resetrx_on_no_rxdata(xemacpsif);
+    resetrx_on_no_rxdata(xemacpsif);
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c

@@ -32,7 +32,7 @@
 #include "lwipopts.h"
 
 #if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
-	XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+    XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
 #define PCM_PMA_CORE_PRESENT
 #else
 #undef PCM_PMA_CORE_PRESENT
@@ -51,44 +51,44 @@ extern long xInsideISR;
 
 XEmacPs_Config *xemacps_lookup_config(unsigned mac_base)
 {
-	XEmacPs_Config *cfgptr = NULL;
-	s32_t i;
+    XEmacPs_Config *cfgptr = NULL;
+    s32_t i;
 
-	for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
-		if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
-			cfgptr = &XEmacPs_ConfigTable[i];
-			break;
+    for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
+	    if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
+		    cfgptr = &XEmacPs_ConfigTable[i];
+		    break;
 		}
 	}
 
-	return (cfgptr);
+    return (cfgptr);
 }
 
 void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
 {
-	XEmacPs *xemacpsp;
-	s32_t status = XST_SUCCESS;
-	u32_t i;
-	u32_t phyfoundforemac0 = FALSE;
-	u32_t phyfoundforemac1 = FALSE;
+    XEmacPs *xemacpsp;
+    s32_t status = XST_SUCCESS;
+    u32_t i;
+    u32_t phyfoundforemac0 = FALSE;
+    u32_t phyfoundforemac1 = FALSE;
 
-	xemacpsp = &xemacps->emacps;
+    xemacpsp = &xemacps->emacps;
 
 #ifdef ZYNQMP_USE_JUMBO
-	XEmacPs_SetOptions(xemacpsp, XEMACPS_JUMBO_ENABLE_OPTION);
+    XEmacPs_SetOptions(xemacpsp, XEMACPS_JUMBO_ENABLE_OPTION);
 #endif
 
 #ifdef LWIP_IGMP
-	XEmacPs_SetOptions(xemacpsp, XEMACPS_MULTICAST_OPTION);
+    XEmacPs_SetOptions(xemacpsp, XEMACPS_MULTICAST_OPTION);
 #endif
 
 	/* set mac address */
-	status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
-	if (status != XST_SUCCESS) {
-		xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+    status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
+    if (status != XST_SUCCESS) {
+	    xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
 	}
 
-	XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
+    XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
 
 /*  Please refer to file header comments for the file xemacpsif_physpeed.c
  *  to know more about the PHY programming sequence.
@@ -102,92 +102,92 @@ void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
  */
 #ifdef PCM_PMA_CORE_PRESENT
 #ifdef  XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT
-	link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_1000BASEX_PHYADDR);
+    link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_1000BASEX_PHYADDR);
 #elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
-	link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_SGMII_PHYADDR);
+    link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_SGMII_PHYADDR);
 #endif
 #else
-	detect_phy(xemacpsp);
-	for (i = 31; i > 0; i--) {
-		if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-			if (phymapemac0[i] == TRUE) {
-				link_speed = phy_setup_emacps(xemacpsp, i);
-				phyfoundforemac0 = TRUE;
-				phyaddrforemac = i;
+    detect_phy(xemacpsp);
+    for (i = 31; i > 0; i--) {
+	    if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+		    if (phymapemac0[i] == TRUE) {
+			    link_speed = phy_setup_emacps(xemacpsp, i);
+			    phyfoundforemac0 = TRUE;
+			    phyaddrforemac = i;
 			}
 		} else {
-			if (phymapemac1[i] == TRUE) {
-				link_speed = phy_setup_emacps(xemacpsp, i);
-				phyfoundforemac1 = TRUE;
-				phyaddrforemac = i;
+		    if (phymapemac1[i] == TRUE) {
+			    link_speed = phy_setup_emacps(xemacpsp, i);
+			    phyfoundforemac1 = TRUE;
+			    phyaddrforemac = i;
 			}
 		}
 	}
 	/* If no PHY was detected, use broadcast PHY address of 0 */
-	if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-		if (phyfoundforemac0 == FALSE)
-			link_speed = phy_setup_emacps(xemacpsp, 0);
+    if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+	    if (phyfoundforemac0 == FALSE)
+		    link_speed = phy_setup_emacps(xemacpsp, 0);
 	} else {
-		if (phyfoundforemac1 == FALSE)
-			link_speed = phy_setup_emacps(xemacpsp, 0);
+	    if (phyfoundforemac1 == FALSE)
+		    link_speed = phy_setup_emacps(xemacpsp, 0);
 	}
 #endif
 
-	if (link_speed == XST_FAILURE) {
-		eth_link_status = ETH_LINK_DOWN;
-		xil_printf("Phy setup failure %s \n\r",__func__);
-		return;
+    if (link_speed == XST_FAILURE) {
+	    eth_link_status = ETH_LINK_DOWN;
+	    xil_printf("Phy setup failure %s \n\r",__func__);
+	    return;
 	} else {
-		eth_link_status = ETH_LINK_UP;
+	    eth_link_status = ETH_LINK_UP;
 	}
 
-	XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
+    XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
 	/* Setting the operating speed of the MAC needs a delay. */
 	{
-		volatile s32_t wait;
-		for (wait=0; wait < 20000; wait++);
+	    volatile s32_t wait;
+	    for (wait=0; wait < 20000; wait++);
 	}
 }
 
 void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
 {
-	XEmacPs *xemacpsp;
-	s32_t status = XST_SUCCESS;
+    XEmacPs *xemacpsp;
+    s32_t status = XST_SUCCESS;
 
-	xemacpsp = &xemacps->emacps;
+    xemacpsp = &xemacps->emacps;
 
 	/* set mac address */
-	status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
-	if (status != XST_SUCCESS) {
-		xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+    status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
+    if (status != XST_SUCCESS) {
+	    xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
 	}
 
-	XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
+    XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
 
 	/* Setting the operating speed of the MAC needs a delay. */
 	{
-		volatile s32_t wait;
-		for (wait=0; wait < 20000; wait++);
+	    volatile s32_t wait;
+	    for (wait=0; wait < 20000; wait++);
 	}
 }
 
 void setup_isr (struct xemac_s *xemac)
 {
-	xemacpsif_s   *xemacpsif;
+    xemacpsif_s   *xemacpsif;
 
-	xemacpsif = (xemacpsif_s *)(xemac->state);
+    xemacpsif = (xemacpsif_s *)(xemac->state);
 	/*
 	 * Setup callbacks
 	 */
-	XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND,
+    XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND,
 				     (void *) emacps_send_handler,
 				     (void *) xemac);
 
-	XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV,
+    XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV,
 				    (void *) emacps_recv_handler,
 				    (void *) xemac);
 
-	XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR,
+    XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR,
 				    (void *) emacps_error_handler,
 				    (void *) xemac);
 }
@@ -195,82 +195,82 @@ void setup_isr (struct xemac_s *xemac)
 void start_emacps (xemacpsif_s *xemacps)
 {
 	/* start the temac */
-	XEmacPs_Start(&xemacps->emacps);
+    XEmacPs_Start(&xemacps->emacps);
 }
 
 void restart_emacps_transmitter (xemacpsif_s *xemacps) {
-	u32_t Reg;
-	Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
-					XEMACPS_NWCTRL_OFFSET);
-	Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
-										XEMACPS_NWCTRL_OFFSET, Reg);
+    u32_t Reg;
+    Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
+				    XEMACPS_NWCTRL_OFFSET);
+    Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK);
+    XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
+									    XEMACPS_NWCTRL_OFFSET, Reg);
 
-	Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
-						XEMACPS_NWCTRL_OFFSET);
-	Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK);
-	XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
-										XEMACPS_NWCTRL_OFFSET, Reg);
+    Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
+					    XEMACPS_NWCTRL_OFFSET);
+    Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK);
+    XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
+									    XEMACPS_NWCTRL_OFFSET, Reg);
 }
 
 void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
 {
-	struct xemac_s *xemac;
-	xemacpsif_s   *xemacpsif;
-	XEmacPs_BdRing *rxring;
-	XEmacPs_BdRing *txring;
+    struct xemac_s *xemac;
+    xemacpsif_s   *xemacpsif;
+    XEmacPs_BdRing *rxring;
+    XEmacPs_BdRing *txring;
 #ifdef OS_IS_FREERTOS
-	xInsideISR++;
+    xInsideISR++;
 #endif
 
-	xemac = (struct xemac_s *)(arg);
-	xemacpsif = (xemacpsif_s *)(xemac->state);
-	rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
-	txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
+    xemac = (struct xemac_s *)(arg);
+    xemacpsif = (xemacpsif_s *)(xemac->state);
+    rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+    txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
 
-	if (ErrorWord != 0) {
-		switch (Direction) {
-			case XEMACPS_RECV:
-			if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
-				HandleEmacPsError(xemac);
+    if (ErrorWord != 0) {
+	    switch (Direction) {
+		    case XEMACPS_RECV:
+		    if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
+			    HandleEmacPsError(xemac);
 			}
-			if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
-				emacps_recv_handler(arg);
-				setup_rx_bds(xemacpsif, rxring);
+		    if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
+			    emacps_recv_handler(arg);
+			    setup_rx_bds(xemacpsif, rxring);
 			}
-			if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
-				emacps_recv_handler(arg);
-				setup_rx_bds(xemacpsif, rxring);
+		    if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
+			    emacps_recv_handler(arg);
+			    setup_rx_bds(xemacpsif, rxring);
 			}
-			break;
-			case XEMACPS_SEND:
-			if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
-				HandleEmacPsError(xemac);
+		    break;
+		    case XEMACPS_SEND:
+		    if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
+			    HandleEmacPsError(xemac);
 			}
-			if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
-				HandleTxErrors(xemac);
+		    if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
+			    HandleTxErrors(xemac);
 			}
-			if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
-				HandleTxErrors(xemac);
+		    if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
+			    HandleTxErrors(xemac);
 			}
-			if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
-				HandleTxErrors(xemac);
+		    if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
+			    HandleTxErrors(xemac);
 			}
-			if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
-				LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
+		    if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
+			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
 				// process_sent_bds(xemacpsif, txring);
 			}
-			break;
+		    break;
 		}
 	}
 #ifdef OS_IS_FREERTOS
-	xInsideISR--;
+    xInsideISR--;
 #endif
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c

@@ -33,61 +33,61 @@
 #include "netif/xpqueue.h"
 #include "xil_printf.h"
 
-#define NUM_QUEUES	2
+#define NUM_QUEUES    2
 
 pq_queue_t pq_queue[NUM_QUEUES];
 
 pq_queue_t *
 pq_create_queue()
 {
-	static int i;
-	pq_queue_t *q = NULL;
+    static int i;
+    pq_queue_t *q = NULL;
 
-	if (i >= NUM_QUEUES) {
-		xil_printf("ERR: Max Queues allocated\n\r");
-		return q;
+    if (i >= NUM_QUEUES) {
+	    xil_printf("ERR: Max Queues allocated\n\r");
+	    return q;
 	}
 
-	q = &pq_queue[i++];
+    q = &pq_queue[i++];
 
-	if (!q)
-		return q;
+    if (!q)
+	    return q;
 
-	q->head = q->tail = q->len = 0;
+    q->head = q->tail = q->len = 0;
 
-	return q;
+    return q;
 }
 
 int
 pq_enqueue(pq_queue_t *q, void *p)
 {
-	if (q->len == PQ_QUEUE_SIZE)
-		return -1;
+    if (q->len == PQ_QUEUE_SIZE)
+	    return -1;
 
-	q->data[q->head] = p;
-	q->head = (q->head + 1)%PQ_QUEUE_SIZE;
-	q->len++;
+    q->data[q->head] = p;
+    q->head = (q->head + 1)%PQ_QUEUE_SIZE;
+    q->len++;
 
-	return 0;
+    return 0;
 }
 
 void*
 pq_dequeue(pq_queue_t *q)
 {
-	int ptail;
+    int ptail;
 
-	if (q->len == 0)
-		return NULL;
+    if (q->len == 0)
+	    return NULL;
 
-	ptail = q->tail;
-	q->tail = (q->tail + 1)%PQ_QUEUE_SIZE;
-	q->len--;
+    ptail = q->tail;
+    q->tail = (q->tail + 1)%PQ_QUEUE_SIZE;
+    q->len--;
 
-	return q->data[ptail];
+    return q->data[ptail];
 }
 
 int
 pq_qlength(pq_queue_t *q)
 {
-	return q->len;
+    return q->len;
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c

@@ -3,12 +3,12 @@
 
 struct xtopology_t xtopology[] = {
 	{
-		0xFF0E0000,
-		xemac_type_emacps,
-		0x0,
-		0x0,
-		0xF8F00100,
-		XPAR_XEMACPS_3_INTR,
+	    0xFF0E0000,
+	    xemac_type_emacps,
+	    0x0,
+	    0x0,
+	    0xF8F00100,
+	    XPAR_XEMACPS_3_INTR,
 	},
 };
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h

@@ -20,7 +20,7 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 05/29/14 First release
+* 5.00     pkp  	 05/29/14 First release
 * 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
 *                         ARM processors
 * 7.20  har      01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
@@ -54,15 +54,15 @@ extern "C" {
 *           from the specified address and returning the 8 bit Value read from
 *            that address.
 *
-* @param	Addr: contains the address to perform the input operation
+* @param    Addr: contains the address to perform the input operation
 *
-* @return	The 8 bit Value read from the specified input address.
+* @return    The 8 bit Value read from the specified input address.
 
 *
 ******************************************************************************/
 static INLINE u8 Xil_In8(UINTPTR Addr)
 {
-	return *(volatile u8 *) Addr;
+    return *(volatile u8 *) Addr;
 }
 
 /*****************************************************************************/
@@ -72,14 +72,14 @@ static INLINE u8 Xil_In8(UINTPTR Addr)
 *           the specified address and returning the 16 bit Value read from that
 *           address.
 *
-* @param	Addr: contains the address to perform the input operation
+* @param    Addr: contains the address to perform the input operation
 *
-* @return	The 16 bit Value read from the specified input address.
+* @return    The 16 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u16 Xil_In16(UINTPTR Addr)
 {
-	return *(volatile u16 *) Addr;
+    return *(volatile u16 *) Addr;
 }
 
 /*****************************************************************************/
@@ -89,14 +89,14 @@ static INLINE u16 Xil_In16(UINTPTR Addr)
 *           reading from the specified address and returning the 32 bit Value
 *           read  from that address.
 *
-* @param	Addr: contains the address to perform the input operation
+* @param    Addr: contains the address to perform the input operation
 *
-* @return	The 32 bit Value read from the specified input address.
+* @return    The 32 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u32 Xil_In32(UINTPTR Addr)
 {
-	return *(volatile u32 *) Addr;
+    return *(volatile u32 *) Addr;
 }
 
 /*****************************************************************************/
@@ -106,14 +106,14 @@ static INLINE u32 Xil_In32(UINTPTR Addr)
 *            64 bit Value read  from that address.
 *
 *
-* @param	Addr: contains the address to perform the input operation
+* @param    Addr: contains the address to perform the input operation
 *
-* @return	The 64 bit Value read from the specified input address.
+* @return    The 64 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u64 Xil_In64(UINTPTR Addr)
 {
-	return *(volatile u64 *) Addr;
+    return *(volatile u64 *) Addr;
 }
 
 /*****************************************************************************/
@@ -122,16 +122,16 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
 * @brief    Performs an output operation for an memory location by
 *           writing the 8 bit Value to the the specified address.
 *
-* @param	Addr: contains the address to perform the output operation
-* @param	Value: contains the 8 bit Value to be written at the specified
+* @param    Addr: contains the address to perform the output operation
+* @param    Value: contains the 8 bit Value to be written at the specified
 *           address.
 *
-* @return	None.
+* @return    None.
 *
 ******************************************************************************/
 static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 {
-	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+    volatile u8 *LocalAddr = (volatile u8 *)Addr;
 	*LocalAddr = Value;
 }
 
@@ -141,15 +141,15 @@ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 * @brief    Performs an output operation for a memory location by writing the
 *            16 bit Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains the Value to be written at the specified address.
+* @param    Addr contains the address to perform the output operation
+* @param    Value contains the Value to be written at the specified address.
 *
-* @return	None.
+* @return    None.
 *
 ******************************************************************************/
 static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 {
-	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+    volatile u16 *LocalAddr = (volatile u16 *)Addr;
 	*LocalAddr = Value;
 }
 
@@ -159,20 +159,20 @@ static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 * @brief    Performs an output operation for a memory location by writing the
 *           32 bit Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains the 32 bit Value to be written at the specified
+* @param    Addr contains the address to perform the output operation
+* @param    Value contains the 32 bit Value to be written at the specified
 *           address.
 *
-* @return	None.
+* @return    None.
 *
 ******************************************************************************/
 static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 {
 #ifndef ENABLE_SAFETY
-	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+    volatile u32 *LocalAddr = (volatile u32 *)Addr;
 	*LocalAddr = Value;
 #else
-	XStl_RegUpdate(Addr, Value);
+    XStl_RegUpdate(Addr, Value);
 #endif
 }
 
@@ -182,15 +182,15 @@ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 * @brief    Performs an output operation for a memory location by writing the
 *           64 bit Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
-* @param	Value contains 64 bit Value to be written at the specified address.
+* @param    Addr contains the address to perform the output operation
+* @param    Value contains 64 bit Value to be written at the specified address.
 *
-* @return	None.
+* @return    None.
 *
 ******************************************************************************/
 static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
 {
-	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+    volatile u64 *LocalAddr = (volatile u64 *)Addr;
 	*LocalAddr = Value;
 }
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h

@@ -12,15 +12,15 @@ extern "C" {
 /************************** Constant Definitions *****************************/
 
 #ifndef TRUE
-#  define TRUE		1U
+#  define TRUE	    1U
 #endif
 
 #ifndef FALSE
-#  define FALSE		0U
+#  define FALSE	    0U
 #endif
 
 #ifndef NULL
-#define NULL		0U
+#define NULL	    0U
 #endif
 
 #define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
@@ -54,7 +54,7 @@ typedef long LONG;
 typedef unsigned long ULONG;
 #endif
 
-#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_HI_MASK    0xFFFFFFFF00000000U
 #define ULONG64_LO_MASK	~ULONG64_HI_MASK
 
 /** @{ */
@@ -73,15 +73,15 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 /************************** Constant Definitions *****************************/
 
 #ifndef TRUE
-#define TRUE		1U
+#define TRUE	    1U
 #endif
 
 #ifndef FALSE
-#define FALSE		0U
+#define FALSE	    0U
 #endif
 
 #ifndef NULL
-#define NULL		0U
+#define NULL	    0U
 #endif
 
 #ifdef __cplusplus

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h

@@ -38,16 +38,16 @@
 
 /* Platform specific definitions */
 #define PLATFORM_ZYNQMP
- 
+
 /* Definitions for debug logic configuration in lockstep mode */
 #define LOCKSTEP_MODE_DEBUG 0U
- 
+
 /* Definitions for sleep timer configuration */
 #define XSLEEP_TIMER_IS_DEFAULT_TIMER
- 
+
 /* Definitions for processor access to RPU/IOU slcr address space*/
 #define PROCESSOR_ACCESS_VALUE 255
- 
+
 /******************************************************************/
 /* Definitions for driver AVBUF */
 #define XPAR_XAVBUF_NUM_INSTANCES 1
@@ -750,11 +750,11 @@
 #define  XPAR_PSU_IPI_1_INT_ID  65U
 
 /* Canonical definitions for peripheral psu_ipi_1 */
-#define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSU_IPI_1_DEVICE_ID
-#define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSU_IPI_1_S_AXI_BASEADDR
-#define  XPAR_XIPIPSU_0_BIT_MASK	XPAR_PSU_IPI_1_BIT_MASK
-#define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSU_IPI_1_BUFFER_INDEX
-#define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSU_IPI_1_INT_ID
+#define  XPAR_XIPIPSU_0_DEVICE_ID    XPAR_PSU_IPI_1_DEVICE_ID
+#define  XPAR_XIPIPSU_0_BASE_ADDRESS    XPAR_PSU_IPI_1_S_AXI_BASEADDR
+#define  XPAR_XIPIPSU_0_BIT_MASK    XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPSU_0_BUFFER_INDEX    XPAR_PSU_IPI_1_BUFFER_INDEX
+#define  XPAR_XIPIPSU_0_INT_ID    XPAR_PSU_IPI_1_INT_ID
 
 #define  XPAR_XIPIPSU_NUM_TARGETS  7U
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h

@@ -20,9 +20,9 @@
 *
 * Ver   Who     Date     Changes
 * ----- ------- -------- ---------------------------------------------------
-* 5.00  pkp  	02/29/14 Initial version
+* 5.00  pkp      02/29/14 Initial version
 * 6.0   mus     08/18/16 Defined ARMR5 flag
-* 7.2	pm	03/25/20 Add wakeup Interrupt Id for usbpsu controller
+* 7.2    pm    03/25/20 Add wakeup Interrupt Id for usbpsu controller
 * </pre>
 *
 ******************************************************************************/
@@ -48,105 +48,105 @@ extern "C" {
  */
 
 /* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR		0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+#define XPAR_DDR_MEM_BASEADDR	    0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR	    0x3FFFFFFFU
 
 /* Canonical definitions for Interrupts  */
-#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
-#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
-#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
-#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
-#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR		XPS_CSU_WDT_INT_ID
-#define XPAR_XWDTPS_1_INTR		XPS_LPD_SWDT_INT_ID
-#define XPAR_XWDTPS_2_INTR		XPS_FPD_SWDT_INT_ID
-#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
-#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
-#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
-#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
-#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
-#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
-#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
-#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
-#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
-#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
-#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
-#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
-#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
-#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
-#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
-#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
-#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
-#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
-#define XPAR_PSU_ADMA_0_INTR 		XPS_ADMA_CH0_INT_ID
-#define XPAR_PSU_ADMA_1_INTR 		XPS_ADMA_CH1_INT_ID
-#define XPAR_PSU_ADMA_2_INTR		XPS_ADMA_CH2_INT_ID
-#define XPAR_PSU_ADMA_3_INTR 		XPS_ADMA_CH3_INT_ID
-#define XPAR_PSU_ADMA_4_INTR		XPS_ADMA_CH4_INT_ID
-#define XPAR_PSU_ADMA_5_INTR 		XPS_ADMA_CH5_INT_ID
-#define XPAR_PSU_ADMA_6_INTR 		XPS_ADMA_CH6_INT_ID
-#define XPAR_PSU_ADMA_7_INTR 		XPS_ADMA_CH7_INT_ID
-#define XPAR_PSU_CSUDMA_INTR 		XPS_CSU_DMA_INT_ID
-#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
-#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
-#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
-#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
-#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
-#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
-#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
-#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
-#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
-#define XPAR_PSU_GDMA_0_INTR		XPS_ZDMA_CH0_INT_ID
-#define XPAR_PSU_GDMA_1_INTR		XPS_ZDMA_CH1_INT_ID
-#define XPAR_PSU_GDMA_2_INTR 		XPS_ZDMA_CH2_INT_ID
-#define XPAR_PSU_GDMA_3_INTR 		XPS_ZDMA_CH3_INT_ID
-#define XPAR_PSU_GDMA_4_INTR		XPS_ZDMA_CH4_INT_ID
-#define XPAR_PSU_GDMA_5_INTR 		XPS_ZDMA_CH5_INT_ID
-#define XPAR_PSU_GDMA_6_INTR 		XPS_ZDMA_CH6_INT_ID
-#define XPAR_PSU_GDMA_7_INTR 		XPS_ZDMA_CH7_INT_ID
-#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
-#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
-#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
-#define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
-#define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
-#define XPAR_XUSBPS_0_WAKE_INTR		XPS_USB3_0_WAKE_INT_ID
-#define XPAR_XUSBPS_1_WAKE_INTR		XPS_USB3_1_WAKE_INT_ID
-#define	XPAR_XRTCPSU_ALARM_INTR 	XPS_RTC_ALARM_INT_ID
-#define	XPAR_XRTCPSU_SECONDS_INTR	XPS_RTC_SEC_INT_ID
-#define XPAR_XAPMPS_0_INTR		XPS_APM0_INT_ID
-#define XPAR_XAPMPS_1_INTR		XPS_APM1_INT_ID
-#define XPAR_XAPMPS_2_INTR		XPS_APM2_INT_ID
-#define XPAR_XAPMPS_5_INTR		XPS_APM5_INT_ID
-#define XPAR_XSYSMONPSU_INTR		XPS_AMS_INT_ID
+#define XPAR_XUARTPS_0_INTR	    XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR	    XPS_UART1_INT_ID
+#define XPAR_XIICPS_0_INTR	    XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR	    XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR	    XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR	    XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR	    XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR	    XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR	    XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR	    XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR    XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR	    XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR    XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR	    XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR    XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR	    XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR    XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR	    XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR	    XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR	    XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR	    XPS_CSU_WDT_INT_ID
+#define XPAR_XWDTPS_1_INTR	    XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_2_INTR	    XPS_FPD_SWDT_INT_ID
+#define XPAR_XDCFG_0_INTR	    XPS_DVC_INT_ID
+#define XPAR_XTTCPS_0_INTR	    XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR	    XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR	    XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR	    XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR	    XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR	    XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR	    XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR	    XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR	    XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR	    XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR	    XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR	    XPS_TTC3_2_INT_ID
+#define XPAR_XNANDPS8_0_INTR            XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 	    XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 	    XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR	    XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 	    XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR	    XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 	    XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 	    XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 	    XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 	    XPS_CSU_DMA_INT_ID
+#define XPAR_PSU_ADMA_0_INTR 	    XPS_ADMA_CH0_INT_ID
+#define XPAR_PSU_ADMA_1_INTR 	    XPS_ADMA_CH1_INT_ID
+#define XPAR_PSU_ADMA_2_INTR	    XPS_ADMA_CH2_INT_ID
+#define XPAR_PSU_ADMA_3_INTR 	    XPS_ADMA_CH3_INT_ID
+#define XPAR_PSU_ADMA_4_INTR	    XPS_ADMA_CH4_INT_ID
+#define XPAR_PSU_ADMA_5_INTR 	    XPS_ADMA_CH5_INT_ID
+#define XPAR_PSU_ADMA_6_INTR 	    XPS_ADMA_CH6_INT_ID
+#define XPAR_PSU_ADMA_7_INTR 	    XPS_ADMA_CH7_INT_ID
+#define XPAR_PSU_CSUDMA_INTR 	    XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 	    XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR	    XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR	    XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 	    XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 	    XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR	    XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 	    XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 	    XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 	    XPS_ZDMA_CH7_INT_ID
+#define XPAR_PSU_GDMA_0_INTR	    XPS_ZDMA_CH0_INT_ID
+#define XPAR_PSU_GDMA_1_INTR	    XPS_ZDMA_CH1_INT_ID
+#define XPAR_PSU_GDMA_2_INTR 	    XPS_ZDMA_CH2_INT_ID
+#define XPAR_PSU_GDMA_3_INTR 	    XPS_ZDMA_CH3_INT_ID
+#define XPAR_PSU_GDMA_4_INTR	    XPS_ZDMA_CH4_INT_ID
+#define XPAR_PSU_GDMA_5_INTR 	    XPS_ZDMA_CH5_INT_ID
+#define XPAR_PSU_GDMA_6_INTR 	    XPS_ZDMA_CH6_INT_ID
+#define XPAR_PSU_GDMA_7_INTR 	    XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 	    XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 	    XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 	    XPS_FPD_SMMU_INT_ID
+#define XPAR_XUSBPS_0_INTR	    XPS_USB3_0_ENDPT_INT_ID
+#define XPAR_XUSBPS_1_INTR	    XPS_USB3_1_ENDPT_INT_ID
+#define XPAR_XUSBPS_0_WAKE_INTR	    XPS_USB3_0_WAKE_INT_ID
+#define XPAR_XUSBPS_1_WAKE_INTR	    XPS_USB3_1_WAKE_INT_ID
+#define    XPAR_XRTCPSU_ALARM_INTR     XPS_RTC_ALARM_INT_ID
+#define    XPAR_XRTCPSU_SECONDS_INTR    XPS_RTC_SEC_INT_ID
+#define XPAR_XAPMPS_0_INTR	    XPS_APM0_INT_ID
+#define XPAR_XAPMPS_1_INTR	    XPS_APM1_INT_ID
+#define XPAR_XAPMPS_2_INTR	    XPS_APM2_INT_ID
+#define XPAR_XAPMPS_5_INTR	    XPS_APM5_INT_ID
+#define XPAR_XSYSMONPSU_INTR	    XPS_AMS_INT_ID
 
 /* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES	1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_NUM_INSTANCES    1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID    0U
 #define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
 #define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
-#define XPAR_SCUGIC_ACK_BEFORE		0U
+#define XPAR_SCUGIC_ACK_BEFORE	    0U
 
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
 
 
 /*
@@ -154,27 +154,27 @@ extern "C" {
  * within the hardblock. These have been put for bacwards compatibility
  */
 
-#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
-#define XPS_SCU_PERIPH_BASE		0xF9000000U
+#define XPS_SYS_CTRL_BASEADDR    0xFF180000U
+#define XPS_SCU_PERIPH_BASE	    0xF9000000U
 
 
 /* Shared Peripheral Interrupts (SPI) */
-#define XPS_FPGA0_INT_ID		121U
-#define XPS_FPGA1_INT_ID		122U
-#define XPS_FPGA2_INT_ID		123U
-#define XPS_FPGA3_INT_ID		124U
-#define XPS_FPGA4_INT_ID		125U
-#define XPS_FPGA5_INT_ID		126U
-#define XPS_FPGA6_INT_ID		127U
-#define XPS_FPGA7_INT_ID		128U
-#define XPS_FPGA8_INT_ID		136U
-#define XPS_FPGA9_INT_ID		137U
-#define XPS_FPGA10_INT_ID		138U
-#define XPS_FPGA11_INT_ID		139U
-#define XPS_FPGA12_INT_ID		140U
-#define XPS_FPGA13_INT_ID		141U
-#define XPS_FPGA14_INT_ID		142U
-#define XPS_FPGA15_INT_ID		143U
+#define XPS_FPGA0_INT_ID	    121U
+#define XPS_FPGA1_INT_ID	    122U
+#define XPS_FPGA2_INT_ID	    123U
+#define XPS_FPGA3_INT_ID	    124U
+#define XPS_FPGA4_INT_ID	    125U
+#define XPS_FPGA5_INT_ID	    126U
+#define XPS_FPGA6_INT_ID	    127U
+#define XPS_FPGA7_INT_ID	    128U
+#define XPS_FPGA8_INT_ID	    136U
+#define XPS_FPGA9_INT_ID	    137U
+#define XPS_FPGA10_INT_ID	    138U
+#define XPS_FPGA11_INT_ID	    139U
+#define XPS_FPGA12_INT_ID	    140U
+#define XPS_FPGA13_INT_ID	    141U
+#define XPS_FPGA14_INT_ID	    142U
+#define XPS_FPGA15_INT_ID	    143U
 
 /* Updated Interrupt-IDs */
 #define XPS_OCMINTR_INT_ID		(10U + 32U)
@@ -189,8 +189,8 @@ extern "C" {
 #define XPS_UART1_INT_ID		(22U + 32U)
 #define XPS_CAN0_INT_ID			(23U + 32U)
 #define XPS_CAN1_INT_ID			(24U + 32U)
-#define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
-#define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
+#define    XPS_RTC_ALARM_INT_ID 	(26U + 32U)
+#define    XPS_RTC_SEC_INT_ID	 	(27U + 32U)
 #define XPS_LPD_SWDT_INT_ID		(52U + 32U)
 #define XPS_CSU_WDT_INT_ID	    (53U + 32U)
 #define XPS_FPD_SWDT_INT_ID		(113U + 32U)
@@ -268,8 +268,8 @@ extern "C" {
 #define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
 #define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
 #define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR    		XPS_LPD_SWDT_INT_ID
-#define XPAR_PSU_WDT_1_INTR     	XPS_FPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_0_INTR    	    XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_1_INTR         XPS_FPD_SWDT_INT_ID
 #define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
 #define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
 #define XPAR_PSU_TTC_1_INTR         XPS_TTC0_1_INT_ID
@@ -277,42 +277,42 @@ extern "C" {
 #define XPAR_PSU_TTC_3_INTR         XPS_TTC1_0_INT_ID
 #define XPAR_PSU_TTC_4_INTR         XPS_TTC1_1_INT_ID
 #define XPAR_PSU_TTC_5_INTR         XPS_TTC1_2_INT_ID
-#define XPAR_PSU_TTC_6_INTR			XPS_TTC2_0_INT_ID
-#define XPAR_PSU_TTC_7_INTR			XPS_TTC2_1_INT_ID
-#define XPAR_PSU_TTC_8_INTR			XPS_TTC2_2_INT_ID
-#define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
-#define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
-#define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
-#define XPAR_PSU_AMS_INTR			XPS_AMS_INT_ID
+#define XPAR_PSU_TTC_6_INTR		    XPS_TTC2_0_INT_ID
+#define XPAR_PSU_TTC_7_INTR		    XPS_TTC2_1_INT_ID
+#define XPAR_PSU_TTC_8_INTR		    XPS_TTC2_2_INT_ID
+#define XPAR_PSU_TTC_9_INTR		    XPS_TTC3_0_INT_ID
+#define XPAR_PSU_TTC_10_INTR	    XPS_TTC3_1_INT_ID
+#define XPAR_PSU_TTC_11_INTR	    XPS_TTC3_2_INT_ID
+#define XPAR_PSU_AMS_INTR		    XPS_AMS_INT_ID
 
 #define XPAR_XADCPS_NUM_INSTANCES 1U
 #define XPAR_XADCPS_0_DEVICE_ID   0U
 #define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
-#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+#define XPAR_XADCPS_INT_ID	    XPS_SYSMON_INT_ID
 
 /* For backwards compatibility */
-#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+#define XPAR_XUARTPS_0_CLOCK_HZ	    XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ	    XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ	    XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ	    XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ	    XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ	    XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ	    XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ	    XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ	    XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ	    XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
 
-#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+#define XPAR_XQSPIPS_0_CLOCK_HZ	    XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
 
 #ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
 #endif
 
 #ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
 #endif
 
-#define XPAR_SCUWDT_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID	    0U
 
 
 #ifdef __cplusplus

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h

@@ -12,12 +12,12 @@ extern "C" {
 #define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
 #define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
 #define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
-									XPAR_PMC_TAP_VERSION_OFFSET)
+								    XPAR_PMC_TAP_VERSION_OFFSET)
 #else
 #define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define	XPAR_CSU_VER_OFFSET 0x00000044U
+#define    XPAR_CSU_VER_OFFSET 0x00000044U
 #define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
-									XPAR_CSU_VER_OFFSET)
+								    XPAR_CSU_VER_OFFSET)
 #endif
 #define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
 #define XPLAT_ZYNQ_ULTRA_MP 0x1
@@ -44,13 +44,13 @@ extern "C" {
 static INLINE u32 XGetPlatform_Info()
 {
 #if defined (versal)
-	return XPLAT_VERSAL;
+    return XPLAT_VERSAL;
 #elif defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
-	return XPLAT_ZYNQ_ULTRA_MP;
+    return XPLAT_ZYNQ_ULTRA_MP;
 #elif (__microblaze__)
-	return XPLAT_MICROBLAZE;
+    return XPLAT_MICROBLAZE;
 #else
-	return XPLAT_ZYNQ;
+    return XPLAT_ZYNQ;
 #endif
 }
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h

@@ -87,7 +87,7 @@ extern "C" {
 #define XST_NOT_ENABLED                 29L	/*!< A requested service is not
 						   available because it has not
 						   been enabled */
-#define XST_NO_ACCESS			30L	/* Generic access error */
+#define XST_NO_ACCESS		    30L	/* Generic access error */
 #define XST_TIMEOUT                     31L	/*!< Event timeout occurred */
 
 /** @} */
@@ -258,7 +258,7 @@ extern "C" {
 #define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
 					     /* didn't return written value */
 #define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
-#define XST_IIC_ARB_LOST 				1089 	/*!< Arbitration lost for master	*/
+#define XST_IIC_ARB_LOST 			    1089 	/*!< Arbitration lost for master	*/
 /** @} */
 /**
 @name ATMC Status Codes 1101 - 1125
@@ -422,10 +422,10 @@ extern "C" {
 */
 /********************** FlexRay constants 1400 - 1409 *************************/
 
-#define XST_FR_TX_ERROR			1400
-#define XST_FR_TX_BUSY			1401
-#define XST_FR_BUF_LOCKED		1402
-#define XST_FR_NO_BUF			1403
+#define XST_FR_TX_ERROR		    1400
+#define XST_FR_TX_BUSY		    1401
+#define XST_FR_BUF_LOCKED	    1402
+#define XST_FR_NO_BUF		    1403
 /** @} */
 /**
 @name USB constants 1410 - 1420
@@ -433,11 +433,11 @@ extern "C" {
 */
 /****************** USB constants 1410 - 1420  *******************************/
 
-#define XST_USB_ALREADY_CONFIGURED	1410
-#define XST_USB_BUF_ALIGN_ERROR		1411
-#define XST_USB_NO_DESC_AVAILABLE	1412
-#define XST_USB_BUF_TOO_BIG		1413
-#define XST_USB_NO_BUF			1414
+#define XST_USB_ALREADY_CONFIGURED    1410
+#define XST_USB_BUF_ALIGN_ERROR	    1411
+#define XST_USB_NO_DESC_AVAILABLE    1412
+#define XST_USB_BUF_TOO_BIG	    1413
+#define XST_USB_NO_BUF		    1414
 /** @} */
 /**
 @name HWICAP constants 1421 - 1429
@@ -445,7 +445,7 @@ extern "C" {
 */
 /****************** HWICAP constants 1421 - 1429  *****************************/
 
-#define XST_HWICAP_WRITE_DONE		1421
+#define XST_HWICAP_WRITE_DONE	    1421
 
 /** @} */
 /**
@@ -454,7 +454,7 @@ extern "C" {
 */
 /****************** AXI VDMA constants 1430 - 1440  *****************************/
 
-#define XST_VDMA_MISMATCH_ERROR		1430
+#define XST_VDMA_MISMATCH_ERROR	    1430
 /** @} */
 /**
 @name NAND Flash Status Codes 1441 - 1459
@@ -462,35 +462,35 @@ extern "C" {
 */
 /*********************** NAND Flash statuses 1441 - 1459  *********************/
 
-#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+#define XST_NAND_BUSY		    1441L	/*!< Flash is erasing or
 						 * programming
 						 */
-#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+#define XST_NAND_READY		    1442L	/*!< Flash is ready for commands
 						 */
-#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+#define XST_NAND_ERROR		    1443L	/*!< Flash had detected an
 						 * internal error.
 						 */
-#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+#define XST_NAND_PART_NOT_SUPPORTED    1444L	/*!< Flash type not supported by
 						 * driver
 						 */
-#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+#define XST_NAND_OPT_NOT_SUPPORTED    1445L	/*!< Operation not supported
 						 */
-#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+#define XST_NAND_TIMEOUT_ERROR	    1446L	/*!< Programming or erase
 						 * operation aborted due to a
 						 * timeout
 						 */
-#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+#define XST_NAND_ADDRESS_ERROR	    1447L	/*!< Accessed flash outside its
 						 * addressible range
 						 */
-#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+#define XST_NAND_ALIGNMENT_ERROR    1448L	/*!< Write alignment error
 						 */
-#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+#define XST_NAND_PARAM_PAGE_ERROR    1449L	/*!< Failed to read parameter
 						 * page of the device
 						 */
-#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+#define XST_NAND_CACHE_ERROR	    1450L	/*!< Flash page buffer error
 						 */
 
-#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+#define XST_NAND_WRITE_PROTECTED    1451L	/*!< Flash is write protected
 						 */
 /** @} */
 

bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c

@@ -64,7 +64,7 @@ void rt_zynqmp_eth_link_detect(struct rt_zynqmp_eth *eth_dev)
     if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
             (eth_link_status == ETH_LINK_UNDEFINED))
         return;
-    
+
     phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
 
     if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
@@ -173,7 +173,7 @@ static rt_err_t rt_zynqmp_eth_init(rt_device_t dev)
 
     setup_isr(xemac);
     init_dma(xemac);
-    
+
     xtopologyp = &xtopology[xemac->topology_index];
     /*
     * Connect the device driver handler that will be called when an
@@ -190,7 +190,7 @@ static rt_err_t rt_zynqmp_eth_init(rt_device_t dev)
 
     if (eth_link_status == ETH_LINK_UP)
         eth_device_linkchange(&eth_dev->parent, RT_TRUE);
-    
+
     rt_thread_t tid;
     tid = rt_thread_create("phylnk",
                            phy_monitor_thread,

bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c

@@ -47,10 +47,10 @@ static int rt_hw_timer_init(void)
     /* Setup interval */
     TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
     /* Clear all of the prescaler control bits in the register */
-    TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK | 
+    TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK |
                                             TTC_CLK_CNTRL_PS_EN_MASK);
     /* We do not need a prescaler*/
-    
+
     /* Register the ticker handler with the GIC */
     rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
     /* Enable TTC interrupts in the GIC */

bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h

@@ -9,11 +9,11 @@
 #define __REG8(x)  (*((volatile rt_uint8_t *)(x)))
 
 #define ZynqMP_CRL_APB_BASEADDR        XPAR_PSU_CRL_APB_S_AXI_BASEADDR
-#define ZynqMP_CRL_APB_IOPLL_CTRL	   0x020    
-#define ZynqMP_CRL_APB_IOPLL_CFG	   0x024   
-#define ZynqMP_CRL_APB_UART0_REF_CTRL  0x074   
-#define ZynqMP_CRL_APB_UART1_REF_CTRL  0x078   
-#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL  0x0AC  
+#define ZynqMP_CRL_APB_IOPLL_CTRL	   0x020
+#define ZynqMP_CRL_APB_IOPLL_CFG	   0x024
+#define ZynqMP_CRL_APB_UART0_REF_CTRL  0x074
+#define ZynqMP_CRL_APB_UART1_REF_CTRL  0x078
+#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL  0x0AC
 #define ZynqMP_CRL_APB_RESET_CTRL      0x218
 #define ZynqMP_RESET_MASK       0x10