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@@ -1,11 +1,11 @@
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/*
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/*
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- * Copyright (C) 2020, Huada Semiconductor Co., Ltd.
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+ * Copyright (C) 2021, Huada Semiconductor Co., Ltd.
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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- * 2021-8-19 pjq first version
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+ * 2021-08-19 pjq first version
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*/
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*/
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#include <rtthread.h>
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#include <rtthread.h>
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@@ -125,75 +125,7 @@ void Gpio_IRQHandler(uint8_t u8Param)
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rt_interrupt_leave();
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rt_interrupt_leave();
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}
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}
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-//void PORTA_IRQHandler(void)
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-//{
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-// en_gpio_pin_t i;
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-//
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-// rt_interrupt_enter();
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-// for (i=GpioPin0; i<=GpioPin15; i++)
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-// {
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-// if(TRUE == Gpio_GetIrqStatus(GpioPortA, i))
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-// {
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-// Gpio_ClearIrq(GpioPortA, i);
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-// pin_irq_handler(GpioPortA, i);
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-// }
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-
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-// }
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-// rt_interrupt_leave();
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-//}
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-
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-//void PORTB_IRQHandler(void)
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-//{
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-// en_gpio_pin_t i;
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-//
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-// rt_interrupt_enter();
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-// for (i=GpioPin0; i<=GpioPin15; i++)
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-// {
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-// if(TRUE == Gpio_GetIrqStatus(GpioPortB, i))
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-// {
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-// Gpio_ClearIrq(GpioPortB, i);
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-// pin_irq_handler(GpioPortB, i);
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-// }
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-
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-// }
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-// rt_interrupt_leave();
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-//}
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-
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-//void PORTC_IRQHandler(void)
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-//{
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-// en_gpio_pin_t i;
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-//
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-// rt_interrupt_enter();
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-// for (i=GpioPin0; i<=GpioPin15; i++)
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-// {
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-// if(TRUE == Gpio_GetIrqStatus(GpioPortC, i))
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-// {
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-// Gpio_ClearIrq(GpioPortC, i);
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-// pin_irq_handler(GpioPortC, i);
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-// }
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-
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-// }
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-// rt_interrupt_leave();
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-//}
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-
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-//void PORTD_IRQHandler(void)
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-//{
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-// en_gpio_pin_t i;
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-//
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-// rt_interrupt_enter();
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-// for (i=GpioPin0; i<=GpioPin15; i++)
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-// {
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-// if(TRUE == Gpio_GetIrqStatus(GpioPortD, i))
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-// {
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-// Gpio_ClearIrq(GpioPortD, i);
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-// pin_irq_handler(GpioPortD, i);
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-// }
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-
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-// }
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-// rt_interrupt_leave();
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-//}
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-
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-static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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{
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uint8_t gpio_port;
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uint8_t gpio_port;
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uint16_t gpio_pin;
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uint16_t gpio_pin;
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@@ -213,7 +145,7 @@ static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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}
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}
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}
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}
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-static int hc32_pin_read(rt_device_t dev, rt_base_t pin)
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+static int _pin_read(rt_device_t dev, rt_base_t pin)
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{
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{
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uint8_t gpio_port;
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uint8_t gpio_port;
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uint16_t gpio_pin;
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uint16_t gpio_pin;
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@@ -236,7 +168,7 @@ static int hc32_pin_read(rt_device_t dev, rt_base_t pin)
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return value;
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return value;
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}
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}
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-static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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{
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uint8_t gpio_port;
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uint8_t gpio_port;
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uint16_t gpio_pin;
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uint16_t gpio_pin;
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@@ -290,7 +222,7 @@ static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
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Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
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}
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}
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-static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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{
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rt_base_t level;
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rt_base_t level;
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@@ -325,7 +257,7 @@ static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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return RT_EOK;
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return RT_EOK;
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}
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}
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-static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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{
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rt_base_t level;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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rt_int32_t irqindex = -1;
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@@ -351,7 +283,7 @@ static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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return RT_EOK;
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return RT_EOK;
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}
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}
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-static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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{
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rt_base_t level;
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rt_base_t level;
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en_gpio_port_t gpio_port;
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en_gpio_port_t gpio_port;
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@@ -428,21 +360,21 @@ static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
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return RT_EOK;
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return RT_EOK;
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}
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}
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-static const struct rt_pin_ops pin_ops =
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+static const struct rt_pin_ops _pin_ops =
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{
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{
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- hc32_pin_mode,
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- hc32_pin_write,
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- hc32_pin_read,
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- hc32_pin_attach_irq,
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- hc32_pin_detach_irq,
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- hc32_pin_irq_enable,
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+ _pin_mode,
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+ _pin_write,
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+ _pin_read,
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+ _pin_attach_irq,
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+ _pin_detach_irq,
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+ _pin_irq_enable,
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};
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};
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int rt_hw_pin_init(void)
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int rt_hw_pin_init(void)
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{
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{
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Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
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Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
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- return rt_device_pin_register("pin", &pin_ops, RT_NULL);
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+ return rt_device_pin_register("pin", &_pin_ops, RT_NULL);
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}
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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