add lpc1788

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1759 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.c

@@ -0,0 +1,358 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V2.00
+ * @date     13. September 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined   ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm           /*!< asm keyword for TASKING Compiler          */
+  #define __INLINE         inline          /*!< inline keyword for TASKING Compiler       */
+
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __CLREX(void)
+{
+  clrex
+}
+#endif /* __ARMCC_VERSION  */
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_IPSR(void)
+{
+  mrs r0, ipsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_APSR(void)
+{
+  mrs r0, apsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_xPSR(void)
+{
+  mrs r0, xpsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask Register.
+
+    \return               Fault Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+/** \brief  Set the Fault Mask
+
+     This function assigns the given value to the Fault Mask Register.
+
+    \param [in]    faultMask  Fault Mask value value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

bsp/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.h

@@ -0,0 +1,1242 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V2.01
+ * @date     06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
+ @ingroup CMSIS
+
+  List of Lint messages which will be suppressed and not shown:
+    - not yet checked
+  .
+  Note:  To re-enable a Message, insert a space before 'lint' *
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  @ingroup CMSIS
+  This file defines all structures and symbols for CMSIS core:
+    - CMSIS version number
+    - Cortex-M core
+    - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+#include <stdint.h>                      /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  @ingroup CMSIS
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+ @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t RELOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t CURR;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __IO  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
+  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
+  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
+  Type definitions for the Cortex-M Interrupt Type Register
+  @{
+ */
+
+/** \brief  Structure type to access the Interrupt Type Register.
+ */
+typedef struct
+{
+       uint32_t RESERVED0;
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
+#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
+#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
+
+/*@}*/ /* end of group CMSIS_InterruptType */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  @ingroup CMSIS
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                       |
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->RELOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->CURR   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*lint -restore */

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/LPC177x_8x.h

@@ -0,0 +1,1443 @@
+/**********************************************************************
+* $Id: LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $		LPC177x_8x.h			2011-06-02
+*//**
+* @file		LPC177x_8x.h
+* @brief	Cortex-M3 Core Peripheral Access Layer Header File for
+*			NXP LPC177x_8x Series.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __LPC177x_8x_H__
+#define __LPC177x_8x_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
+
+/******  LPC177x_8x Specific Interrupt Numbers *******************************************************/
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
+  Reserved0_IRQn                = 13,       /*!< Reserved                                         */
+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
+  MCI_IRQn                      = 29,       /*!< SD/MMC card I/F Interrupt                        */
+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
+  USBActivity_IRQn              = 33,       /*!< USB Activity interrupt                           */
+  CANActivity_IRQn              = 34,       /*!< CAN Activity interrupt                           */
+  UART4_IRQn                    = 35,       /*!< UART4 Interrupt                                  */
+  SSP2_IRQn                     = 36,       /*!< SSP2 Interrupt                                   */
+  LCD_IRQn                      = 37,       /*!< LCD Interrupt                                    */
+  GPIO_IRQn                     = 38,       /*!< GPIO Interrupt                                   */
+  PWM0_IRQn                     = 39,       /*!< PWM0 Interrupt                                   */
+  EEPROM_IRQn                   = 40,       /*!< EEPROM Interrupt                           */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
+//#include "system_LPC177x_8x.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
+       uint32_t RESERVED0[31];
+  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
+  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
+  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
+  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
+       uint32_t RESERVED1[4];
+  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
+  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
+  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
+  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
+       uint32_t RESERVED2[4];
+  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
+  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
+       uint32_t RESERVED3[14];
+  __IO uint32_t EMCCLKSEL;                  /*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
+  __IO uint32_t CCLKSEL;                    /*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
+  __IO uint32_t USBCLKSEL;                  /*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
+  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
+  __IO uint32_t	CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
+  __IO uint32_t	CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
+       uint32_t RESERVED4[10];
+  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
+       uint32_t RESERVED5[1];
+  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
+  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
+       uint32_t RESERVED6[12];
+  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
+       uint32_t RESERVED7[7];
+  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
+  __IO uint32_t IRCTRIM;                    /*!< Offset: 0x1A4 (R/W) Clock Dividers                     */
+  __IO uint32_t PCLKSEL;                    /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
+       uint32_t RESERVED8[3];
+  __IO uint32_t LCD_CFG;                    /*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
+       uint32_t RESERVED9[1];
+  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
+  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
+  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
+  __IO uint32_t RSTCON0;                    /*!< Offset: 0x1CC (R/W)  RESET Control0 Register */
+  __IO uint32_t RSTCON1;                    /*!< Offset: 0x1D0 (R/W)  RESET Control1 Register */
+       uint32_t RESERVED10[2];
+  __IO uint32_t EMCDLYCTL;                  /*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
+  __IO uint32_t EMCCAL;                     /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+  __IO uint32_t P0_0;				/* 0x000 */
+  __IO uint32_t P0_1;
+  __IO uint32_t P0_2;
+  __IO uint32_t P0_3;
+  __IO uint32_t P0_4;
+  __IO uint32_t P0_5;
+  __IO uint32_t P0_6;
+  __IO uint32_t P0_7;
+
+  __IO uint32_t P0_8;				/* 0x020 */
+  __IO uint32_t P0_9;
+  __IO uint32_t P0_10;
+  __IO uint32_t P0_11;
+  __IO uint32_t P0_12;
+  __IO uint32_t P0_13;
+  __IO uint32_t P0_14;
+  __IO uint32_t P0_15;
+
+  __IO uint32_t P0_16;				/* 0x040 */
+  __IO uint32_t P0_17;
+  __IO uint32_t P0_18;
+  __IO uint32_t P0_19;
+  __IO uint32_t P0_20;
+  __IO uint32_t P0_21;
+  __IO uint32_t P0_22;
+  __IO uint32_t P0_23;
+
+  __IO uint32_t P0_24;				/* 0x060 */
+  __IO uint32_t P0_25;
+  __IO uint32_t P0_26;
+  __IO uint32_t P0_27;
+  __IO uint32_t P0_28;
+  __IO uint32_t P0_29;
+  __IO uint32_t P0_30;
+  __IO uint32_t P0_31;
+
+  __IO uint32_t P1_0;				/* 0x080 */
+  __IO uint32_t P1_1;
+  __IO uint32_t P1_2;
+  __IO uint32_t P1_3;
+  __IO uint32_t P1_4;
+  __IO uint32_t P1_5;
+  __IO uint32_t P1_6;
+  __IO uint32_t P1_7;
+
+  __IO uint32_t P1_8;				/* 0x0A0 */
+  __IO uint32_t P1_9;
+  __IO uint32_t P1_10;
+  __IO uint32_t P1_11;
+  __IO uint32_t P1_12;
+  __IO uint32_t P1_13;
+  __IO uint32_t P1_14;
+  __IO uint32_t P1_15;
+
+  __IO uint32_t P1_16;				/* 0x0C0 */
+  __IO uint32_t P1_17;
+  __IO uint32_t P1_18;
+  __IO uint32_t P1_19;
+  __IO uint32_t P1_20;
+  __IO uint32_t P1_21;
+  __IO uint32_t P1_22;
+  __IO uint32_t P1_23;
+
+  __IO uint32_t P1_24;				/* 0x0E0 */
+  __IO uint32_t P1_25;
+  __IO uint32_t P1_26;
+  __IO uint32_t P1_27;
+  __IO uint32_t P1_28;
+  __IO uint32_t P1_29;
+  __IO uint32_t P1_30;
+  __IO uint32_t P1_31;
+
+  __IO uint32_t P2_0;				/* 0x100 */
+  __IO uint32_t P2_1;
+  __IO uint32_t P2_2;
+  __IO uint32_t P2_3;
+  __IO uint32_t P2_4;
+  __IO uint32_t P2_5;
+  __IO uint32_t P2_6;
+  __IO uint32_t P2_7;
+
+  __IO uint32_t P2_8;				/* 0x120 */
+  __IO uint32_t P2_9;
+  __IO uint32_t P2_10;
+  __IO uint32_t P2_11;
+  __IO uint32_t P2_12;
+  __IO uint32_t P2_13;
+  __IO uint32_t P2_14;
+  __IO uint32_t P2_15;
+
+  __IO uint32_t P2_16;				/* 0x140 */
+  __IO uint32_t P2_17;
+  __IO uint32_t P2_18;
+  __IO uint32_t P2_19;
+  __IO uint32_t P2_20;
+  __IO uint32_t P2_21;
+  __IO uint32_t P2_22;
+  __IO uint32_t P2_23;
+
+  __IO uint32_t P2_24;				/* 0x160 */
+  __IO uint32_t P2_25;
+  __IO uint32_t P2_26;
+  __IO uint32_t P2_27;
+  __IO uint32_t P2_28;
+  __IO uint32_t P2_29;
+  __IO uint32_t P2_30;
+  __IO uint32_t P2_31;
+
+  __IO uint32_t P3_0;				/* 0x180 */
+  __IO uint32_t P3_1;
+  __IO uint32_t P3_2;
+  __IO uint32_t P3_3;
+  __IO uint32_t P3_4;
+  __IO uint32_t P3_5;
+  __IO uint32_t P3_6;
+  __IO uint32_t P3_7;
+
+  __IO uint32_t P3_8;				/* 0x1A0 */
+  __IO uint32_t P3_9;
+  __IO uint32_t P3_10;
+  __IO uint32_t P3_11;
+  __IO uint32_t P3_12;
+  __IO uint32_t P3_13;
+  __IO uint32_t P3_14;
+  __IO uint32_t P3_15;
+
+  __IO uint32_t P3_16;				/* 0x1C0 */
+  __IO uint32_t P3_17;
+  __IO uint32_t P3_18;
+  __IO uint32_t P3_19;
+  __IO uint32_t P3_20;
+  __IO uint32_t P3_21;
+  __IO uint32_t P3_22;
+  __IO uint32_t P3_23;
+
+  __IO uint32_t P3_24;				/* 0x1E0 */
+  __IO uint32_t P3_25;
+  __IO uint32_t P3_26;
+  __IO uint32_t P3_27;
+  __IO uint32_t P3_28;
+  __IO uint32_t P3_29;
+  __IO uint32_t P3_30;
+  __IO uint32_t P3_31;
+
+  __IO uint32_t P4_0;				/* 0x200 */
+  __IO uint32_t P4_1;
+  __IO uint32_t P4_2;
+  __IO uint32_t P4_3;
+  __IO uint32_t P4_4;
+  __IO uint32_t P4_5;
+  __IO uint32_t P4_6;
+  __IO uint32_t P4_7;
+
+  __IO uint32_t P4_8;				/* 0x220 */
+  __IO uint32_t P4_9;
+  __IO uint32_t P4_10;
+  __IO uint32_t P4_11;
+  __IO uint32_t P4_12;
+  __IO uint32_t P4_13;
+  __IO uint32_t P4_14;
+  __IO uint32_t P4_15;
+
+  __IO uint32_t P4_16;				/* 0x240 */
+  __IO uint32_t P4_17;
+  __IO uint32_t P4_18;
+  __IO uint32_t P4_19;
+  __IO uint32_t P4_20;
+  __IO uint32_t P4_21;
+  __IO uint32_t P4_22;
+  __IO uint32_t P4_23;
+
+  __IO uint32_t P4_24;				/* 0x260 */
+  __IO uint32_t P4_25;
+  __IO uint32_t P4_26;
+  __IO uint32_t P4_27;
+  __IO uint32_t P4_28;
+  __IO uint32_t P4_29;
+  __IO uint32_t P4_30;
+  __IO uint32_t P4_31;
+
+  __IO uint32_t P5_0;				/* 0x280 */
+  __IO uint32_t P5_1;
+  __IO uint32_t P5_2;
+  __IO uint32_t P5_3;
+  __IO uint32_t P5_4;				/* 0x290 */
+} LPC_IOCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+  __IO uint32_t DIR;
+       uint32_t RESERVED0[3];
+  __IO uint32_t MASK;
+  __IO uint32_t PIN;
+  __IO uint32_t SET;
+  __O  uint32_t CLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+  __I  uint32_t IntStatus;
+  __I  uint32_t IO0IntStatR;
+  __I  uint32_t IO0IntStatF;
+  __O  uint32_t IO0IntClr;
+  __IO uint32_t IO0IntEnR;
+  __IO uint32_t IO0IntEnF;
+       uint32_t RESERVED0[3];
+  __I  uint32_t IO2IntStatR;
+  __I  uint32_t IO2IntStatF;
+  __O  uint32_t IO2IntClr;
+  __IO uint32_t IO2IntEnR;
+  __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
+  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
+  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
+  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
+  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
+  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
+  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
+  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
+  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
+  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
+  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
+       uint32_t RESERVED0[2];
+  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
+       uint32_t RESERVED1[12];
+  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
+  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
+  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
+  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
+  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
+  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
+  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
+  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
+  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
+  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
+  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
+  __I  uint32_t CR2;					/*!< Offset: 0x034 Capture Register 2 (R/ ) */
+  __I  uint32_t CR3;					/*!< Offset: 0x038 Capture Register 3 (R/ ) */
+       uint32_t RESERVED0;
+  __IO uint32_t MR4;					/*!< Offset: 0x040 Match Register 4 (R/W) */
+  __IO uint32_t MR5;					/*!< Offset: 0x044 Match Register 5 (R/W) */
+  __IO uint32_t MR6;					/*!< Offset: 0x048 Match Register 6 (R/W) */
+  __IO uint32_t PCR;					/*!< Offset: 0x04C PWM Control Register (R/W) */
+  __IO uint32_t LER;					/*!< Offset: 0x050 Load Enable Register (R/W) */
+       uint32_t RESERVED1[7];
+  __IO uint32_t CTCR;					/*!< Offset: 0x070 Counter Control Register (R/W) */
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
+/* There are three types of UARTs on the chip:
+(1) UART0,UART2, and UART3 are the standard UART.
+(2) UART1 is the standard with modem capability.
+(3) USART(UART4) is the sync/async UART with smart card capability.
+More details can be found on the Users Manual. */
+
+#if 0
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;
+} LPC_UART_TypeDef;
+#else
+typedef struct
+{
+	union
+	{
+		__I  uint8_t  RBR;
+		__O  uint8_t  THR;
+		__IO uint8_t  DLL;
+		uint32_t RESERVED0;
+	};
+	union
+	{
+		__IO uint8_t  DLM;
+		__IO uint32_t IER;
+	};
+	union
+	{
+		__I  uint32_t IIR;
+		__O  uint8_t  FCR;
+	};
+	__IO uint8_t  LCR;
+	uint8_t  RESERVED1[7];//Reserved
+	__I  uint8_t  LSR;
+	uint8_t  RESERVED2[7];//Reserved
+	__IO uint8_t  SCR;
+	uint8_t  RESERVED3[3];//Reserved
+	__IO uint32_t ACR;
+	__IO uint8_t  ICR;
+	uint8_t  RESERVED4[3];//Reserved
+	__IO uint8_t  FDR;
+	uint8_t  RESERVED5[7];//Reserved
+	__IO uint8_t  TER;
+	uint8_t  RESERVED8[27];//Reserved
+	__IO uint8_t  RS485CTRL;
+	uint8_t  RESERVED9[3];//Reserved
+	__IO uint8_t  ADRMATCH;
+	uint8_t  RESERVED10[3];//Reserved
+	__IO uint8_t  RS485DLY;
+	uint8_t  RESERVED11[3];//Reserved
+	__I  uint8_t  FIFOLVL;
+}LPC_UART_TypeDef;
+#endif
+
+
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  MCR;
+       uint8_t  RESERVED2[3];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED3[3];
+  __I  uint8_t  MSR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED5[3];
+  __IO uint32_t ACR;
+       uint32_t RESERVED6;
+  __IO uint32_t FDR;
+       uint32_t RESERVED7;
+  __IO uint8_t  TER;
+       uint8_t  RESERVED8[27];
+  __IO uint8_t  RS485CTRL;
+       uint8_t  RESERVED9[3];
+  __IO uint8_t  ADRMATCH;
+       uint8_t  RESERVED10[3];
+  __IO uint8_t  RS485DLY;
+       uint8_t  RESERVED11[3];
+  __I  uint8_t  FIFOLVL;
+} LPC_UART1_TypeDef;
+
+typedef struct
+{
+  union {
+  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
+  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+  };
+  union {
+  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+  };
+  union {
+  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
+  };
+  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
+  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
+  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
+  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
+  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+  __IO uint32_t  ICR;                   /*!< Offset: 0x024 irDA Control Register (R/W) */
+  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+  __IO uint32_t  OSR;                   /*!< Offset: 0x02C Over sampling Register (R/W) */
+  __O  uint32_t  POP;                   /*!< Offset: 0x030 NHP Pop Register (W) */
+  __IO uint32_t  MODE;                  /*!< Offset: 0x034 NHP Mode selection Register (W) */
+       uint32_t  RESERVED0[2];
+  __IO uint32_t  HDEN;                  /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
+       uint32_t  RESERVED1;
+  __IO uint32_t  SCI_CTRL;				/*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
+  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+  __IO uint32_t  SYNCCTRL;              /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
+  __IO uint32_t  TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */
+       uint32_t  RESERVED2[989];
+  __I  uint32_t  CFG;                   /*!< Offset: 0xFD4 Configuration Register (R) */
+  __O  uint32_t  INTCE;                 /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
+  __O  uint32_t  INTSE;                 /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
+  __I  uint32_t  INTS;                  /*!< Offset: 0xFE0 Interrupt Status Register (R) */
+  __I  uint32_t  INTE;                  /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
+  __O  uint32_t  INTCS;                 /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
+  __O  uint32_t  INTSS;                 /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
+       uint32_t  RESERVED3[3];
+  __I  uint32_t  MID;                   /*!< Offset: 0xFFC Module Identification Register (R) */
+} LPC_UART4_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
+  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
+  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
+  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
+  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
+  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
+  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
+  __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
+  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
+  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
+  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
+  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t DAO;
+  __IO uint32_t DAI;
+  __O  uint32_t TXFIFO;
+  __I  uint32_t RXFIFO;
+  __I  uint32_t STATE;
+  __IO uint32_t DMA1;
+  __IO uint32_t DMA2;
+  __IO uint32_t IRQ;
+  __IO uint32_t TXRATE;
+  __IO uint32_t RXRATE;
+  __IO uint32_t TXBITRATE;
+  __IO uint32_t RXBITRATE;
+  __IO uint32_t TXMODE;
+  __IO uint32_t RXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  ILR;
+       uint8_t  RESERVED0[7];
+  __IO uint8_t  CCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  CIIR;
+       uint8_t  RESERVED2[3];
+  __IO uint8_t  AMR;
+       uint8_t  RESERVED3[3];
+  __I  uint32_t CTIME0;
+  __I  uint32_t CTIME1;
+  __I  uint32_t CTIME2;
+  __IO uint8_t  SEC;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  MIN;
+       uint8_t  RESERVED5[3];
+  __IO uint8_t  HOUR;
+       uint8_t  RESERVED6[3];
+  __IO uint8_t  DOM;
+       uint8_t  RESERVED7[3];
+  __IO uint8_t  DOW;
+       uint8_t  RESERVED8[3];
+  __IO uint16_t DOY;
+       uint16_t RESERVED9;
+  __IO uint8_t  MONTH;
+       uint8_t  RESERVED10[3];
+  __IO uint16_t YEAR;
+       uint16_t RESERVED11;
+  __IO uint32_t CALIBRATION;
+  __IO uint32_t GPREG0;
+  __IO uint32_t GPREG1;
+  __IO uint32_t GPREG2;
+  __IO uint32_t GPREG3;
+  __IO uint32_t GPREG4;
+  __IO uint8_t  RTC_AUXEN;
+       uint8_t  RESERVED12[3];
+  __IO uint8_t  RTC_AUX;
+       uint8_t  RESERVED13[3];
+  __IO uint8_t  ALSEC;
+       uint8_t  RESERVED14[3];
+  __IO uint8_t  ALMIN;
+       uint8_t  RESERVED15[3];
+  __IO uint8_t  ALHOUR;
+       uint8_t  RESERVED16[3];
+  __IO uint8_t  ALDOM;
+       uint8_t  RESERVED17[3];
+  __IO uint8_t  ALDOW;
+       uint8_t  RESERVED18[3];
+  __IO uint16_t ALDOY;
+       uint16_t RESERVED19;
+  __IO uint8_t  ALMON;
+       uint8_t  RESERVED20[3];
+  __IO uint16_t ALYEAR;
+       uint16_t RESERVED21;
+  __IO uint32_t ERSTATUS;
+  __IO uint32_t ERCONTROL;
+  __IO uint32_t ERCOUNTERS;
+       uint32_t RESERVED22;
+  __IO uint32_t ERFIRSTSTAMP0;
+  __IO uint32_t ERFIRSTSTAMP1;
+  __IO uint32_t ERFIRSTSTAMP2;
+       uint32_t RESERVED23;
+  __IO uint32_t ERLASTSTAMP0;
+  __IO uint32_t ERLASTSTAMP1;
+  __IO uint32_t ERLASTSTAMP2;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  MOD;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t TC;
+  __O  uint8_t  FEED;
+       uint8_t  RESERVED1[3];
+  __I  uint32_t TV;
+       uint32_t RESERVED2;
+  __IO uint32_t WARNINT;
+  __IO uint32_t WINDOW;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
+  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
+       uint32_t RESERVED0;
+  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
+  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
+  __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CTRL;
+  __IO uint32_t CNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+  __I  uint32_t CON;
+  __O  uint32_t CON_SET;
+  __O  uint32_t CON_CLR;
+  __I  uint32_t CAPCON;
+  __O  uint32_t CAPCON_SET;
+  __O  uint32_t CAPCON_CLR;
+  __IO uint32_t TC0;
+  __IO uint32_t TC1;
+  __IO uint32_t TC2;
+  __IO uint32_t LIM0;
+  __IO uint32_t LIM1;
+  __IO uint32_t LIM2;
+  __IO uint32_t MAT0;
+  __IO uint32_t MAT1;
+  __IO uint32_t MAT2;
+  __IO uint32_t DT;
+  __IO uint32_t CP;
+  __IO uint32_t CAP0;
+  __IO uint32_t CAP1;
+  __IO uint32_t CAP2;
+  __I  uint32_t INTEN;
+  __O  uint32_t INTEN_SET;
+  __O  uint32_t INTEN_CLR;
+  __I  uint32_t CNTCON;
+  __O  uint32_t CNTCON_SET;
+  __O  uint32_t CNTCON_CLR;
+  __I  uint32_t INTF;
+  __O  uint32_t INTF_SET;
+  __O  uint32_t INTF_CLR;
+  __O  uint32_t CAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+  __O  uint32_t CON;
+  __I  uint32_t STAT;
+  __IO uint32_t CONF;
+  __I  uint32_t POS;
+  __IO uint32_t MAXPOS;
+  __IO uint32_t CMPOS0;
+  __IO uint32_t CMPOS1;
+  __IO uint32_t CMPOS2;
+  __I  uint32_t INXCNT;
+  __IO uint32_t INXCMP0;
+  __IO uint32_t LOAD;
+  __I  uint32_t TIME;
+  __I  uint32_t VEL;
+  __I  uint32_t CAP;
+  __IO uint32_t VELCOMP;
+  __IO uint32_t FILTERPHA;
+  __IO uint32_t FILTERPHB;
+  __IO uint32_t FILTERINX;
+  __IO uint32_t WINDOW;
+  __IO uint32_t INXCMP1;
+  __IO uint32_t INXCMP2;
+       uint32_t RESERVED0[993];
+  __O  uint32_t IEC;
+  __O  uint32_t IES;
+  __I  uint32_t INTSTAT;
+  __I  uint32_t IE;
+  __O  uint32_t CLR;
+  __O  uint32_t SET;
+} LPC_QEI_TypeDef;
+
+/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLOCK;
+  __IO uint32_t ARGUMENT;
+  __IO uint32_t COMMAND;
+  __I  uint32_t RESP_CMD;
+  __I  uint32_t RESP0;
+  __I  uint32_t RESP1;
+  __I  uint32_t RESP2;
+  __I  uint32_t RESP3;
+  __IO uint32_t DATATMR;
+  __IO uint32_t DATALEN;
+  __IO uint32_t DATACTRL;
+  __I  uint32_t DATACNT;
+  __I  uint32_t STATUS;
+  __O  uint32_t CLEAR;
+  __IO uint32_t MASK0;
+       uint32_t RESERVED0[2];
+  __I  uint32_t FIFOCNT;
+       uint32_t RESERVED1[13];
+  __IO uint32_t FIFO;
+} LPC_MCI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+  __IO uint32_t mask[512];              /* ID Masks                           */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct                          /* Acceptance Filter Registers        */
+{
+	///Offset: 0x00000000 - Acceptance Filter Register
+	__IO uint32_t AFMR;
+
+	///Offset: 0x00000004 - Standard Frame Individual Start Address Register
+	__IO uint32_t SFF_sa;
+
+	///Offset: 0x00000008 - Standard Frame Group Start Address Register
+	__IO uint32_t SFF_GRP_sa;
+
+	///Offset: 0x0000000C - Extended Frame Start Address Register
+	__IO uint32_t EFF_sa;
+
+	///Offset: 0x00000010 - Extended Frame Group Start Address Register
+	__IO uint32_t EFF_GRP_sa;
+
+	///Offset: 0x00000014 - End of AF Tables register
+	__IO uint32_t ENDofTable;
+
+	///Offset: 0x00000018 - LUT Error Address register
+	__I  uint32_t LUTerrAd;
+
+	///Offset: 0x0000001C - LUT Error Register
+	__I  uint32_t LUTerr;
+
+	///Offset: 0x00000020 - CAN Central Transmit Status Register
+	__IO uint32_t FCANIE;
+
+	///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
+	__IO uint32_t FCANIC0;
+
+	///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
+	__IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct                          /* Central Registers                  */
+{
+  __I  uint32_t TxSR;
+  __I  uint32_t RxSR;
+  __I  uint32_t MSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct                          /* Controller Registers               */
+{
+	///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
+	__IO uint32_t MOD;
+
+	///Offset: 0x00000004 - Command bits that affect the state
+	__O  uint32_t CMR;
+
+	///Offset: 0x00000008 - Global Controller Status and Error Counters
+	__IO uint32_t GSR;
+
+	///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
+	__I  uint32_t ICR;
+
+	///Offset: 0x00000010 - Interrupt Enable Register
+	__IO uint32_t IER;
+
+	///Offset: 0x00000014 - Bus Timing Register
+	__IO uint32_t BTR;
+
+	///Offset: 0x00000018 - Error Warning Limit
+	__IO uint32_t EWL;
+
+	///Offset: 0x0000001C - Status Register
+	__I  uint32_t SR;
+
+	///Offset: 0x00000020 - Receive frame status
+	__IO uint32_t RFS;
+
+	///Offset: 0x00000024 - Received Identifier
+	__IO uint32_t RID;
+
+	///Offset: 0x00000028 - Received data bytes 1-4
+	__IO uint32_t RDA;
+
+	///Offset: 0x0000002C - Received data bytes 5-8
+	__IO uint32_t RDB;
+
+	///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
+	__IO uint32_t TFI1;
+
+	///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
+	__IO uint32_t TID1;
+
+	///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
+	__IO uint32_t TDA1;
+
+	///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
+	__IO uint32_t TDB1;
+
+	///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
+	__IO uint32_t TFI2;
+
+	///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
+	__IO uint32_t TID2;
+
+	///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
+	__IO uint32_t TDA2;
+
+	///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
+	__IO uint32_t TDB2;
+
+	///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
+	__IO uint32_t TFI3;
+
+	///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
+	__IO uint32_t TID3;
+
+	///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
+	__IO uint32_t TDA3;
+
+	///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
+	__IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct                          /* Common Registers                   */
+{
+  __I  uint32_t IntStat;
+  __I  uint32_t IntTCStat;
+  __O  uint32_t IntTCClear;
+  __I  uint32_t IntErrStat;
+  __O  uint32_t IntErrClr;
+  __I  uint32_t RawIntTCStat;
+  __I  uint32_t RawIntErrStat;
+  __I  uint32_t EnbldChns;
+  __IO uint32_t SoftBReq;
+  __IO uint32_t SoftSReq;
+  __IO uint32_t SoftLBReq;
+  __IO uint32_t SoftLSReq;
+  __IO uint32_t Config;
+  __IO uint32_t Sync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct                          /* Channel Registers                  */
+{
+  __IO uint32_t CSrcAddr;
+  __IO uint32_t CDestAddr;
+  __IO uint32_t CLLI;
+  __IO uint32_t CControl;
+  __IO uint32_t CConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+  __I  uint32_t Revision;             /* USB Host Registers                 */
+  __IO uint32_t Control;
+  __IO uint32_t CommandStatus;
+  __IO uint32_t InterruptStatus;
+  __IO uint32_t InterruptEnable;
+  __IO uint32_t InterruptDisable;
+  __IO uint32_t HCCA;
+  __I  uint32_t PeriodCurrentED;
+  __IO uint32_t ControlHeadED;
+  __IO uint32_t ControlCurrentED;
+  __IO uint32_t BulkHeadED;
+  __IO uint32_t BulkCurrentED;
+  __I  uint32_t DoneHead;
+  __IO uint32_t FmInterval;
+  __I  uint32_t FmRemaining;
+  __I  uint32_t FmNumber;
+  __IO uint32_t PeriodicStart;
+  __IO uint32_t LSTreshold;
+  __IO uint32_t RhDescriptorA;
+  __IO uint32_t RhDescriptorB;
+  __IO uint32_t RhStatus;
+  __IO uint32_t RhPortStatus1;
+  __IO uint32_t RhPortStatus2;
+       uint32_t RESERVED0[40];
+  __I  uint32_t Module_ID;
+
+  __I  uint32_t IntSt;               /* USB On-The-Go Registers            */
+  __IO uint32_t IntEn;
+  __O  uint32_t IntSet;
+  __O  uint32_t IntClr;
+  __IO uint32_t StCtrl;
+  __IO uint32_t Tmr;
+       uint32_t RESERVED1[58];
+
+  __I  uint32_t DevIntSt;            /* USB Device Interrupt Registers     */
+  __IO uint32_t DevIntEn;
+  __O  uint32_t DevIntClr;
+  __O  uint32_t DevIntSet;
+
+  __O  uint32_t CmdCode;             /* USB Device SIE Command Registers   */
+  __I  uint32_t CmdData;
+
+  __I  uint32_t RxData;              /* USB Device Transfer Registers      */
+  __O  uint32_t TxData;
+  __I  uint32_t RxPLen;
+  __O  uint32_t TxPLen;
+  __IO uint32_t Ctrl;
+  __O  uint32_t DevIntPri;
+
+  __I  uint32_t EpIntSt;             /* USB Device Endpoint Interrupt Regs */
+  __IO uint32_t EpIntEn;
+  __O  uint32_t EpIntClr;
+  __O  uint32_t EpIntSet;
+  __O  uint32_t EpIntPri;
+
+  __IO uint32_t ReEp;                /* USB Device Endpoint Realization Reg*/
+  __O  uint32_t EpInd;
+  __IO uint32_t MaxPSize;
+
+  __I  uint32_t DMARSt;              /* USB Device DMA Registers           */
+  __O  uint32_t DMARClr;
+  __O  uint32_t DMARSet;
+       uint32_t RESERVED2[9];
+  __IO uint32_t UDCAH;
+  __I  uint32_t EpDMASt;
+  __O  uint32_t EpDMAEn;
+  __O  uint32_t EpDMADis;
+  __I  uint32_t DMAIntSt;
+  __IO uint32_t DMAIntEn;
+       uint32_t RESERVED3[2];
+  __I  uint32_t EoTIntSt;
+  __O  uint32_t EoTIntClr;
+  __O  uint32_t EoTIntSet;
+  __I  uint32_t NDDRIntSt;
+  __O  uint32_t NDDRIntClr;
+  __O  uint32_t NDDRIntSet;
+  __I  uint32_t SysErrIntSt;
+  __O  uint32_t SysErrIntClr;
+  __O  uint32_t SysErrIntSet;
+       uint32_t RESERVED4[15];
+
+  union {
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
+  __O  uint32_t I2C_TX;
+  };
+  __IO  uint32_t I2C_STS;
+  __IO uint32_t I2C_CTL;
+  __IO uint32_t I2C_CLKHI;
+  __O  uint32_t I2C_CLKLO;
+       uint32_t RESERVED5[824];
+
+  union {
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
+  __IO uint32_t OTGClkCtrl;
+  };
+  union {
+  __I  uint32_t USBClkSt;
+  __I  uint32_t OTGClkSt;
+  };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+  __IO uint32_t MAC1;                   /* MAC Registers                      */
+  __IO uint32_t MAC2;
+  __IO uint32_t IPGT;
+  __IO uint32_t IPGR;
+  __IO uint32_t CLRT;
+  __IO uint32_t MAXF;
+  __IO uint32_t SUPP;
+  __IO uint32_t TEST;
+  __IO uint32_t MCFG;
+  __IO uint32_t MCMD;
+  __IO uint32_t MADR;
+  __O  uint32_t MWTD;
+  __I  uint32_t MRDD;
+  __I  uint32_t MIND;
+       uint32_t RESERVED0[2];
+  __IO uint32_t SA0;
+  __IO uint32_t SA1;
+  __IO uint32_t SA2;
+       uint32_t RESERVED1[45];
+  __IO uint32_t Command;                /* Control Registers                  */
+  __I  uint32_t Status;
+  __IO uint32_t RxDescriptor;
+  __IO uint32_t RxStatus;
+  __IO uint32_t RxDescriptorNumber;
+  __I  uint32_t RxProduceIndex;
+  __IO uint32_t RxConsumeIndex;
+  __IO uint32_t TxDescriptor;
+  __IO uint32_t TxStatus;
+  __IO uint32_t TxDescriptorNumber;
+  __IO uint32_t TxProduceIndex;
+  __I  uint32_t TxConsumeIndex;
+       uint32_t RESERVED2[10];
+  __I  uint32_t TSV0;
+  __I  uint32_t TSV1;
+  __I  uint32_t RSV;
+       uint32_t RESERVED3[3];
+  __IO uint32_t FlowControlCounter;
+  __I  uint32_t FlowControlStatus;
+       uint32_t RESERVED4[34];
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
+  __I  uint32_t RxFilterWoLStatus;
+  __O  uint32_t RxFilterWoLClear;
+       uint32_t RESERVED5;
+  __IO uint32_t HashFilterL;
+  __IO uint32_t HashFilterH;
+       uint32_t RESERVED6[882];
+  __I  uint32_t IntStatus;              /* Module Control Registers           */
+  __IO uint32_t IntEnable;
+  __O  uint32_t IntClear;
+  __O  uint32_t IntSet;
+       uint32_t RESERVED7;
+  __IO uint32_t PowerDown;
+       uint32_t RESERVED8;
+  __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+/*------------- LCD controller (LCD) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t TIMH;                   /* LCD Registers                      */
+  __IO uint32_t TIMV;
+  __IO uint32_t POL;
+  __IO uint32_t LE;
+  __IO uint32_t UPBASE;
+  __IO uint32_t LPBASE;
+  __IO uint32_t CTRL;
+  __IO uint32_t INTMSK;
+  __I  uint32_t INTRAW;
+  __I  uint32_t INTSTAT;
+  __O  uint32_t INTCLR;
+  __I  uint32_t UPCURR;
+  __I  uint32_t LPCURR;
+       uint32_t RESERVED0[115];
+  __IO uint32_t PAL[128];
+       uint32_t RESERVED1[256];
+  __IO uint32_t CRSR_IMG[256];
+  __IO uint32_t CRSR_CTRL;
+  __IO uint32_t CRSR_CFG;
+  __IO uint32_t CRSR_PAL0;
+  __IO uint32_t CRSR_PAL1;
+  __IO uint32_t CRSR_XY;
+  __IO uint32_t CRSR_CLIP;
+       uint32_t RESERVED2[2];
+  __IO uint32_t CRSR_INTMSK;
+  __O  uint32_t CRSR_INTCLR;
+  __I  uint32_t CRSR_INTRAW;
+  __I  uint32_t CRSR_INTSTAT;
+} LPC_LCD_TypeDef;
+
+/*------------- External Memory Controller (EMC) -----------------------------*/
+typedef struct
+{
+  __IO uint32_t Control;
+  __I  uint32_t Status;
+  __IO uint32_t Config;
+       uint32_t RESERVED0[5];
+  __IO uint32_t DynamicControl;
+  __IO uint32_t DynamicRefresh;
+  __IO uint32_t DynamicReadConfig;
+       uint32_t RESERVED1[1];
+  __IO uint32_t DynamicRP;
+  __IO uint32_t DynamicRAS;
+  __IO uint32_t DynamicSREX;
+  __IO uint32_t DynamicAPR;
+  __IO uint32_t DynamicDAL;
+  __IO uint32_t DynamicWR;
+  __IO uint32_t DynamicRC;
+  __IO uint32_t DynamicRFC;
+  __IO uint32_t DynamicXSR;
+  __IO uint32_t DynamicRRD;
+  __IO uint32_t DynamicMRD;
+       uint32_t RESERVED2[9];
+  __IO uint32_t StaticExtendedWait;
+       uint32_t RESERVED3[31];
+  __IO uint32_t DynamicConfig0;
+  __IO uint32_t DynamicRasCas0;
+       uint32_t RESERVED4[6];
+  __IO uint32_t DynamicConfig1;
+  __IO uint32_t DynamicRasCas1;
+       uint32_t RESERVED5[6];
+  __IO uint32_t DynamicConfig2;
+  __IO uint32_t DynamicRasCas2;
+       uint32_t RESERVED6[6];
+  __IO uint32_t DynamicConfig3;
+  __IO uint32_t DynamicRasCas3;
+       uint32_t RESERVED7[38];
+  __IO uint32_t StaticConfig0;
+  __IO uint32_t StaticWaitWen0;
+  __IO uint32_t StaticWaitOen0;
+  __IO uint32_t StaticWaitRd0;
+  __IO uint32_t StaticWaitPage0;
+  __IO uint32_t StaticWaitWr0;
+  __IO uint32_t StaticWaitTurn0;
+       uint32_t RESERVED8[1];
+  __IO uint32_t StaticConfig1;
+  __IO uint32_t StaticWaitWen1;
+  __IO uint32_t StaticWaitOen1;
+  __IO uint32_t StaticWaitRd1;
+  __IO uint32_t StaticWaitPage1;
+  __IO uint32_t StaticWaitWr1;
+  __IO uint32_t StaticWaitTurn1;
+       uint32_t RESERVED9[1];
+  __IO uint32_t StaticConfig2;
+  __IO uint32_t StaticWaitWen2;
+  __IO uint32_t StaticWaitOen2;
+  __IO uint32_t StaticWaitRd2;
+  __IO uint32_t StaticWaitPage2;
+  __IO uint32_t StaticWaitWr2;
+  __IO uint32_t StaticWaitTurn2;
+       uint32_t RESERVED10[1];
+  __IO uint32_t StaticConfig3;
+  __IO uint32_t StaticWaitWen3;
+  __IO uint32_t StaticWaitOen3;
+  __IO uint32_t StaticWaitRd3;
+  __IO uint32_t StaticWaitPage3;
+  __IO uint32_t StaticWaitWr3;
+  __IO uint32_t StaticWaitTurn3;
+} LPC_EMC_TypeDef;
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t MODE;
+  __IO uint32_t SEED;
+  union {
+  __I  uint32_t SUM;
+  __O  uint32_t WR_DATA_DWORD;
+  __O  uint16_t WR_DATA_WORD;
+       uint16_t RESERVED_WORD;
+  __O  uint8_t WR_DATA_BYTE;
+       uint8_t RESERVED_BYTE[3];
+  };
+} LPC_CRC_TypeDef;
+
+/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
+typedef struct
+{
+  __IO uint32_t CMD;			/* 0x0080 */
+  __IO uint32_t ADDR;
+  __IO uint32_t WDATA;
+  __IO uint32_t RDATA;
+  __IO uint32_t WSTATE;			/* 0x0090 */
+  __IO uint32_t CLKDIV;
+  __IO uint32_t PWRDWN;			/* 0x0098 */
+       uint32_t RESERVED0[975];
+  __IO uint32_t INT_CLR_ENABLE;	/* 0x0FD8 */
+  __IO uint32_t INT_SET_ENABLE;
+  __IO uint32_t INT_STATUS;		/* 0x0FE0 */
+  __IO uint32_t INT_ENABLE;
+  __IO uint32_t INT_CLR_STATUS;
+  __IO uint32_t INT_SET_STATUS;
+} LPC_EEPROM_TypeDef;
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+#define LPC_FLASH_BASE        (0x00000000UL)
+#define LPC_RAM_BASE          (0x10000000UL)
+#define LPC_PERI_RAM_BASE     (0x20000000UL)
+#define LPC_APB0_BASE         (0x40000000UL)
+#define LPC_APB1_BASE         (0x40080000UL)
+#define LPC_AHBRAM1_BASE      (0x20004000UL)
+#define LPC_AHB_BASE          (0x20080000UL)
+#define LPC_CM3_BASE          (0xE0000000UL)
+
+/* APB0 peripherals                                                           */
+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM0_BASE         (LPC_APB0_BASE + 0x14000)
+#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
+#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
+#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals                                                           */
+#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
+#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)
+#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
+#define LPC_SSP2_BASE         (LPC_APB1_BASE + 0x2C000)
+#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
+#define LPC_MCI_BASE          (LPC_APB1_BASE + 0x40000)
+#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals                                                            */
+#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x00000)
+#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x00100)
+#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x00120)
+#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x00140)
+#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x00160)
+#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x00180)
+#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x001A0)
+#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x001C0)
+#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x001E0)
+#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x04000)
+#define LPC_LCD_BASE          (LPC_AHB_BASE  + 0x08000)
+#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
+#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x10000)
+#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x18000)
+#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x18020)
+#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x18040)
+#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x18060)
+#define LPC_GPIO4_BASE        (LPC_AHB_BASE  + 0x18080)
+#define LPC_GPIO5_BASE        (LPC_AHB_BASE  + 0x180A0)
+#define LPC_EMC_BASE          (LPC_AHB_BASE  + 0x1C000)
+
+#define LPC_EEPROM_BASE       (LPC_FLASH_BASE+ 0x200080)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
+#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
+#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
+#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
+#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
+#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
+#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
+#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
+#define LPC_UART4             ((LPC_UART4_TypeDef     *) LPC_UART4_BASE    )
+#define LPC_PWM0              ((LPC_PWM_TypeDef       *) LPC_PWM0_BASE     )
+#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
+#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
+#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
+#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
+#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
+#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
+#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
+#define LPC_IOCON             ((LPC_IOCON_TypeDef     *) LPC_IOCON_BASE    )
+#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
+#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
+#define LPC_SSP2              ((LPC_SSP_TypeDef       *) LPC_SSP2_BASE     )
+#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
+#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
+#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
+#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
+#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
+#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
+#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
+#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
+#define LPC_MCI               ((LPC_MCI_TypeDef       *) LPC_MCI_BASE      )
+#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
+#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
+#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
+#define LPC_LCD               ((LPC_LCD_TypeDef       *) LPC_LCD_BASE      )
+#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
+#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
+#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
+#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
+#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
+#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
+#define LPC_GPIO5             ((LPC_GPIO_TypeDef      *) LPC_GPIO5_BASE    )
+#define LPC_EMC               ((LPC_EMC_TypeDef       *) LPC_EMC_BASE      )
+#define LPC_CRC               ((LPC_CRC_TypeDef       *) LPC_CRC_BASE      )
+#define LPC_EEPROM            ((LPC_EEPROM_TypeDef    *) LPC_EEPROM_BASE   )
+
+#endif  // __LPC177x_8x_H__

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x00000000;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000140;
+define symbol __ICFEDIT_region_RAM_end__   = 0x1000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define symbol _AHB_RAM_start__  = 0x20080000;
+define symbol _AHB_RAM_end__    = 0x200BFFFF;
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
+place in RAM_region     { readonly };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };
+place in AHB_RAM_region { section USB_RAM };

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf

@@ -0,0 +1,35 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x1000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define symbol _AHB_RAM_start__  = 0x20080000;
+define symbol _AHB_RAM_end__    = 0x200BFFFF;
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
+place at address mem:0x2FC { section CRPKEY };
+place in ROM_region     { readonly };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };
+place in AHB_RAM_region { section USB_RAM };

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s

@@ -0,0 +1,301 @@
+;/*****************************************************************************
+; * @file:    startup_LPC177x_8x.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; *           for the NXP LPC177x_8x Device Series 
+; * @version: V1.20
+; * @date:    07. October 2010
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
+                DCD     TIMER0_IRQHandler         ; 17: Timer0
+                DCD     TIMER1_IRQHandler         ; 18: Timer1
+                DCD     TIMER2_IRQHandler         ; 19: Timer2
+                DCD     TIMER3_IRQHandler         ; 20: Timer3
+                DCD     UART0_IRQHandler          ; 21: UART0
+                DCD     UART1_IRQHandler          ; 22: UART1
+                DCD     UART2_IRQHandler          ; 23: UART2
+                DCD     UART3_IRQHandler          ; 24: UART3
+                DCD     PWM1_IRQHandler           ; 25: PWM1
+                DCD     I2C0_IRQHandler           ; 26: I2C0
+                DCD     I2C1_IRQHandler           ; 27: I2C1
+                DCD     I2C2_IRQHandler           ; 28: I2C2
+                DCD     SPIFI_IRQHandler          ; 29: SPIFI
+                DCD     SSP0_IRQHandler           ; 30: SSP0
+                DCD     SSP1_IRQHandler           ; 31: SSP1
+                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
+                DCD     RTC_IRQHandler            ; 33: Real Time Clock
+                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
+                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
+                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
+                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
+                DCD     ADC_IRQHandler            ; 38: A/D Converter
+                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
+                DCD     USB_IRQHandler            ; 40: USB
+                DCD     CAN_IRQHandler            ; 41: CAN
+                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
+                DCD     I2S_IRQHandler            ; 43: I2S
+                DCD     ENET_IRQHandler           ; 44: Ethernet
+                DCD     MCI_IRQHandler            ; 45: SD/MMC card I/F
+                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
+                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
+                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
+				DCD		USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
+				DCD		CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup
+				DCD		UART4_IRQHandler          ; 51: UART4
+				DCD		SSP2_IRQHandler           ; 52: SSP2
+				DCD		LCD_IRQHandler            ; 53: LCD
+				DCD		GPIO_IRQHandler           ; 54: GPIO
+				DCD		PWM0_IRQHandler           ; 55: PWM0
+				DCD		EEPROM_IRQHandler         ; 56: EEPROM
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+				IMPORT  SystemInit
+                IMPORT  __main
+				LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  TIMER0_IRQHandler         [WEAK]
+                EXPORT  TIMER1_IRQHandler         [WEAK]
+                EXPORT  TIMER2_IRQHandler         [WEAK]
+                EXPORT  TIMER3_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  PWM1_IRQHandler           [WEAK]
+                EXPORT  I2C0_IRQHandler           [WEAK]
+                EXPORT  I2C1_IRQHandler           [WEAK]
+                EXPORT  I2C2_IRQHandler           [WEAK]
+                EXPORT  SPIFI_IRQHandler          [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  PLL0_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  EINT0_IRQHandler          [WEAK]
+                EXPORT  EINT1_IRQHandler          [WEAK]
+                EXPORT  EINT2_IRQHandler          [WEAK]
+                EXPORT  EINT3_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  I2S_IRQHandler            [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  MCI_IRQHandler            [WEAK]
+                EXPORT  MCPWM_IRQHandler          [WEAK]
+                EXPORT  QEI_IRQHandler            [WEAK]
+                EXPORT  PLL1_IRQHandler           [WEAK]
+				EXPORT  USBActivity_IRQHandler    [WEAK]
+				EXPORT  CANActivity_IRQHandler    [WEAK]
+				EXPORT  UART4_IRQHandler          [WEAK]
+				EXPORT  SSP2_IRQHandler           [WEAK]
+				EXPORT  LCD_IRQHandler            [WEAK]
+				EXPORT  GPIO_IRQHandler           [WEAK]
+				EXPORT  PWM0_IRQHandler           [WEAK]
+				EXPORT  EEPROM_IRQHandler         [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPIFI_IRQHandler            
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+MCI_IRQHandler          
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+USBActivity_IRQHandler
+CANActivity_IRQHandler
+UART4_IRQHandler
+SSP2_IRQHandler
+LCD_IRQHandler
+GPIO_IRQHandler
+PWM0_IRQHandler
+EEPROM_IRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s

@@ -0,0 +1,275 @@
+/*****************************************************************************/
+/* startup_LPC17xx.s: Startup file for LPC17xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
+*/
+
+
+/*
+// <h> Stack Configuration
+//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+    .equ    Heap_Size,  0x00001000
+
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
+    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
+    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
+    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
+    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
+    .long   UART0_IRQHandler            /* 21: UART0                        */
+    .long   UART1_IRQHandler            /* 22: UART1                        */
+    .long   UART2_IRQHandler            /* 23: UART2                        */
+    .long   UART3_IRQHandler            /* 24: UART3                        */
+    .long   PWM1_IRQHandler             /* 25: PWM1                         */
+    .long   I2C0_IRQHandler             /* 26: I2C0                         */
+    .long   I2C1_IRQHandler             /* 27: I2C1                         */
+    .long   I2C2_IRQHandler             /* 28: I2C2                         */
+    .long   SPIFI_IRQHandler            /* 29: SPIFI	                    */
+    .long   SSP0_IRQHandler             /* 30: SSP0                         */
+    .long   SSP1_IRQHandler             /* 31: SSP1                         */
+    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
+    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
+    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
+    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
+    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
+    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
+    .long   ADC_IRQHandler              /* 38: A/D Converter                */
+    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
+    .long   USB_IRQHandler              /* 40: USB                          */
+    .long   CAN_IRQHandler              /* 41: CAN                          */
+    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
+    .long   I2S_IRQHandler              /* 43: I2S                          */
+    .long   ENET_IRQHandler             /* 44: Ethernet                     */
+    .long   MCI_IRQHandler              /* 45: SD/MMC Card					*/
+    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
+    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
+    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
+    .long	USBActivity_IRQHandler		/* 49: USB Activity 				*/
+    .long 	CANActivity_IRQHandler		/* 50: CAN Activity					*/
+    .long	UART4_IRQHandler            /* 51: UART4						*/
+    .long	SSP2_IRQHandler				/* 52: SSP2							*/
+    .long 	LCD_IRQHandler				/* 53: LCD							*/
+    .long	GPIO_IRQHandler				/* 54: GPIO							*/
+    .long 	PWM0_IRQHandler				/* 55: PWM0							*/
+    .long 	EEPROM_IRQHandler			/* 56: EEPROM						*/
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+.if (RAM_MODE)
+/* Clear .bss section (Zero init) */
+	MOV     R0, #0
+	LDR     R1, =__bss_start__
+	LDR     R2, =__bss_end__
+	CMP     R1,R2
+	BEQ     BSSIsEmpty
+LoopZI:
+	CMP     R1, R2
+	BHS		BSSIsEmpty
+	STR   	R0, [R1]
+	ADD		R1, #4
+	BLO     LoopZI
+BSSIsEmpty:
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=main
+    BX      R0
+.else
+    LDR     R0, =SystemInit
+    BLX     R0
+	LDR     R0,=_start
+    BX      R0
+.endif
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     WDT_IRQHandler
+    IRQ     TIMER0_IRQHandler
+    IRQ     TIMER1_IRQHandler
+    IRQ     TIMER2_IRQHandler
+    IRQ     TIMER3_IRQHandler
+    IRQ     UART0_IRQHandler
+    IRQ     UART1_IRQHandler
+    IRQ     UART2_IRQHandler
+    IRQ     UART3_IRQHandler
+    IRQ     PWM1_IRQHandler
+    IRQ     I2C0_IRQHandler
+    IRQ     I2C1_IRQHandler
+    IRQ     I2C2_IRQHandler
+    IRQ		SPIFI_IRQHandler
+    IRQ     SSP0_IRQHandler
+    IRQ     SSP1_IRQHandler
+    IRQ     PLL0_IRQHandler
+    IRQ     RTC_IRQHandler
+    IRQ     EINT0_IRQHandler
+    IRQ     EINT1_IRQHandler
+    IRQ     EINT2_IRQHandler
+    IRQ     EINT3_IRQHandler
+    IRQ     ADC_IRQHandler
+    IRQ     BOD_IRQHandler
+    IRQ     USB_IRQHandler
+    IRQ     CAN_IRQHandler
+    IRQ     DMA_IRQHandler
+    IRQ     I2S_IRQHandler
+    IRQ     ENET_IRQHandler
+    IRQ     MCI_IRQHandler
+    IRQ     MCPWM_IRQHandler
+    IRQ     QEI_IRQHandler
+    IRQ     PLL1_IRQHandler
+    IRQ		USBActivity_IRQHandler
+    IRQ		CANActivity_IRQHandler
+	IRQ		UART4_IRQHandler
+	IRQ		SSP2_IRQHandler
+	IRQ		LCD_IRQHandler
+	IRQ		GPIO_IRQHandler
+	IRQ		PWM0_IRQHandler
+	IRQ		EEPROM_IRQHandler
+
+    .end

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s

@@ -0,0 +1,393 @@
+;/*****************************************************************************
+; * @file:    startup_LPC177x_8x.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; *           for the NXP LPC17xx Device Series
+; * @version: V1.03
+; * @date:    09. February 2010
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
+        DCD     TIMER0_IRQHandler         ; 17: Timer0
+        DCD     TIMER1_IRQHandler         ; 18: Timer1
+        DCD     TIMER2_IRQHandler         ; 19: Timer2
+        DCD     TIMER3_IRQHandler         ; 20: Timer3
+        DCD     UART0_IRQHandler          ; 21: UART0
+        DCD     UART1_IRQHandler          ; 22: UART1
+        DCD     UART2_IRQHandler          ; 23: UART2
+        DCD     UART3_IRQHandler          ; 24: UART3
+        DCD     PWM1_IRQHandler           ; 25: PWM1
+        DCD     I2C0_IRQHandler           ; 26: I2C0
+        DCD     I2C1_IRQHandler           ; 27: I2C1
+        DCD     I2C2_IRQHandler           ; 28: I2C2
+        DCD     SPIFI_IRQHandler          ; 29: SPIFI
+        DCD     SSP0_IRQHandler           ; 30: SSP0
+        DCD     SSP1_IRQHandler           ; 31: SSP1
+        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
+        DCD     RTC_IRQHandler            ; 33: Real Time Clock
+        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
+        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
+        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
+        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
+        DCD     ADC_IRQHandler            ; 38: A/D Converter
+        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
+        DCD     USB_IRQHandler            ; 40: USB
+        DCD     CAN_IRQHandler            ; 41: CAN
+        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
+        DCD     I2S_IRQHandler            ; 43: I2S
+        DCD     ENET_IRQHandler           ; 44: Ethernet
+        DCD		MCI_IRQHandler		  	  ; 45: MCI Card
+        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
+		DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
+		DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
+	    DCD		USBActivity_IRQHandler	  ; 49: USB Activity Interrupt
+	    DCD		CANActivity_IRQHandler	  ; 50: CAN Activity Interrupt
+		DCD		UART4_IRQHandler          ; 51: UART4
+		DCD		SSP2_IRQHandler		      ; 52: SSP2
+		DCD		LCD_IRQHandler		  	  ; 53: LCD
+		DCD		GPIO_IRQHandler		  	  ; 54: GPIO
+		DCD		PWM0_IRQHandler		  	  ; 55: PWM0
+		DCD		EEPROM_IRQHandler	  	  ; 56: EEPROM
+
+
+
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+
+        PUBWEAK TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+        B TIMER0_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+
+        PUBWEAK TIMER3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+        B TIMER3_IRQHandler
+
+        PUBWEAK UART0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+        B UART0_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK PWM1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PWM1_IRQHandler
+        B PWM1_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPIFI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPIFI_IRQHandler
+        B SPIFI_IRQHandler
+
+        PUBWEAK SSP0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+        B SSP0_IRQHandler
+
+        PUBWEAK SSP1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+        B SSP1_IRQHandler
+
+        PUBWEAK PLL0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PLL0_IRQHandler
+        B PLL0_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK EINT0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT0_IRQHandler
+        B EINT0_IRQHandler
+
+        PUBWEAK EINT1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT1_IRQHandler
+        B EINT1_IRQHandler
+
+        PUBWEAK EINT2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT2_IRQHandler
+        B EINT2_IRQHandler
+
+        PUBWEAK EINT3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT3_IRQHandler
+        B EINT3_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK BOD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+BOD_IRQHandler
+        B BOD_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK CAN_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+        B CAN_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK I2S_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S_IRQHandler
+        B I2S_IRQHandler
+
+        PUBWEAK ENET_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+        B ENET_IRQHandler
+
+        PUBWEAK MCI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+MCI_IRQHandler
+        B MCI_IRQHandler
+
+        PUBWEAK MCPWM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+        B MCPWM_IRQHandler
+
+        PUBWEAK QEI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+        B QEI_IRQHandler
+
+        PUBWEAK PLL1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PLL1_IRQHandler
+        B PLL1_IRQHandler
+
+        PUBWEAK USBActivity_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBActivity_IRQHandler
+        B USBActivity_IRQHandler
+
+        PUBWEAK CANActivity_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CANActivity_IRQHandler
+        B CANActivity_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK SSP2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP2_IRQHandler
+        B SSP2_IRQHandler
+
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK GPIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO_IRQHandler
+        B GPIO_IRQHandler
+
+        PUBWEAK PWM0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PWM0_IRQHandler
+        B PWM0_IRQHandler
+
+		PUBWEAK EEPROM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EEPROM_IRQHandler
+        B EEPROM_IRQHandler
+
+        END

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c

@@ -0,0 +1,466 @@
+/**********************************************************************
+* $Id: system_LPC177x_8x.c 7485 2011-06-03 07:57:16Z sgg06786 $		system_LPC177x_8x.c			2011-06-02
+*//**
+* @file		system_LPC177x_8x.c
+* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+*          	for the NXP LPC177x_8x Device Series
+*
+*			ARM Limited (ARM) is supplying this software for use with 
+*			Cortex-M processor based microcontrollers.  This file can be 
+*			freely distributed within development tools that are supporting 
+*			such ARM based processors.
+*
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#include <stdint.h>
+#include "LPC177x_8x.h"
+#include "system_LPC177x_8x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Controls and Status Register (SCS)
+//     <o1.0>       EMC_SHIFT: EMC Shift enable
+//                     <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
+//                     <1=> Static CS addresses start at LSB 0 regardless of memory width
+//     <o1.1>       EMC_RESET: EMC Reset disable
+//                     <0=> EMC will be reset by any chip reset
+//                     <1=> Portions of EMC will only be reset by POR or BOR
+//     <o1.2>       EMC_BURST: EMC Burst disable
+//     <o1.3>       MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
+//                     <0=> SD_PWR is active low
+//                     <1=> SD_PWR is active high
+//     <o1.4>       OSCRANGE: Main Oscillator Range Select
+//                     <0=>  1 MHz to 20 MHz
+//                     <1=> 15 MHz to 25 MHz
+//     <o1.5>       OSCEN: Main Oscillator enable
+//   </h>
+//
+//   <h> Clock Source Select Register (CLKSRCSEL)
+//     <o2.0>       CLKSRC: sysclk and PLL0 clock source selection
+//                     <0=> Internal RC oscillator
+//                     <1=> Main oscillator
+//   </h>
+//
+//   <e3> PLL0 Configuration (Main PLL)
+//     <h> PLL0 Configuration Register (PLL0CFG)
+//                     <i> PLL out clock = (F_cco / (2 * P))
+//                     <i> F_cco = (F_in * M * 2 * P)
+//                     <i> F_in  must be in the range of 1 MHz to 25 MHz
+//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+//       <o4.0..4>   MSEL: PLL Multiplier Selection
+//                     <i> M Value
+//                     <1-32><#-1>
+//       <o4.5..6> PSEL: PLL Divider Selection
+//                     <i> P Value
+//                     <0=> 1
+//                     <1=> 2
+//                     <2=> 4
+//                     <3=> 8
+//     </h>
+//   </e>
+//
+//   <e5> PLL1 Configuration (Alt PLL)
+//     <h> PLL1 Configuration Register (PLL1CFG)
+//                     <i> PLL out clock = (F_cco / (2 * P))
+//                     <i> F_cco = (F_in * M * 2 * P)
+//                     <i> F_in  must be in the range of 1 MHz to 25 MHz
+//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+//       <o6.0..4>   MSEL: PLL Multiplier Selection
+//                     <i> M Value
+//                     <1-32><#-1>
+//       <o6.5..6> PSEL: PLL Divider Selection
+//                     <i> P Value
+//                     <0=> 1
+//                     <1=> 2
+//                     <2=> 4
+//                     <3=> 8
+//     </h>
+//   </e>
+//
+//   <h> CPU Clock Selection Register (CCLKSEL)
+//     <o7.0..4>    CCLKDIV: CPU clock (CCLK) divider
+//                     <i> 0: The divider is turned off. No clock will be provided to the CPU
+//                     <i> n: The input clock is divided by n to produce the CPU clock
+//                     <0-31>
+//     <o7.8>       CCLKSEL: CPU clock divider input clock selection
+//                     <0=> sysclk clock
+//                     <1=> PLL0 clock
+//   </h>
+//
+//   <h> USB Clock Selection Register (USBCLKSEL)
+//     <o8.0..4>    USBDIV: USB clock (source PLL0) divider selection
+//                     <0=> USB clock off
+//                     <4=> PLL0 / 4 (PLL0 must be 192Mhz)
+//                     <6=> PLL0 / 6 (PLL0 must be 288Mhz)
+//     <o8.8..9>    USBSEL: USB clock divider input clock selection
+//                     <i> When CPU clock is selected, the USB can be accessed
+//                     <i> by software but cannot perform USB functions
+//                     <0=> CPU clock
+//                     <1=> PLL0 clock
+//                     <2=> PLL1 clock
+//   </h>
+//
+//   <h> EMC Clock Selection Register (EMCCLKSEL)
+//     <o9.0>       EMCDIV: EMC clock selection
+//                     <0=> CPU clock
+//                     <1=> CPU clock / 2
+//   </h>
+//
+//   <h> Peripheral Clock Selection Register (PCLKSEL)
+//     <o10.0..4>   PCLKDIV: APB Peripheral clock divider
+//                     <i> 0: The divider is turned off. No clock will be provided to APB peripherals
+//                     <i> n: The input clock is divided by n to produce the APB peripheral clock
+//                     <0-31>
+//   </h>
+//
+//   <h> Power Control for Peripherals Register (PCONP)
+//     <o11.0>      PCLCD: LCD controller power/clock enable
+//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
+//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
+//     <o11.3>      PCUART0: UART 0 power/clock enable
+//     <o11.4>      PCUART1: UART 1 power/clock enable
+//     <o11.5>      PCPWM0: PWM0 power/clock enable
+//     <o11.6>      PCPWM1: PWM1 power/clock enable
+//     <o11.7>      PCI2C0: I2C 0 interface power/clock enable
+//     <o11.8>      PCUART4: UART 4 power/clock enable
+//     <o11.9>      PCRTC: RTC and Event Recorder power/clock enable
+//     <o11.10>     PCSSP1: SSP 1 interface power/clock enable
+//     <o11.11>     PCEMC: External Memory Controller power/clock enable
+//     <o11.12>     PCADC: A/D converter power/clock enable
+//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
+//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
+//     <o11.15>     PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
+//     <o11.17>     PCMCPWM: Motor Control PWM power/clock enable
+//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
+//     <o11.19>     PCI2C1: I2C 1 interface power/clock enable
+//     <o11.20>     PCSSP2: SSP 2 interface power/clock enable
+//     <o11.21>     PCSSP0: SSP 0 interface power/clock enable
+//     <o11.22>     PCTIM2: Timer 2 power/clock enable
+//     <o11.23>     PCTIM3: Timer 3 power/clock enable
+//     <o11.24>     PCUART2: UART 2 power/clock enable
+//     <o11.25>     PCUART3: UART 3 power/clock enable
+//     <o11.26>     PCI2C2: I2C 2 interface power/clock enable
+//     <o11.27>     PCI2S: I2S interface power/clock enable
+//     <o11.28>     PCSDC: SD Card interface power/clock enable
+//     <o11.29>     PCGPDMA: GPDMA function power/clock enable
+//     <o11.30>     PCENET: Ethernet block power/clock enable
+//     <o11.31>     PCUSB: USB interface power/clock enable
+//   </h>
+//
+//   <h> Clock Output Configuration Register (CLKOUTCFG)
+//     <o12.0..3>   CLKOUTSEL: Clock Source for CLKOUT Selection
+//                     <0=> CPU clock
+//                     <1=> Main Oscillator
+//                     <2=> Internal RC Oscillator
+//                     <3=> USB clock
+//                     <4=> RTC Oscillator
+//                     <5=> unused
+//                     <6=> Watchdog Oscillator
+//     <o12.4..7>   CLKOUTDIV: Output Clock Divider
+//                     <1-16><#-1>
+//     <o12.8>      CLKOUT_EN: CLKOUT enable
+//   </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP           1
+#define SCS_Val               0x00000021
+#define CLKSRCSEL_Val         0x00000001
+#define PLL0_SETUP            1
+#define PLL0CFG_Val           0x00000009
+#define PLL1_SETUP            1
+#define PLL1CFG_Val           0x00000023
+#define CCLKSEL_Val           (0x00000001|(1<<8))
+#define USBCLK_SETUP		  1
+#define USBCLKSEL_Val         (0x00000001|(0x02<<8))
+#define EMCCLKSEL_Val         0x00000001
+#define PCLKSEL_Val           0x00000002
+#define PCONP_Val             0x042887DE
+#define CLKOUTCFG_Val         0x00000100
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+//   <o1.12..15> FLASHTIM: Flash Access Time
+//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+//               <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP           1
+#define FLASHCFG_Val          0x00005000
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
+   #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
+   #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
+   #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
+   #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
+   #error "CCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
+   #error "USBCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
+   #error "EMCCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
+   #error "PCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
+   #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+   #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+   #warning "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+/* pll_out_clk = F_cco / (2 × P)
+   F_cco = pll_in_clk × M × 2 × P */
+#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
+#define __PLL0_CLK(__F_IN)    (__F_IN * __M)
+#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
+#define __PCLK_DIV			  (PCLKSEL_Val & 0x1F)
+#define __ECLK_DIV			  ((EMCCLKSEL_Val & 0x01) + 1)
+
+/* Determine core clock frequency according to settings */
+#if (CLOCK_SETUP)                       /* Clock Setup                        */
+
+  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
+   #error "Main Oscillator is selected as clock source but is not enabled!"
+  #endif
+
+  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
+   #error "Main PLL is selected as clock source but is not enabled!"
+  #endif
+
+  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
+    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
+        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+		#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
+        #define __EMC_CLK  (IRC_OSC/  __ECLK_DIV)
+    #else                               /* sysclk = osc_clk */
+        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
+        #define __EMC_CLK  (OSC_CLK/  __ECLK_DIV)
+    #endif
+  #else                                 /* cclk = pll_clk */
+    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
+        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
+        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
+        #define __EMC_CLK  (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
+    #else                               /* sysclk = osc_clk */
+        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
+        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
+		#define __EMC_CLK  (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
+    #endif
+  #endif
+
+#else
+        #define __CORE_CLK (IRC_OSC)
+        #define __PER_CLK  (IRC_OSC)
+        #define __EMC_CLK  (IRC_OSC)
+#endif
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
+uint32_t EMCClock		 = __EMC_CLK; /*!< EMC Clock Frequency 				  */
+uint32_t USBClock 		 = (48000000UL);		  /*!< USB Clock Frequency - this value will
+									be updated after call SystemCoreClockUpdate, should be 48MHz*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  /* Determine clock frequency according to clock register values             */
+  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
+    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
+          SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));
+          PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));
+          EMCClock        = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+    }
+    else {                                        /* sysclk = osc_clk */
+      if ((LPC_SC->SCS & 0x40) == 0) {
+          SystemCoreClock = 0;                      /* this should never happen! */
+          PeripheralClock = 0;
+          EMCClock        = 0;
+      }
+      else {
+          SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));
+          PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));
+          EMCClock        = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+      }
+    }
+  }
+  else {                                          /* cclk = pll_clk */
+    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
+          SystemCoreClock = 0;                      /* this should never happen! */
+          PeripheralClock = 0;
+          EMCClock 		  = 0;
+    }
+    else {
+      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
+          SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+          PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+          EMCClock        = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+      }
+      else {                                        /* sysclk = osc_clk */
+        if ((LPC_SC->SCS & 0x40) == 0) {
+          SystemCoreClock = 0;                      /* this should never happen! */
+          PeripheralClock = 0;
+          EMCClock 		  = 0;
+        }
+        else {
+          SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+          PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+          EMCClock        = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+        }
+      }
+    }
+  }
+  /* ---update USBClock------------------*/
+  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
+  {
+	  switch (LPC_SC->USBCLKSEL & 0x1F)
+	  {
+	  case 0:
+		  USBClock = 0; //no clock will be provided to the USB subsystem
+		  break;
+	  case 4:
+	  case 6:
+		  if(LPC_SC->CLKSRCSEL & 0x01)	//pll_clk_in = main_osc
+			  USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+		  else //pll_clk_in = irc_clk
+			  USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+		  break;
+	  default:
+		  USBClock = 0;  /* this should never happen! */
+	  }
+  }
+  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
+  {
+	  if(LPC_SC->CLKSRCSEL & 0x01)	//pll1_clk_in = main_osc
+	  		USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
+	  else //pll1_clk_in = irc_clk
+	  		USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
+  }
+  else
+	  USBClock = 0; /* this should never happen! */
+}
+
+  /* Determine clock frequency according to clock register values             */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP)                       /* Clock Setup                        */
+  LPC_SC->SCS       = SCS_Val;
+  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
+    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
+  }
+
+  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
+
+#if (PLL0_SETUP)
+  LPC_SC->PLL0CFG   = PLL0CFG_Val;
+  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
+#endif
+
+#if (PLL1_SETUP)
+  LPC_SC->PLL1CFG   = PLL1CFG_Val;
+  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
+#endif
+
+  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
+  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
+  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
+  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
+  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
+  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
+#endif
+
+#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
+  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
+#endif
+#ifdef  __RAM_MODE__
+  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
+#else
+  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
+#endif
+}

bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.h

@@ -0,0 +1,83 @@
+/**********************************************************************
+* $Id: system_LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $		system_LPC177x_8x.h			2011-06-02
+*//**
+* @file		system_LPC177x_8x.h
+* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+*			for the NXP LPC177x_8x Device Series
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __SYSTEM_LPC177x_8x_H
+#define __SYSTEM_LPC177x_8x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;      /*!< System Clock Frequency (Core Clock)  	*/
+extern uint32_t PeripheralClock;	    /*!< Peripheral Clock Frequency (Pclk) 	    */
+extern uint32_t EMCClock;			        /*!< EMC Clock                              */
+extern uint32_t USBClock;			        /*!< USB Frequency 						              */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL        (12000000UL)        /* Oscillator frequency               */
+#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
+#define IRC_OSC     (12000000UL)        /* Internal RC oscillator frequency   */
+#define WDT_OSC		  (  500000UL)		/* Internal WDT oscillator frequency  */
+
+
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC177x_8x_H */

bsp/lpc178x/CMSIS/SConscript

@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+src = ['CM3/CoreSupport/core_cm3.c', 'CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c']
+CPPPATH = [cwd + '/CM3/CoreSupport', cwd + '/CM3/DeviceSupport/NXP/LPC177x_8x/']
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/lpc178x/SConscript

@@ -0,0 +1,19 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+src_bsp   = ['application.c', 'startup.c', 'board.c']
+src_drv   = ['uart.c', 'led.c']
+
+if GetDepend('RT_USING_DFS'):
+    src_drv += ['sd.c', 'spi.c']
+
+if GetDepend('RT_USING_LWIP'):
+    src_drv += ['emac.c']
+
+src = File(src_bsp + src_drv)
+CPPPATH = [ GetCurrentDir() ]
+CPPDEFINES = []
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/lpc178x/SConstruct

@@ -0,0 +1,44 @@
+import os
+import sys
+import rtconfig
+
+RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-lpc178x.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+if GetDepend('RT_USING_WEBSERVER'):
+    objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
+
+if GetDepend('RT_USING_RTGUI'):
+    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+# libc testsuite 
+# objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
+
+# build program 
+env.Program(TARGET, objs)
+
+# end building 
+EndBuilding(TARGET)

bsp/lpc178x/application.c

@@ -0,0 +1,112 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-03-04     Magicoe      for LPC1766 version
+ * 2010-05-02     Aozima       add led function
+ * 2010-05-24     Bernard      add filesystem initialization and move led function to led.c
+ */
+
+/**
+ * @addtogroup LPC17
+ */
+/*@{*/
+
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+/* dfs init */
+#include <dfs_init.h>
+/* dfs filesystem:ELM FatFs filesystem init */
+#include <dfs_elm.h>
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#include <lwip/api.h>
+#include <netif/ethernetif.h>
+#endif
+
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
+{
+    unsigned int count=0;
+
+    while (1)
+    {
+        /* led1 on */
+        rt_kprintf("on count : %d\r\n",count);
+        count++;
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+
+        /* led1 off */
+        rt_kprintf("led off\r\n");
+        rt_thread_delay( RT_TICK_PER_SECOND/2 );
+    }
+
+    /* Filesystem Initialization */
+#ifdef RT_USING_DFS
+    {
+        /* init the device filesystem */
+        dfs_init();
+
+        /* init the elm FAT filesystam*/
+        elm_init();
+
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+            rt_kprintf("File System initialized!\n");
+        else
+            rt_kprintf("File System init failed!\n");
+    }
+#endif
+
+    /* LwIP Initialization */
+#ifdef RT_USING_LWIP
+    {
+        extern void lwip_sys_init(void);
+        extern void lpc17xx_emac_hw_init(void);
+
+        eth_system_device_init();
+
+        /* register ethernetif device */
+        lpc17xx_emac_hw_init();
+        /* init all device */
+        rt_device_init_all();
+
+        /* init lwip system */
+        lwip_sys_init();
+        rt_kprintf("TCP/IP initialized!\n");
+    }
+#endif
+}
+
+int rt_application_init()
+{
+    rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 8, 20);
+#else
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 80, 20);
+#endif
+    if (init_thread != RT_NULL) rt_thread_startup(init_thread);
+
+    return 0;
+}
+
+/*@}*/

bsp/lpc178x/drivers/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/lpc178x/drivers/board.c

@@ -0,0 +1,77 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2010-02-04     Magicoe      ported to LPC17xx
+ * 2010-05-02     Aozima       update CMSIS to 130
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "uart.h"
+#include "board.h"
+#include "LPC177x_8x.h"
+#include "system_LPC177x_8x.h"
+
+/**
+ * @addtogroup LPC17xx
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+void SysTick_Handler(void)
+{
+    rt_hw_timer_handler();
+}
+
+/**
+ * This function will initial LPC17xx board.
+ */
+void rt_hw_board_init()
+{
+	/* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+	/* Set the Vector Table base location at 0x10000000 */
+	SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+	/* Set the Vector Table base location at 0x00000000 */
+	SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+#endif
+
+	/* init systick */
+	SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND - 1);
+	/* set pend exception priority */
+	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+
+	rt_hw_uart_init();
+	rt_console_set_device( CONSOLE_DEVICE );
+
+    rt_kprintf("\r\n\r\nSystemInit......\r\n");
+}
+
+/*@}*/

bsp/lpc178x/drivers/board.h

@@ -0,0 +1,29 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+/* RT_USING_UART */
+#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_USING_UART0
+#define RT_USING_UART1
+
+#define CONSOLE_DEVICE      "uart1"
+#define FINSH_DEVICE_NAME   "uart1"
+
+void rt_hw_board_init(void);
+
+#endif

bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c

@@ -0,0 +1,301 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_clkpwr.c			2011-06-02
+*//**
+* @file		lpc177x_8x_clkpwr.c
+* @brief	Contains all functions support for Clock and Power Control
+*			firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CLKPWR
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_clkpwr.h"
+
+
+uint32_t USBFrequency = 0;
+uint32_t SPIFIFrequency = 0;
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CLKPWR_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief 		Set value of each Peripheral Clock Selection
+ * @param[in]	ClkType clock type that will be divided, should be:
+ * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
+ * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
+ * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
+ * 				- CLKPWR_CLKTYPE_USB 		: USB clock
+ * @param[in]	DivVal	Value of divider. This value should be set as follows:
+ * 					- CPU clock: DivVal must be in range: 0..31
+ * 					- Peripheral clock: DivVal must be in range: 0..31
+ * 					- EMC clock: DivVal must be:
+ * 							+ 0: The EMC uses the same clock as the CPU
+ * 							+ 1: The EMC uses a clock at half the rate of the CPU
+ *   				- USB clock: DivVal must be:
+ * 							+ 0: the divider is turned off, no clock will
+ * 								 be provided to the USB subsystem
+ * 							+ 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
+ * 							+ 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
+ * @return none
+ * Note: Pls assign right DivVal, this function will not check if it is illegal.
+ **********************************************************************/
+void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
+{
+	switch(ClkType)
+	{
+	case CLKPWR_CLKTYPE_CPU:
+		LPC_SC->CCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_PER:
+		LPC_SC->PCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_EMC:
+		LPC_SC->EMCCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_USB:
+		LPC_SC->USBCLKSEL &= ~(0x0000001F);
+		LPC_SC->USBCLKSEL |= DivVal;
+		break;
+	default:
+		while(1);//Error Loop;
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Get current clock value
+ * @param[in]	ClkType clock type that will be divided, should be:
+ * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
+ * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
+ * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
+ * 				- CLKPWR_CLKTYPE_USB 		: USB clock
+ **********************************************************************/
+uint32_t CLKPWR_GetCLK (uint8_t ClkType)
+{
+	switch(ClkType)
+	{
+		case CLKPWR_CLKTYPE_CPU:
+			return SystemCoreClock;
+
+		case CLKPWR_CLKTYPE_PER:
+			return PeripheralClock;
+
+		case CLKPWR_CLKTYPE_EMC:
+			return EMCClock;
+
+		case CLKPWR_CLKTYPE_USB:
+			return USBClock;
+
+		default:
+			while(1);//error loop
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Configure power supply for each peripheral according to NewState
+ * @param[in]	PPType	Type of peripheral used to enable power,
+ *     			should be one of the following:
+ *     			-  CLKPWR_PCONP_PCLCD		: LCD
+ *     			-  CLKPWR_PCONP_PCTIM0 		: Timer 0
+				-  CLKPWR_PCONP_PCTIM1 		: Timer 1
+				-  CLKPWR_PCONP_PCUART0  	: UART 0
+				-  CLKPWR_PCONP_PCUART1   	: UART 1
+				-  CLKPWR_PCONP_PCPWM0		: PWM 0
+				-  CLKPWR_PCONP_PCPWM1 		: PWM 1
+				-  CLKPWR_PCONP_PCI2C0 		: I2C 0
+				-  CLKPWR_PCONP_PCUART4		: UART4
+				-  CLKPWR_PCONP_PCRTC   	: RTC
+				-  CLKPWR_PCONP_PCSSP1 		: SSP 1
+				-  CLKPWR_PCONP_PCEMC		: EMC
+				-  CLKPWR_PCONP_PCADC   		: ADC
+				-  CLKPWR_PCONP_PCAN1   	: CAN 1
+				-  CLKPWR_PCONP_PCAN2   	: CAN 2
+				-  CLKPWR_PCONP_PCGPIO 		: GPIO
+				-  CLKPWR_PCONP_PCMC 		: MCPWM
+				-  CLKPWR_PCONP_PCQEI 		: QEI
+				-  CLKPWR_PCONP_PCI2C1   	: I2C 1
+				-  CLKPWR_PCONP_PCSSP2		: SSP 2
+				-  CLKPWR_PCONP_PCSSP0 		: SSP 0
+				-  CLKPWR_PCONP_PCTIM2 		: Timer 2
+				-  CLKPWR_PCONP_PCTIM3 		: Timer 3
+				-  CLKPWR_PCONP_PCUART2  	: UART 2
+				-  CLKPWR_PCONP_PCUART3   	: UART 3
+				-  CLKPWR_PCONP_PCI2C2 		: I2C 2
+				-  CLKPWR_PCONP_PCI2S   	: I2S
+				-  CLKPWR_PCONP_PCSDC		: SDC
+				-  CLKPWR_PCONP_PCGPDMA   	: GPDMA
+				-  CLKPWR_PCONP_PCENET 		: Ethernet
+				-  CLKPWR_PCONP_PCUSB   	: USB
+ *
+ * @param[in]	NewState	New state of Peripheral Power, should be:
+ * 				- ENABLE	: Enable power for this peripheral
+ * 				- DISABLE	: Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		LPC_SC->PCONP |= PPType;
+	}
+	else if (NewState == DISABLE)
+	{
+		LPC_SC->PCONP &= ~PPType;
+	}
+}
+
+#if 0
+// nxp21346
+/*********************************************************************//**
+ * @brief 		Configure hardware reset for each peripheral according to NewState
+ * @param[in]	PPType	Type of peripheral used to enable power,
+ *     			should be one of the following:
+ *     			-  CLKPWR_RSTCON0_LCD		: LCD
+ *     			-  CLKPWR_RSTCON0_TIM0 		: Timer 0
+				-  CLKPWR_RSTCON0_TIM1 		: Timer 1
+				-  CLKPWR_RSTCON0_UART0  	: UART 0
+				-  CLKPWR_RSTCON0_UART1   	: UART 1
+				-  CLKPWR_RSTCON0_PWM0 		: PWM 0
+				-  CLKPWR_RSTCON0_PWM1 		: PWM 1
+				-  CLKPWR_RSTCON0_I2C0		: I2C 0
+				-  CLKPWR_RSTCON0_UART4   	: UART 4
+				-  CLKPWR_RSTCON0_RTC 		: RTC
+				-  CLKPWR_RSTCON0_SSP1		: SSP 1
+				-  CLKPWR_RSTCON0_EMC   	: EMC
+				-  CLKPWR_RSTCON0_ADC   	: ADC
+				-  CLKPWR_RSTCON0_CAN1   	: CAN 1
+				-  CLKPWR_RSTCON0_CAN2 		: CAN 2
+				-  CLKPWR_RSTCON0_GPIO 		: GPIO
+				-  CLKPWR_RSTCON0_MCPWM 	: MCPWM
+				-  CLKPWR_RSTCON0_QEI   	: QEI
+				-  CLKPWR_RSTCON0_I2C1		: I2C 1
+				-  CLKPWR_RSTCON0_SSP2 		: SSP 2
+				-  CLKPWR_RSTCON0_SSP0 		: SSP 0
+				-  CLKPWR_RSTCON0_TIM2 		: Timer 2
+				-  CLKPWR_RSTCON0_TIM3  	: Timer 3
+				-  CLKPWR_RSTCON0_UART2  	: UART 2
+				-  CLKPWR_RSTCON0_UART3   	: UART 3
+				-  CLKPWR_RSTCON0_I2C2 		: I2C 2
+				-  CLKPWR_RSTCON0_I2S   	: I2S
+				-  CLKPWR_RSTCON0_SDC		: SDC
+				-  CLKPWR_RSTCON0_GPDMA   	: GPDMA
+				-  CLKPWR_RSTCON0_ENET 		: Ethernet
+				-  CLKPWR_RSTCON0_USB   	: USB
+ *
+ * @param[in]	NewState	New state of Peripheral Power, should be:
+ * 				- ENABLE	: Enable power for this peripheral
+ * 				- DISABLE	: Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
+{
+	if(PType < 32)
+	{
+		if(NewState == ENABLE)
+			LPC_SC->RSTCON0 |=(1<<PType);
+		else
+			LPC_SC->RSTCON0 &=~(1<<PType);
+	}
+	else
+	{
+		if(NewState == ENABLE)
+			LPC_SC->RSTCON1 |= (1<<(PType - 31));
+		else
+			LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
+	}
+}
+// nxp21346
+#endif
+
+/*********************************************************************//**
+ * @brief 		Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_Sleep(void)
+{
+	LPC_SC->PCON = 0x00;
+	/* Sleep Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_DeepSleep(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x8;
+	/* Deep Sleep Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_PowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x09;
+	/* Power Down Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_DeepPowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x03;
+	/* Deep Power Down Mode*/
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h

@@ -0,0 +1,242 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_clkpwr.h			2011-06-02
+*//**
+* @file		lpc177x_8x_clkpwr.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for Clock and Power Control firmware library on 
+*			LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR	Clock Power
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_CLKPWR_H_
+#define __LPC177X_8X_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+#include "system_LPC177x_8x.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/********************************************************************
+* Clock Source Selection Definitions
+**********************************************************************/
+#define CLKPWR_CLKSRCSEL_IRCOSC		((uint32_t)(0))
+#define CLKPWR_CLKSRCSEL_MAINOSC	((uint32_t)(1))
+
+/********************************************************************
+* Clock type/domain Definitions (calculated from input and pre-configuration
+* parameter(s)
+**********************************************************************/
+#define CLKPWR_CLKTYPE_CPU			((uint32_t)(0))
+#define CLKPWR_CLKTYPE_PER			((uint32_t)(1))
+#define CLKPWR_CLKTYPE_EMC			((uint32_t)(2))
+#define CLKPWR_CLKTYPE_USB			((uint32_t)(3))
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** LCD controller power/clock control bit */
+#define CLKPWR_PCONP_PCLCD		((uint32_t)(1<<0))
+
+/** Timer/Counter 0 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM0		((uint32_t)(1<<1))
+
+/* Timer/Counter 1 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM1		((uint32_t)(1<<2))
+
+/** UART0 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART0  	((uint32_t)(1<<3))
+
+/** UART1 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART1  	((uint32_t)(1<<4))
+
+/** PWM0 power/clock control bit */
+#define CLKPWR_PCONP_PCPWM0		((uint32_t)(1<<5))
+
+/** PWM1 power/clock control bit */
+#define	CLKPWR_PCONP_PCPWM1		((uint32_t)(1<<6))
+
+/** The I2C0 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C0		((uint32_t)(1<<7))
+
+/** UART4 power/clock control bit */
+#define CLKPWR_PCONP_PCUART4	((uint32_t)(1<<8))
+
+/** The RTC power/clock control bit */
+#define	CLKPWR_PCONP_PCRTC  	((uint32_t)(1<<9))
+
+/** The SSP1 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCSSP1	 	((uint32_t)(1<<10))
+
+/** External Memory controller power/clock control bit */
+#define CLKPWR_PCONP_PCEMC		((uint32_t)(1<<11))
+
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define	CLKPWR_PCONP_PCADC  	((uint32_t)(1<<12))
+
+/** CAN Controller 1 power/clock control bit */
+#define	CLKPWR_PCONP_PCAN1  	((uint32_t)(1<<13))
+
+/** CAN Controller 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCAN2 	((uint32_t)(1<<14))
+
+/** GPIO power/clock control bit */
+#define	CLKPWR_PCONP_PCGPIO 	((uint32_t)(1<<15))
+
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMCPWM 	((uint32_t)(1<<17))
+
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI 		((uint32_t)(1<<18))
+
+/** The I2C1 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C1  	((uint32_t)(1<<19))
+
+/** The SSP2 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP2		((uint32_t)(1<<20))
+
+/** The SSP0 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCSSP0		((uint32_t)(1<<21))
+
+/** Timer 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM2	((uint32_t)(1<<22))
+
+/** Timer 3 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM3	((uint32_t)(1<<23))
+
+/** UART 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART2  	((uint32_t)(1<<24))
+
+/** UART 3 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART3  	((uint32_t)(1<<25))
+
+/** I2C interface 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C2	((uint32_t)(1<<26))
+
+/** I2S interface power/clock control bit*/
+#define	CLKPWR_PCONP_PCI2S  	((uint32_t)(1<<27))
+
+/** SD card interface power/clock control bit */
+#define CLKPWR_PCONP_PCSDC		((uint32_t)(1<<28))
+
+/** GP DMA function power/clock control bit*/
+#define	 CLKPWR_PCONP_PCGPDMA  	((uint32_t)(1<<29))
+
+/** Ethernet block power/clock control bit*/
+#define	 CLKPWR_PCONP_PCENET	((uint32_t)(1<<30))
+
+/** USB interface power/clock control bit*/
+#define	 CLKPWR_PCONP_PCUSB  	((uint32_t)(1<<31))
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+#define CLKPWR_RSTCON0_LCD		((uint32_t)(0))
+#define CLKPWR_RSTCON0_TIM0		((uint32_t)(1))
+#define CLKPWR_RSTCON0_TIM1		((uint32_t)(2))
+#define CLKPWR_RSTCON0_UART0	((uint32_t)(3))
+#define CLKPWR_RSTCON0_UART1	((uint32_t)(4))
+#define CLKPWR_RSTCON0_PWM0		((uint32_t)(5))
+#define CLKPWR_RSTCON0_PWM1		((uint32_t)(6))
+#define CLKPWR_RSTCON0_I2C0		((uint32_t)(7))
+#define CLKPWR_RSTCON0_UART4	((uint32_t)(8))
+#define CLKPWR_RSTCON0_RTC		((uint32_t)(9))
+#define CLKPWR_RSTCON0_SSP1		((uint32_t)(10))
+#define CLKPWR_RSTCON0_EMC		((uint32_t)(11))
+#define CLKPWR_RSTCON0_ADC		((uint32_t)(12))
+#define CLKPWR_RSTCON0_CAN1		((uint32_t)(13))
+#define CLKPWR_RSTCON0_CAN2		((uint32_t)(14))
+#define CLKPWR_RSTCON0_GPIO		((uint32_t)(15))
+#define CLKPWR_RSTCON0_MCPWM	((uint32_t)(17))
+#define CLKPWR_RSTCON0_QEI		((uint32_t)(18))
+#define CLKPWR_RSTCON0_I2C1		((uint32_t)(19))
+#define CLKPWR_RSTCON0_SSP2		((uint32_t)(20))
+#define CLKPWR_RSTCON0_SSP0		((uint32_t)(21))
+#define CLKPWR_RSTCON0_TIM2		((uint32_t)(22))
+#define CLKPWR_RSTCON0_TIM3		((uint32_t)(23))
+#define CLKPWR_RSTCON0_UART2	((uint32_t)(24))
+#define CLKPWR_RSTCON0_UART3	((uint32_t)(25))
+#define CLKPWR_RSTCON0_I2C2		((uint32_t)(26))
+#define CLKPWR_RSTCON0_I2S		((uint32_t)(27))
+#define CLKPWR_RSTCON0_SDC		((uint32_t)(28))
+#define CLKPWR_RSTCON0_GPDMA	((uint32_t)(29))
+#define CLKPWR_RSTCON0_ENET		((uint32_t)(30))
+#define CLKPWR_RSTCON0_USB		((uint32_t)(31))
+
+#define CLKPWR_RSTCON1_IOCON	((uint32_t)(32))
+#define CLKPWR_RSTCON1_DAC		((uint32_t)(33))
+#define CLKPWR_RSTCON1_CANACC	((uint32_t)(34))
+/**
+ * @}
+ */
+ 
+/* External clock variable from system_LPC177x_8x.h */
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  	*/
+extern uint32_t PeripheralClock;	 /*!< Peripheral Clock Frequency (Pclk) 	*/
+extern uint32_t EMCClock;		 /*!< EMC Clock Frequency                   	*/
+
+/* External clock variable from lpc177x_8x_clkpwr.h */
+extern uint32_t USBClock;		/*!< USB Frequency 								*/
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal);
+uint32_t CLKPWR_GetCLK(uint8_t ClkType);
+void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState);
+void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC177X_8X_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

bsp/lpc178x/drivers/lpc177x_8x_pinsel.c

@@ -0,0 +1,348 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_pinsel.c			2011-06-02
+*//**
+* @file		lpc177x_8x_pinsel.c
+* @brief	Contains all functions support for Pin-connection block
+*			firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup PINSEL
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_pinsel.h"
+
+#define PINSEL_I2C_MODE_POS				(8)
+#define PINSEL_I2C_MODE_NUMBITS			(2)
+#define PINSEL_I2C_MODE_BITMASK			(0x03)
+
+#define PINSEL_BASIC_MODE_POS			(3)
+#define PINSEL_BASIC_MODE_NUMBITS		(2)
+#define PINSEL_BASIC_MODE_BITMASK		(0x03)
+
+#define PINSEL_DACEN_POS				(16)
+#define PINSEL_DACEN_BITMASK			(0x01)
+#define PINSEL_DACEN_NUMBITS			(1)
+
+#define PINSEL_GLITCH_FILTER_POS				(8)
+#define PINSEL_GLITCH_FILTER_BITMASK			(0x01)
+#define PINSEL_GLITCH_FILTER_NUMBITS			(1)
+
+#define PINSEL_ADMODE_POS				(7)
+#define PINSEL_ADMODE_BITMASK			(0x01)
+#define PINSEL_ADMODE_NUMBITS			(1)
+
+/* Private Functions ---------------------------------------------------------- */
+
+/*********************************************************************//**
+ * @brief		Get pointer to GPIO peripheral due to GPIO port
+ * @param[in]	portnum		Port Number value, should be in range from 0..3.
+ * @param[in]	pinnum		Pin number value, should be in range from 0..31
+ * @return		Pointer to GPIO peripheral
+ **********************************************************************/
+static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
+	return pPIN;
+}
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup PINSEL_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief 		Setup the pin selection function
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	funcnum Function number, should be range: 0..7
+ * 				- 0: Select GPIO (Default)
+ * 				- 1: Selects the 1st alternate function
+ * 				- 2: Selects the 2nd alternate function
+ * 				...
+ *				- 7: Selects the 7th alternate function
+ * @return 		None
+ **********************************************************************/
+void PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	*pPIN &= 0x00000007;//Clear function bits
+	*pPIN |= funcnum;
+}
+
+
+/*********************************************************************//**
+ * @brief 		Setup resistor mode for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	modenum: Mode number, should be in range: 0..3
+				- IOCON_MODE_PLAIN: Plain output
+				- IOCON_MODE_PULLDOWN: Pull-down enable
+				- IOCON_MODE_PULLUP: Pull-up enable
+				- IOCON_MODE_REPEATER: Repeater mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	*(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
+	*(uint32_t *)pPIN |= modenum;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup hysteresis for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Hysteresis mode, should be:
+ * 				- ENABLE: Hysteresis enable
+ * 				- DISABLE: Hysteresis disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_HYS;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Slew rate for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Slew rate control, should be:
+ * 				- ENABLE: Output slew rate control is enable
+ * 				- DISABLE: Output slew rate control is disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_SLEW;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Input Buffer for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Input buffer mode, should be:
+ * 				- ENABLE: The input buffer is enable
+ * 				- DISABLE: The input buffer is disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_INBUF;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup I2CMode for only pins that provide special I2C functionality
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	I2CMode I2C mode, should be:
+ * 				- IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
+ * 				- IOCON_I2CMODE_OPENDRAIN: Open drain I/O
+ * 				- IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
+ * 				- IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	*(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
+	*(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Open-drain mode in each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Open-drain mode:
+ * 				- DISABLE: Normal pin I/O mode
+ * 				- ENABLE: Open-drain enable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
+	}
+	else
+	{
+		*(uint32_t *)pPIN |= IOCON_ODMODE;
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Enable the Analog mode for each pin (default is as Digital pins)
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: Enable the DAC mode of the pin
+				- DISABLE: Disable the DAC mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	uint8_t condition = 0;
+
+	condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
+					| ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
+					| ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
+
+	if(!condition)
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	//Clear this bit to set the pin to Analog mode
+	*(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
+
+	if(enable)
+	{
+
+	}
+	else
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
+	}
+
+	return;
+}
+
+
+
+/*********************************************************************//**
+ * @brief 		Choose the DAC mode for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: Enable the DAC mode of the pin
+				- DISABLE: Disable the DAC mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	// This setting is only for DAC pin (output pin)
+	if(!((portnum == 0) && (pinnum == 26)))
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	//Clear DAC Enable function bits
+	*(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
+
+	if(enable)
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
+	}
+	else
+	{
+
+	}
+
+	return;
+}
+
+/*********************************************************************//**
+ * @brief 		Control the glitch filter for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: The noise pulses below approximately 10ns are filtered out
+				- DISABLE: No input filtering is done.
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	// This setting is only for DAC pin (output pin)
+	if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	*(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
+
+	//Clear Filter bits
+	*(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
+
+	if(!enable)
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
+	}
+	else
+	{
+
+	}
+
+	*pPIN = *pPIN;
+
+	return;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

bsp/lpc178x/drivers/lpc177x_8x_pinsel.h

@@ -0,0 +1,263 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_pinsel.h			2011-06-02
+*//**
+* @file		lpc177x_8x_pinsel.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for Pin-connection block firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PINSEL	Pin Selection
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_PINSEL_H
+#define __LPC177X_8X_PINSEL_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Macros
+ * @{
+ */
+
+/* Macros define IOCON bits */
+#define IOCON_MODE_PLAIN			((0<<3))
+#define IOCON_MODE_PULLDOWN			((1<<3))
+#define IOCON_MODE_PULLUP			((2<<3))
+#define IOCON_MODE_REPEATER			((3<<3))
+#define IOCON_HYS					((1<<5))
+#define IOCON_SLEW					((1<<6))
+#define IOCON_INBUF					((1<<7))
+#define IOCON_I2CMODE_FAST			((0<<8))
+#define IOCON_I2CMODE_OPENDRAIN		((1<<8))
+#define IOCON_I2CMODE_FASTPLUS		((2<<8))
+#define IOCON_I2CMODE_HIGHOPENDRAIN	((3<<8))
+#define IOCON_ODMODE				((1<<10))
+
+
+/* Macros define for LOC registers */
+#define LOC_CAN_RD_1_P0_0			((0))	/**< Input for CAN_RD_1 comes from P0.0 */
+#define LOC_CAN_RD_1_P0_21			((1))	/**< Input for CAN_RD_1 comes from P0.21 */
+#define LOC_CAN_RD_2_P2_7			((0))	/**< Input for CAN_RD_2 comes from P2.7 */
+#define LOC_CAN_RD_2_P0_4			((1))	/**< Input for CAN_RD_2 comes from P0.4 */
+#define LOC_ENET_MDIO_P2_9			((0))	/**< Input for ENET_MDIO comes from P2.9 */
+#define LOC_ENET_MDIO_P1_17			((1))	/**< Input for ENET_MDIO comes from P1.17 */
+#define LOC_EINT_0_P0_29			((0))	/**< Input for EINT_0 comes from P0.29 */
+#define LOC_EINT_0_P2_10			((1))	/**< Input for EINT_0 comes from P2.10 */
+#define LOC_EINT_1_P0_30			((0))	/**< Input for EINT_1 comes from P0.30 */
+#define LOC_EINT_1_P2_11			((1))	/**< Input for EINT_1 comes from P2.11 */
+#define LOC_I2C0_SCL_P1_31			((0))	/**< Input for I2C0_SCL comes from P1.31 */
+#define LOC_I2C0_SCL_P0_28			((1))	/**< Input for I2C0_SCL comes from P0.28 */
+#define LOC_I2C0_SCL_P5_3			((2))	/**< Input for I2C0_SCL comes from P5.3 */
+#define LOC_I2C0_SDA_P1_30			((0))	/**< Input for I2C0_SDA comes from P1.30 */
+#define LOC_I2C0_SDA_P0_27			((1))	/**< Input for I2C0_SDA comes from P0.27 */
+#define LOC_I2C0_SDA_P5_2			((2))	/**< Input for I2C0_SDA comes from P5.2 */
+#define LOC_I2C1_SCL_P0_1			((0))	/**< Input for I2C1_SCL comes from P0.1 */
+#define LOC_I2C1_SCL_P2_15			((1))	/**< Input for I2C1_SCL comes from P2.15 */
+#define LOC_I2C1_SCL_P0_20			((2))	/**< Input for I2C1_SCL comes from P0.20 */
+#define LOC_I2C1_SDA_P2_14			((0))	/**< Input for I2C1_SDA comes from P2.14 */
+#define LOC_I2C1_SDA_P0_0			((1))	/**< Input for I2C1_SDA comes from P0.0 */
+#define LOC_I2C1_SDA_P0_19			((2))	/**< Input for I2C1_SDA comes from P0.19 */
+#define LOC_I2C2_SCL_P2_31			((0))	/**< Input for I2C2_SCL comes from P2.31 */
+#define LOC_I2C2_SCL_P0_11			((1))	/**< Input for I2C2_SCL comes from P0.11 */
+#define LOC_I2C2_SCL_P4_21			((2))	/**< Input for I2C2_SCL comes from P4.21 */
+#define LOC_I2C2_SCL_P4_29			((3))	/**< Input for I2C2_SCL comes from P4.29 */
+#define LOC_I2C2_SDA_P2_30			((0))	/**< Input for I2C2_SDA comes from P2.30 */
+#define LOC_I2C2_SDA_P0_10			((1))	/**< Input for I2C2_SDA comes from P0.10 */
+#define LOC_I2C2_SDA_P4_20			((2))	/**< Input for I2C2_SDA comes from P4.20 */
+#define LOC_I2C2_SDA_P1_15			((3))	/**< Input for I2C2_SDA comes from P1.15 */
+#define LOC_I2S_RX_SCK_P0_23		((0))	/**< Input for I2S_RX_SCK comes from P0.23 */
+#define LOC_I2S_RX_SCK_P0_4			((1))	/**< Input for I2S_RX_SCK comes from P0.4 */
+#define LOC_I2S_RX_SDA_P0_25		((0))	/**< Input for I2S_RX_SDA comes from P0.25 */
+#define LOC_I2S_RX_SDA_P0_6			((1))	/**< Input for I2S_RX_SDA comes from P0.6 */
+#define LOC_I2S_RX_WS_P0_24			((0))	/**< Input for I2S_RX_WS comes from P0.24 */
+#define LOC_I2S_RX_WS_P0_5			((1))	/**< Input for I2S_RX_WS comes from P0.5 */
+#define LOC_I2S_TX_SCK_P2_11		((0))	/**< Input for I2S_TX_SCK comes from P2.11 */
+#define LOC_I2S_TX_SCK_P0_7			((1))	/**< Input for I2S_TX_SCK comes from P0.7 */
+#define LOC_I2S_TX_WS_P2_12			((0))	/**< Input for I2S_TX_WS comes from P2.12 */
+#define LOC_I2S_TX_WS_P0_8			((1))	/**< Input for I2S_TX_WS comes from P0.8 */
+#define LOC_PWM0_CAP_0_P1_12		((0))	/**< Input for PWM0_CAP_0 comes from P1.12 */
+#define LOC_PWM0_CAP_0_P3_22		((1))	/**< Input for PWM0_CAP_0 comes from P3.22 */
+#define LOC_PWM1_CAP_0_P3_23		((0))	/**< Input for PWM1_CAP_0 comes from P3.23 */
+#define LOC_PWM1_CAP_0_P1_28		((1))	/**< Input for PWM1_CAP_0 comes from P1.28 */
+#define LOC_PWM1_CAP_0_P2_6			((2))	/**< Input for PWM1_CAP_0 comes from P2.6 */
+#define LOC_SD_CMD_P0_20			((0))	/**< Input for SD_CMD comes from P0.20 */
+#define LOC_SD_CMD_P1_3				((1))	/**< Input for SD_CMD comes from P1.3 */
+#define LOC_SD_DAT_0_P0_22			((0))	/**< Input for SD_DAT_0 comes from P0.22 */
+#define LOC_SD_DAT_0_P1_6			((1))	/**< Input for SD_DAT_0 comes from P1.6 */
+#define LOC_SD_DAT_1_P2_11			((0))	/**< Input for SD_DAT_1 comes from P2.11 */
+#define LOC_SD_DAT_1_P1_7			((1))	/**< Input for SD_DAT_1 comes from P1.7 */
+#define LOC_SD_DAT_2_P2_12			((0))	/**< Input for SD_DAT_2 comes from P2.12 */
+#define LOC_SD_DAT_2_P1_11			((1))	/**< Input for SD_DAT_2 comes from P1.11 */
+#define LOC_SD_DAT_3_P2_13			((0))	/**< Input for SD_DAT_3 comes from P2.13 */
+#define LOC_SD_DAT_3_P1_12			((1))	/**< Input for SD_DAT_3 comes from P1.12 */
+#define LOC_SSP0_MISO_P2_26			((0))	/**< Input for SSP0_MISO comes from P2.26 */
+#define LOC_SSP0_MISO_P1_23			((1))	/**< Input for SSP0_MISO comes from P1_23 */
+#define LOC_SSP0_MISO_P0_17			((2))	/**< Input for SSP0_MISO comes from P0_17 */
+#define LOC_SSP0_MOSI_P2_27			((0))	/**< Input for SSP0_MOSI comes from P2.27 */
+#define LOC_SSP0_MOSI_P1_24			((1))	/**< Input for SSP0_MOSI comes from P1.24 */
+#define LOC_SSP0_MOSI_P0_18			((2))	/**< Input for SSP0_MOSI comes from P0.18 */
+#define LOC_SSP0_SCK_P1_20			((0))	/**< Input for SSP0_SCK comes from P1.20 */
+#define LOC_SSP0_SCK_P2_22			((1))	/**< Input for SSP0_SCK comes from P2.22 */
+#define LOC_SSP0_SCK_P0_15			((2))	/**< Input for SSP0_SCK comes from P0_15 */
+#define LOC_SSP0_SSEL_P2_23			((0))	/**< Input for SSP0_SSEL comes from P2.23 */
+#define LOC_SSP0_SSEL_P1_21			((1))	/**< Input for SSP0_SSEL comes from P1.21 */
+#define LOC_SSP0_SSEL_P1_28			((2))	/**< Input for SSP0_SSEL comes from P1.28 */
+#define LOC_SSP0_SSEL_P0_16			((3))	/**< Input for SSP0_SSEL comes from P0.16 */
+#define LOC_SSP1_MISO_P0_12			((0))	/**< Input for SSP1_MISO comes from P0.12 */
+#define LOC_SSP1_MISO_P1_18			((1))	/**< Input for SSP1_MISO comes from P1.18 */
+#define LOC_SSP1_MISO_P4_22			((2))	/**< Input for SSP1_MISO comes from P4_22 */
+#define LOC_SSP1_MISO_P0_8			((3))	/**< Input for SSP1_MISO comes from P0.8 */
+#define LOC_SSP1_MOSI_P0_13			((0))	/**< Input for SSP1_MOSI comes from P0.13 */
+#define LOC_SSP1_MOSI_P1_22			((1))	/**< Input for SSP1_MOSI comes from P1.22 */
+#define LOC_SSP1_MOSI_P4_23			((2))	/**< Input for SSP1_MOSI comes from P4.23 */
+#define LOC_SSP1_MOSI_P0_9			((3))	/**< Input for SSP1_MOSI comes from P0.9 */
+#define LOC_SSP1_SCK_P1_31			((0))	/**< Input for SSP1_SCK comes from P1.31 */
+#define LOC_SSP1_SCK_P1_19			((1))	/**< Input for SSP1_SCK comes from P1.19 */
+#define LOC_SSP1_SCK_P4_20			((2))	/**< Input for SSP1_SCK comes from P4_20 */
+#define LOC_SSP1_SCK_P0_7			((3))	/**< Input for SSP1_SCK comes from P0_7 */
+#define LOC_SSP1_SSEL_P0_14			((0))	/**< Input for SSP1_SSEL comes from P0.14 */
+#define LOC_SSP1_SSEL_P1_26			((1))	/**< Input for SSP1_SSEL comes from P1.26 */
+#define LOC_SSP1_SSEL_P4_21			((2))	/**< Input for SSP1_SSEL comes from P4.21 */
+#define LOC_SSP1_SSEL_P0_6			((3))	/**< Input for SSP1_SSEL comes from P0.6 */
+#define LOC_SSP2_MISO_P1_4			((1))	/**< Input for SSP2_MISO comes from P1.4 */
+#define LOC_SSP2_MOSI_P1_1			((1))	/**< Input for SSP2_MOSI comes from P1.1 */
+#define LOC_SSP2_SCK_P1_0			((1))	/**< Input for SSP2_SCK comes from P1.0 */
+#define LOC_SSP2_SSEL_P1_8			((1))	/**< Input for SSP2_SSEL comes from P1.8 */
+#define LOC_T0_CAP_0_P3_23			((0))	/**< Input for T0_CAP_0 comes from P3.23 */
+#define LOC_T0_CAP_0_P1_26			((1))	/**< Input for T0_CAP_0 comes from P1.26 */
+#define LOC_T0_CAP_1_P3_24			((0))	/**< Input for T0_CAP_1 comes from P3.24 */
+#define LOC_T0_CAP_1_P1_27			((1))	/**< Input for T0_CAP_1 comes from P1.27 */
+#define LOC_T1_CAP_0_P1_18			((0))	/**< Input for T1_CAP_0 comes from P1.18 */
+#define LOC_T1_CAP_0_P3_27			((1))	/**< Input for T1_CAP_0 comes from P3.27 */
+#define LOC_T1_CAP_1_P3_28			((0))	/**< Input for T1_CAP_1 comes from P3.28 */
+#define LOC_T1_CAP_1_P1_19			((1))	/**< Input for T1_CAP_1 comes from P1.19 */
+#define LOC_T2_CAP_0_P2_14			((0))	/**< Input for T2_CAP_0 comes from P2.14 */
+#define LOC_T2_CAP_0_P2_6			((1))	/**< Input for T2_CAP_0 comes from P2.6 */
+#define LOC_T2_CAP_0_P0_4			((2))	/**< Input for T2_CAP_0 comes from P0.4 */
+#define LOC_T2_CAP_0_P1_14			((3))	/**< Input for T2_CAP_0 comes from P1.14 */
+#define LOC_T2_CAP_1_P2_15			((0))	/**< Input for T2_CAP_1 comes from P2.15 */
+#define LOC_T2_CAP_1_P0_5			((1))	/**< Input for T2_CAP_1 comes from P0.5 */
+#define LOC_T3_CAP_0_P0_23			((0))	/**< Input for T3_CAP_0 comes from P0.23 */
+#define LOC_T3_CAP_0_P2_22			((1))	/**< Input for T3_CAP_0 comes from P2.22 */
+#define LOC_T3_CAP_0_P1_10			((2))	/**< Input for T3_CAP_0 comes from P1.10 */
+#define LOC_T3_CAP_1_P0_24			((0))	/**< Input for T3_CAP_1 comes from P0.24 */
+#define LOC_T3_CAP_1_P2_23			((1))	/**< Input for T3_CAP_1 comes from P2.23 */
+#define LOC_T3_CAP_1_P1_0			((2))	/**< Input for T3_CAP_1 comes from P1.0 */
+#define LOC_U0_RXD_P0_1				((0))	/**< Input for U0_RXD comes from P0.1 */
+#define LOC_U0_RXD_P0_3				((1))	/**< Input for U0_RXD comes from P0.3 */
+#define LOC_U1_CTS_P0_17			((0))	/**< Input for U1_CTS comes from P0.17 */
+#define LOC_U1_CTS_P2_8				((1))	/**< Input for U1_CTS comes from P2.8 */
+#define LOC_U1_CTS_P2_2				((2))	/**< Input for U1_CTS comes from P2.2 */
+#define LOC_U1_CTS_P3_18			((3))	/**< Input for U1_CTS comes from P3.18 */
+#define LOC_U1_DCD_P0_18			((0))	/**< Input for U1_DCD comes from P0.18 */
+#define LOC_U1_DCD_P2_3				((1))	/**< Input for U1_DCD comes from P2.3 */
+#define LOC_U1_DCD_P3_19			((2))	/**< Input for U1_DCD comes from P3_19 */
+#define LOC_U1_DSR_P0_19			((0))	/**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_DSR_P2_4				((1))	/**< Input for U1_DSR comes from P2.4 */
+#define LOC_U1_DSR_P3_20			((2))	/**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_RI_P0_21				((0))	/**< Input for U1_RI comes from P0.21 */
+#define LOC_U1_RI_P2_6				((1))	/**< Input for U1_RI comes from P2.6 */
+#define LOC_U1_RI_P3_22				((2))	/**< Input for U1_RI comes from P3.22 */
+#define LOC_U1_RXD_P0_16			((0))	/**< Input for U1_RXD comes from P0.16 */
+#define LOC_U1_RXD_P3_17			((1))	/**< Input for U1_RXD comes from P3.17 */
+#define LOC_U1_RXD_P2_1				((2))	/**< Input for U1_RXD comes from P2.1 */
+#define LOC_U2_RXD_P0_11			((0))	/**< Input for U2_RXD comes from P0.11 */
+#define LOC_U2_RXD_P4_23			((1))	/**< Input for U2_RXD comes from P4.23 */
+#define LOC_U2_RXD_P2_9				((2))	/**< Input for U2_RXD comes from P2.9 */
+#define LOC_U3_RXD_P0_26			((0))	/**< Input for U3_RXD comes from P0.26 */
+#define LOC_U3_RXD_P0_1				((1))	/**< Input for U3_RXD comes from P0.1 */
+#define LOC_U3_RXD_P4_29			((2))	/**< Input for U3_RXD comes from P4.29 */
+#define LOC_U3_RXD_P0_3				((3))	/**< Input for U3_RXD comes from P0.3 */
+#define LOC_U4_RXD_P2_9				((0))	/**< Input for U4_RXD comes from P2.9 */
+#define LOC_U4_RXD_P5_3				((1))	/**< Input for U4_RXD comes from P5.3 */
+#define LOC_USB_SCL_P0_28			((0))	/**< Input for USB_SCL comes from P0.28 */
+#define LOC_USB_SCL_P1_28			((1))	/**< Input for USB_SCL comes from P1.28 */
+#define LOC_USB_SDA_P0_27			((0))	/**< Input for USB_SDA comes from P0.27 */
+#define LOC_USB_SDA_P1_29			((1))	/**< Input for USB_SDA comes from P1.29 */
+
+/**
+ * @}
+ */
+
+/** @defgroup PINSEL_Public_Types PINSEL Public Types
+ * @{
+ */
+ 
+
+typedef enum
+{
+	PINSEL_BASICMODE_PLAINOUT  = 0,	/**< Plain output */
+	PINSEL_BASICMODE_PULLDOWN,		/**< Pull-down enabled */
+  	PINSEL_BASICMODE_PULLUP,		/**< Pull-up enabled (default) */
+	PINSEL_BASICMODE_REPEATER		/**< Repeater mode */
+}PinSel_BasicMode;
+
+typedef enum
+{
+	/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
+	PINSEL_I2CMODE_FAST_STANDARD  = 0,
+	/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
+	PINSEL_I2CMODE_OPENDRAINIO,
+	/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
+	PINSEL_I2CMODE_FASTMODEPLUS,
+	/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
+	PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
+}PinSel_I2cMode;
+
+/**
+ * @}
+ */
+ 
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Functions
+ * @{
+ */
+void PINSEL_ConfigPin(uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
+void PINSEL_SetPinMode(uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum);
+void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode);
+void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+
+
+/**
+ * @}
+ */
+
+#endif /* LPC177x_8x_PINSEL_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+

bsp/lpc178x/drivers/lpc177x_8x_uart.c

@@ -0,0 +1,1370 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_uart.c			2011-06-02
+*//**
+* @file		lpc177x_8x_uart.c
+* @brief	Contains all functions support for UART firmware library
+*			on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup UART
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_uart.h"
+#include "lpc177x_8x_clkpwr.h"
+
+/* Private Functions ---------------------------------------------------------- */
+
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
+
+
+/*********************************************************************//**
+ * @brief		Determines best dividers to get a target clock rate
+ * @param[in]	UARTx	Pointer to selected UART peripheral, should be:
+ * 				- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	baudrate Desired UART baud rate.
+ * @return 		Error status, could be:
+ * 				- SUCCESS
+ * 				- ERROR
+ **********************************************************************/
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
+{
+	Status errorStatus = ERROR;
+
+	uint32_t uClk;
+	uint32_t d, m, bestd, bestm, tmp;
+	uint64_t best_divisor, divisor;
+	uint32_t current_error, best_error;
+	uint32_t recalcbaud;
+
+	/* get UART block clock */
+	uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
+
+	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+	* The formula is :
+	* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+	* It involves floating point calculations. That's the reason the formulae are adjusted with
+	* Multiply and divide method.*/
+	
+	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+	* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+	best_error = 0xFFFFFFFF; /* Worst case */
+	bestd = 0;
+	bestm = 0;
+	best_divisor = 0;
+	
+	for (m = 1 ; m <= 15 ;m++)
+	{
+		for (d = 0 ; d < m ; d++)
+		{
+			divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d));
+			current_error = divisor & 0xFFFFFFFF;
+
+			tmp = divisor>>32;
+
+			/* Adjust error */
+			if(current_error > ((uint32_t)1<<31))
+			{
+				current_error = -current_error;
+				tmp++;
+			}
+
+			/* Out of range */
+			if(tmp < 1 || tmp > 65536)
+				continue;
+
+			if( current_error < best_error)
+			{
+				best_error = current_error;
+				best_divisor = tmp;
+				bestd = d;
+				bestm = m;
+				
+				if(best_error == 0) 
+					break;
+			}
+		} /* end of inner for loop */
+
+		if (best_error == 0)
+			break;
+	} /* end of outer for loop  */
+
+	/* can not find best match */
+	if(best_divisor == 0) 
+		return ERROR;
+
+	recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
+
+	/* reuse best_error to evaluate baud error*/
+	if(baudrate > recalcbaud) 
+		best_error = baudrate - recalcbaud;
+	else 
+		best_error = recalcbaud -baudrate;
+
+	best_error = best_error * 100 / baudrate;
+
+	if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+			
+			((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor);
+			
+			((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor);
+			
+			/* Then reset DLAB bit */
+			((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+			
+			((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm)
+													| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+		}
+		else
+		{
+			UARTx->LCR |= UART_LCR_DLAB_EN;
+			
+			UARTx->DLM = UART_LOAD_DLM(best_divisor);
+			
+			UARTx->DLL = UART_LOAD_DLL(best_divisor);
+			
+			/* Then reset DLAB bit */
+			UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+			
+			UARTx->FDR = (UART_FDR_MULVAL(bestm) \
+							| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+		}
+		errorStatus = SUCCESS;
+	}
+
+	return errorStatus;
+}
+
+/* End of Private Functions ---------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup UART_Public_Functions
+ * @{
+ */
+/* UART Init/DeInit functions -------------------------------------------------*/
+/********************************************************************//**
+ * @brief		Initializes the UARTx peripheral according to the specified
+ *               parameters in the UART_ConfigStruct.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ *				- LPC_UART4: UART4 peripheral
+ * @param[in]	UART_ConfigStruct Pointer to a UART_CFG_Type structure
+*                    that contains the configuration information for the
+*                    specified UART peripheral.
+ * @return 		None
+ *********************************************************************/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
+{
+	uint32_t tmp;
+
+	if(UARTx == LPC_UART0)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
+	}
+	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
+	}
+	if(UARTx == LPC_UART2)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
+	}
+	if(UARTx == LPC_UART3)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
+	}
+
+	/* FIFOs are empty */
+	UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
+
+	// Disable FIFO
+	UARTx->FCR = 0;
+
+	// Dummy reading
+	while (UARTx->LSR & UART_LSR_RDR)
+	{
+		tmp = UARTx->RBR;
+	}
+
+	UARTx->TER = UART_TER_TXEN;
+
+	// Wait for current transmit complete
+	while (!(UARTx->LSR & UART_LSR_THRE));
+
+	// Disable Tx
+	UARTx->TER = 0;
+
+	// Disable interrupt
+	UARTx->IER = 0;
+
+	// Set LCR to default state
+	UARTx->LCR = 0;
+
+	// Set ACR to default state
+	UARTx->ACR = 0;
+
+	// Set RS485 control to default state
+	UARTx->RS485CTRL = 0;
+
+	// Set RS485 delay timer to default state
+	UARTx->RS485DLY = 0;
+
+	// Set RS485 addr match to default state
+	UARTx->ADRMATCH = 0;
+
+	// Dummy reading
+	tmp = UARTx->LSR;
+
+	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		// Set Modem Control to default state
+		((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
+
+		//Dummy Reading to Clear Status
+		tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
+	}
+	else
+	{
+		// Set IrDA to default state for all UART other than UART1
+		UARTx->ICR = 0;
+	}
+
+	// Set Line Control register ----------------------------
+
+	uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
+													& UART_LCR_BITMASK;
+	}
+	else
+	{
+		tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
+	}
+
+	switch (UART_ConfigStruct->Databits)
+	{
+		case UART_DATABIT_5:
+			tmp |= UART_LCR_WLEN5;
+			break;
+
+		case UART_DATABIT_6:
+			tmp |= UART_LCR_WLEN6;
+			break;
+
+		case UART_DATABIT_7:
+			tmp |= UART_LCR_WLEN7;
+			break;
+
+		case UART_DATABIT_8:
+
+		default:
+			tmp |= UART_LCR_WLEN8;
+			break;
+	}
+
+	if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
+	{
+		// Do nothing...
+	}
+	else
+	{
+		tmp |= UART_LCR_PARITY_EN;
+		switch (UART_ConfigStruct->Parity)
+		{
+			case UART_PARITY_ODD:
+				tmp |= UART_LCR_PARITY_ODD;
+				break;
+
+			case UART_PARITY_EVEN:
+				tmp |= UART_LCR_PARITY_EVEN;
+				break;
+
+			case UART_PARITY_SP_1:
+				tmp |= UART_LCR_PARITY_F_1;
+				break;
+
+			case UART_PARITY_SP_0:
+				tmp |= UART_LCR_PARITY_F_0;
+				break;
+
+			default:
+				break;
+		}
+	}
+
+	switch (UART_ConfigStruct->Stopbits)
+	{
+		case UART_STOPBIT_2:
+			tmp |= UART_LCR_STOPBIT_SEL;
+			break;
+
+		case UART_STOPBIT_1:
+
+		default:
+			// Do no thing
+			break;
+	}
+
+
+	// Write back to LCR, configure FIFO and Disable Tx
+	if (((LPC_UART1_TypeDef *)UARTx) ==  LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+	}
+	else
+	{
+		UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+	}
+}
+
+/*********************************************************************//**
+ * @brief		De-initializes the UARTx peripheral registers to their
+ *                  default reset values.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		None
+ **********************************************************************/
+void UART_DeInit(LPC_UART_TypeDef* UARTx)
+{
+	UART_TxCmd(UARTx, DISABLE);
+
+	if (UARTx == LPC_UART0)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
+	}
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
+	}
+
+	if (UARTx == LPC_UART2)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
+	}
+
+	if (UARTx == LPC_UART3)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
+	}
+}
+
+/*****************************************************************************//**
+* @brief		Fills each UART_InitStruct member with its default value:
+* 				- 9600 bps
+* 				- 8-bit data
+* 				- 1 Stopbit
+* 				- None Parity
+* @param[in]	UART_InitStruct Pointer to a UART_CFG_Type structure
+*                    which will be initialized.
+* @return		None
+*******************************************************************************/
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
+{
+	UART_InitStruct->Baud_rate = 9600;
+
+	UART_InitStruct->Databits = UART_DATABIT_8;
+
+	UART_InitStruct->Parity = UART_PARITY_NONE;
+
+	UART_InitStruct->Stopbits = UART_STOPBIT_1;
+}
+
+/* UART Send/Recieve functions -------------------------------------------------*/
+/*********************************************************************//**
+ * @brief		Transmit a single data through UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	Data	Data to transmit (must be 8-bit long)
+ * @return 		None
+ **********************************************************************/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT;
+	}
+	else
+	{
+		UARTx->THR = Data & UART_THR_MASKBIT;
+	}
+
+}
+
+
+/*********************************************************************//**
+ * @brief		Receive a single data from UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		Data received
+ **********************************************************************/
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT);
+	}
+	else
+	{
+		return (UARTx->RBR & UART_RBR_MASKBIT);
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Send a block of data via UART peripheral
+ * @param[in]	UARTx	Selected UART peripheral used to send data, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	txbuf 	Pointer to Transmit buffer
+ * @param[in]	buflen 	Length of Transmit buffer
+ * @param[in] 	flag 	Flag used in  UART transfer, should be
+ * 						NONE_BLOCKING or BLOCKING
+ * @return 		Number of bytes sent.
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+							uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+	uint32_t bToSend, bSent, timeOut, fifo_cnt;
+	uint8_t *pChar = txbuf;
+
+	bToSend = buflen;
+
+	// blocking mode
+	if (flag == BLOCKING)
+	{
+		bSent = 0;
+		while (bToSend)
+		{
+			timeOut = UART_BLOCKING_TIMEOUT;
+
+			// Wait for THR empty with timeout
+			while (!(UARTx->LSR & UART_LSR_THRE))
+			{
+				if (timeOut == 0)
+					break;
+
+				timeOut--;
+			}
+
+			// Time out!
+			if(timeOut == 0)
+				break;
+
+			fifo_cnt = UART_TX_FIFO_SIZE;
+
+			while (fifo_cnt && bToSend)
+			{
+				UART_SendByte(UARTx, (*pChar++));
+
+				fifo_cnt--;
+
+				bToSend--;
+
+				bSent++;
+			}
+		}
+	}
+
+	// None blocking mode
+	else
+	{
+		bSent = 0;
+		while (bToSend)
+		{
+			if (bToSend == 0)
+				break;
+
+			if (!(UARTx->LSR & UART_LSR_THRE))
+			{
+				break;
+			}
+
+			fifo_cnt = UART_TX_FIFO_SIZE;
+
+			while (fifo_cnt && bToSend)
+			{
+				UART_SendByte(UARTx, (*pChar++));
+
+				bToSend--;
+
+				fifo_cnt--;
+
+				bSent++;
+			}
+		}
+	}
+
+	return bSent;
+}
+
+/*********************************************************************//**
+ * @brief		Receive a block of data via UART peripheral
+ * @param[in]	UARTx	Selected UART peripheral used to send data,
+ * 				should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[out]	rxbuf 	Pointer to Received buffer
+ * @param[in]	buflen 	Length of Received buffer
+ * @param[in] 	flag 	Flag mode, should be NONE_BLOCKING or BLOCKING
+
+ * @return 		Number of bytes received
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf,
+								uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+	uint32_t bToRecv, bRecv, timeOut;
+	uint8_t *pChar = rxbuf;
+
+	bToRecv = buflen;
+
+	// Blocking mode
+	if (flag == BLOCKING)
+	{
+		bRecv = 0;
+		while (bToRecv)
+		{
+			timeOut = UART_BLOCKING_TIMEOUT;
+			while (!(UARTx->LSR & UART_LSR_RDR))
+			{
+				if (timeOut == 0)
+					break;
+
+				timeOut--;
+			}
+
+			// Time out!
+			if(timeOut == 0)
+				break;
+
+			// Get data from the buffer
+			(*pChar++) = UART_ReceiveByte(UARTx);
+
+			bToRecv--;
+
+			bRecv++;
+		}
+	}
+	// None blocking mode
+	else
+	{
+		bRecv = 0;
+		while (bToRecv)
+		{
+			if (!(UARTx->LSR & UART_LSR_RDR))
+			{
+				break;
+			}
+			else
+			{
+				(*pChar++) = UART_ReceiveByte(UARTx);
+
+				bRecv++;
+
+				bToRecv--;
+			}
+		}
+	}
+
+	return bRecv;
+}
+
+/*********************************************************************//**
+ * @brief		Force BREAK character on UART line, output pin UARTx TXD is
+				forced to logic 0.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		None
+ **********************************************************************/
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
+	}
+	else
+	{
+		UARTx->LCR |= UART_LCR_BREAK_EN;
+	}
+}
+
+
+/********************************************************************//**
+ * @brief 		Enable or disable specified UART interrupt.
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	UARTIntCfg	Specifies the interrupt flag,
+ * 				should be one of the following:
+				- UART_INTCFG_RBR 	:  RBR Interrupt enable
+				- UART_INTCFG_THRE 	:  THR Interrupt enable
+				- UART_INTCFG_RLS 	:  RX line status interrupt enable
+				- UART1_INTCFG_MS	:  Modem status interrupt enable (UART1 only)
+				- UART1_INTCFG_CTS	:  CTS1 signal transition interrupt enable (UART1 only)
+				- UART_INTCFG_ABEO 	:  Enables the end of auto-baud interrupt
+				- UART_INTCFG_ABTO 	:  Enables the auto-baud time-out interrupt
+ * @param[in]	NewState New state of specified UART interrupt type,
+ * 				should be:
+ * 				- ENALBE: Enable this UART interrupt type.
+* 				- DISALBE: Disable this UART interrupt type.
+ * @return 		None
+ *********************************************************************/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
+{
+	uint32_t tmp;
+
+	switch(UARTIntCfg)
+	{
+		case UART_INTCFG_RBR:
+			tmp = UART_IER_RBRINT_EN;
+			break;
+
+		case UART_INTCFG_THRE:
+			tmp = UART_IER_THREINT_EN;
+			break;
+
+		case UART_INTCFG_RLS:
+			tmp = UART_IER_RLSINT_EN;
+			break;
+
+		case UART1_INTCFG_MS:
+			tmp = UART1_IER_MSINT_EN;
+			break;
+
+		case UART1_INTCFG_CTS:
+			tmp = UART1_IER_CTSINT_EN;
+			break;
+
+		case UART_INTCFG_ABEO:
+			tmp = UART_IER_ABEOINT_EN;
+			break;
+
+		case UART_INTCFG_ABTO:
+			tmp = UART_IER_ABTOINT_EN;
+			break;
+	}
+
+	if (NewState == ENABLE)
+	{
+		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->IER |= tmp;
+		}
+		else
+		{
+			UARTx->IER |= tmp;
+		}
+	}
+	else
+	{
+		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK;
+		}
+		else
+		{
+			UARTx->IER &= (~tmp) & UART_IER_BITMASK;
+		}
+	}
+}
+
+
+/********************************************************************//**
+ * @brief 		Get current value of Line Status register in UART peripheral.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		Current value of Line Status register in UART peripheral.
+ * Note:	The return value of this function must be ANDed with each member in
+ * 			UART_LS_Type enumeration to determine current flag status
+ * 			corresponding to each Line status type. Because some flags in
+ * 			Line Status register will be cleared after reading, the next reading
+ * 			Line Status register could not be correct. So this function used to
+ * 			read Line status register in one time only, then the return value
+ * 			used to check all flags.
+ *********************************************************************/
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
+	}
+	else
+	{
+		return ((UARTx->LSR) & UART_LSR_BITMASK);
+	}
+}
+
+/********************************************************************//**
+ * @brief 		Get Interrupt Identification value
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		Current value of UART UIIR register in UART peripheral.
+ *********************************************************************/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
+{
+	return (UARTx->IIR & 0x03CF);
+}
+
+/*********************************************************************//**
+ * @brief		Check whether if UART is busy or not
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		RESET if UART is not busy, otherwise return SET.
+ **********************************************************************/
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
+{
+	if (UARTx->LSR & UART_LSR_TEMT)
+	{
+		return RESET;
+	}
+	else
+	{
+		return SET;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure FIFO function on selected UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	FIFOCfg	Pointer to a UART_FIFO_CFG_Type Structure that
+ * 						contains specified information about FIFO configuration
+ * @return 		none
+ **********************************************************************/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
+{
+	uint8_t tmp = 0;
+
+	tmp |= UART_FCR_FIFO_EN;
+
+	switch (FIFOCfg->FIFO_Level)
+	{
+		case UART_FIFO_TRGLEV0:
+			tmp |= UART_FCR_TRG_LEV0;
+			break;
+
+		case UART_FIFO_TRGLEV1:
+			tmp |= UART_FCR_TRG_LEV1;
+			break;
+
+		case UART_FIFO_TRGLEV2:
+			tmp |= UART_FCR_TRG_LEV2;
+			break;
+
+		case UART_FIFO_TRGLEV3:
+
+		default:
+			tmp |= UART_FCR_TRG_LEV3;
+			break;
+	}
+
+	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
+	{
+		tmp |= UART_FCR_TX_RS;
+	}
+
+	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
+	{
+		tmp |= UART_FCR_RX_RS;
+	}
+
+	if (FIFOCfg->FIFO_DMAMode == ENABLE)
+	{
+		tmp |= UART_FCR_DMAMODE_SEL;
+	}
+
+
+	//write to FIFO control register
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK;
+	}
+	else
+	{
+		UARTx->FCR = tmp & UART_FCR_BITMASK;
+	}
+}
+
+/*****************************************************************************//**
+* @brief		Fills each UART_FIFOInitStruct member with its default value:
+* 				- FIFO_DMAMode = DISABLE
+* 				- FIFO_Level = UART_FIFO_TRGLEV0
+* 				- FIFO_ResetRxBuf = ENABLE
+* 				- FIFO_ResetTxBuf = ENABLE
+* 				- FIFO_State = ENABLE
+
+* @param[in]	UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
+*                    which will be initialized.
+* @return		None
+*******************************************************************************/
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
+{
+	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
+
+	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
+
+	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
+
+	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
+}
+
+
+/*********************************************************************//**
+ * @brief		Start/Stop Auto Baudrate activity
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	ABConfigStruct	A pointer to UART_AB_CFG_Type structure that
+ * 								contains specified information about UART
+ * 								auto baudrate configuration
+ * @param[in]	NewState New State of Auto baudrate activity, should be:
+ * 				- ENABLE: Start this activity
+ *				- DISABLE: Stop this activity
+ * Note:		Auto-baudrate mode enable bit will be cleared once this mode
+ * 				completed.
+ * @return 		none
+ **********************************************************************/
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct,
+							FunctionalState NewState)
+{
+	uint32_t tmp;
+
+	tmp = 0;
+	if (NewState == ENABLE)
+	{
+		if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1)
+		{
+			tmp |= UART_ACR_MODE;
+		}
+		if (ABConfigStruct->AutoRestart == ENABLE)
+		{
+			tmp |= UART_ACR_AUTO_RESTART;
+		}
+	}
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		if (NewState == ENABLE)
+		{
+			// Clear DLL and DLM value
+			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+
+			((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
+
+			((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
+
+			((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
+
+			// FDR value must be reset to default value
+			((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
+
+			((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
+		}
+		else
+		{
+			((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+		}
+	}
+	else
+	{
+		if (NewState == ENABLE)
+		{
+			// Clear DLL and DLM value
+			UARTx->LCR |= UART_LCR_DLAB_EN;
+
+			UARTx->DLL = 0;
+
+			UARTx->DLM = 0;
+
+			UARTx->LCR &= ~UART_LCR_DLAB_EN;
+
+			// FDR value must be reset to default value
+			UARTx->FDR = 0x10;
+
+			UARTx->ACR = UART_ACR_START | tmp;
+		}
+		else
+		{
+			UARTx->ACR = 0;
+		}
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Clear Autobaud Interrupt Pending
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	ABIntType	type of auto-baud interrupt, should be:
+ * 				- UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
+ * 				- UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
+ * @return 		none
+ **********************************************************************/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		UARTx->ACR |= ABIntType;
+	}
+	else
+		UARTx->ACR |= ABIntType;
+}
+
+/*********************************************************************//**
+ * @brief		Enable/Disable transmission on UART TxD pin
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	NewState New State of Tx transmission function, should be:
+ * 				- ENABLE: Enable this function
+				- DISABLE: Disable this function
+ * @return none
+ **********************************************************************/
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
+		}
+		else
+		{
+			UARTx->TER |= UART_TER_TXEN;
+		}
+	}
+	else
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+		}
+		else
+		{
+			UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+		}
+	}
+}
+
+/* UART IrDA functions ---------------------------------------------------*/
+/*********************************************************************//**
+ * @brief		Enable or disable inverting serial input function of IrDA
+ * 				on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	NewState New state of inverting serial input, should be:
+ * 				- ENABLE: Enable this function.
+ * 				- DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->ICR |= UART_ICR_IRDAINV;
+	}
+	else if (NewState == DISABLE)
+	{
+		UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Enable or disable IrDA function on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	NewState New state of IrDA function, should be:
+ * 				- ENABLE: Enable this function.
+ * 				- DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->ICR |= UART_ICR_IRDAEN;
+	}
+	else
+	{
+		UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure Pulse divider for IrDA function on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	PulseDiv Pulse Divider value from Peripheral clock,
+ * 				should be one of the following:
+				- UART_IrDA_PULSEDIV2 	: Pulse width = 2 * Tpclk
+				- UART_IrDA_PULSEDIV4 	: Pulse width = 4 * Tpclk
+				- UART_IrDA_PULSEDIV8 	: Pulse width = 8 * Tpclk
+				- UART_IrDA_PULSEDIV16 	: Pulse width = 16 * Tpclk
+				- UART_IrDA_PULSEDIV32 	: Pulse width = 32 * Tpclk
+				- UART_IrDA_PULSEDIV64 	: Pulse width = 64 * Tpclk
+				- UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
+				- UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
+
+ * @return none
+ **********************************************************************/
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
+{
+	uint32_t tmp, tmp1;
+
+	tmp1 = UART_ICR_PULSEDIV(PulseDiv);
+
+	tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7));
+
+	tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
+
+	UARTx->ICR = tmp & UART_ICR_BITMASK;
+}
+
+/* UART1 FullModem function ---------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief		Force pin DTR/RTS corresponding to given state (Full modem mode)
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	Pin	Pin that NewState will be applied to, should be:
+ * 				- UART1_MODEM_PIN_DTR: DTR pin.
+ * 				- UART1_MODEM_PIN_RTS: RTS pin.
+ * @param[in]	NewState New State of DTR/RTS pin, should be:
+ * 				- INACTIVE: Force the pin to inactive signal.
+				- ACTIVE: Force the pin to active signal.
+ * @return none
+ **********************************************************************/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx,
+													UART_MODEM_PIN_Type Pin,
+													UART1_SignalState NewState)
+{
+	uint8_t tmp = 0;
+
+	switch (Pin)
+	{
+		case UART1_MODEM_PIN_DTR:
+			tmp = UART1_MCR_DTR_CTRL;
+			break;
+
+		case UART1_MODEM_PIN_RTS:
+			tmp = UART1_MCR_RTS_CTRL;
+			break;
+
+		default:
+			break;
+	}
+
+	if (NewState == ACTIVE)
+	{
+		UARTx->MCR |= tmp;
+	}
+	else
+	{
+		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure Full Modem mode for UART peripheral
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	Mode Full Modem mode, should be:
+ * 				- UART1_MODEM_MODE_LOOPBACK: Loop back mode.
+ * 				- UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
+ * 				- UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
+ * @param[in]	NewState New State of this mode, should be:
+ * 				- ENABLE: Enable this mode.
+				- DISABLE: Disable this mode.
+ * @return none
+ **********************************************************************/
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode,
+											FunctionalState NewState)
+{
+	uint8_t tmp;
+
+	switch(Mode)
+	{
+		case UART1_MODEM_MODE_LOOPBACK:
+			tmp = UART1_MCR_LOOPB_EN;
+			break;
+
+		case UART1_MODEM_MODE_AUTO_RTS:
+			tmp = UART1_MCR_AUTO_RTS_EN;
+			break;
+
+		case UART1_MODEM_MODE_AUTO_CTS:
+			tmp = UART1_MCR_AUTO_CTS_EN;
+			break;
+
+		default:
+			break;
+	}
+
+	if (NewState == ENABLE)
+	{
+		UARTx->MCR |= tmp;
+	}
+	else
+	{
+		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Get current status of modem status register
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @return 		Current value of modem status register
+ * Note:	The return value of this function must be ANDed with each member
+ * 			UART_MODEM_STAT_type enumeration to determine current flag status
+ * 			corresponding to each modem flag status. Because some flags in
+ * 			modem status register will be cleared after reading, the next reading
+ * 			modem register could not be correct. So this function used to
+ * 			read modem status register in one time only, then the return value
+ * 			used to check all flags.
+ **********************************************************************/
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
+{
+	return ((UARTx->MSR) & UART1_MSR_BITMASK);
+}
+
+
+/* UART RS485 functions --------------------------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief		Configure UART peripheral in RS485 mode according to the specified
+*               parameters in the RS485ConfigStruct.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
+*                    that contains the configuration information for specified UART
+*                    in RS485 mode.
+ * @return		None
+ **********************************************************************/
+void UART_RS485Config(LPC_UART_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
+{
+	uint32_t tmp;
+
+	tmp = 0;
+
+	// If Auto Direction Control is enabled -  This function is used in Master mode
+	if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_DCTRL_EN;
+
+		// Set polar
+		if (RS485ConfigStruct->DirCtrlPol_Level == SET)
+		{
+			tmp |= UART1_RS485CTRL_OINV_1;
+		}
+
+		// Set pin according to. This condition is only with UART1. The others are used
+		// OE pin as default for control the direction of RS485 buffer IC
+		if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
+								&& ((LPC_UART1_TypeDef *)UARTx == LPC_UART1))
+		{
+			tmp |= UART1_RS485CTRL_SEL_DTR;
+		}
+
+		// Fill delay time
+		UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
+	}
+
+	// MultiDrop mode is enable
+	if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_NMM_EN;
+	}
+
+	// Auto Address Detect function
+	if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_AADEN;
+
+		// Fill Match Address
+		UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
+	}
+
+	// Receiver is disable
+	if (RS485ConfigStruct->Rx_State == DISABLE)
+	{
+		tmp |= UART1_RS485CTRL_RX_DIS;
+	}
+
+	// write back to RS485 control register
+	UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
+
+	// Enable Parity function and leave parity in stick '0' parity as default
+	UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
+}
+
+/*********************************************************************//**
+ * @brief		Enable/Disable receiver in RS485 module in UART1
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	NewState	New State of command, should be:
+ * 							- ENABLE: Enable this function.
+ * 							- DISABLE: Disable this function.
+ * @return		None
+ **********************************************************************/
+void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
+	}
+	else
+	{
+		UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Send data on RS485 bus with specified parity stick value (9-bit mode).
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	pDatFrm 	Pointer to data frame.
+ * @param[in]	size		Size of data.
+ * @param[in]	ParityStick	Parity Stick value, should be 0 or 1.
+ * @return		None
+ **********************************************************************/
+uint32_t UART_RS485Send(LPC_UART_TypeDef *UARTx, uint8_t *pDatFrm,
+											uint32_t size, uint8_t ParityStick)
+{
+	uint8_t tmp, save;
+	uint32_t cnt;
+
+	if (ParityStick)
+	{
+		save = tmp = UARTx->LCR & UART_LCR_BITMASK;
+
+		tmp &= ~(UART_LCR_PARITY_EVEN);
+
+		UARTx->LCR = tmp;
+
+		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+
+		while (!(UARTx->LSR & UART_LSR_TEMT));
+
+		UARTx->LCR = save;
+	}
+	else
+	{
+		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+
+		while (!(UARTx->LSR & UART_LSR_TEMT));
+	}
+
+	return cnt;
+}
+
+/*********************************************************************//**
+ * @brief		Send Slave address frames on RS485 bus.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	SlvAddr Slave Address.
+ * @return		None
+ **********************************************************************/
+void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr)
+{
+	UART_RS485Send(UARTx, &SlvAddr, 1, 1);
+}
+
+/*********************************************************************//**
+ * @brief		Send Data frames on RS485 bus.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	pData Pointer to data to be sent.
+ * @param[in]	size Size of data frame to be sent.
+ * @return		None
+ **********************************************************************/
+uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size)
+{
+	return (UART_RS485Send(UARTx, pData, size, 0));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* --------------------------------- End Of File ------------------------------ */
+

bsp/lpc178x/drivers/lpc177x_8x_uart.h

@@ -0,0 +1,697 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_uart.h			2011-06-02
+*//**
+* @file		lpc177x_8x_uart.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for UART firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART	UART (Universal Asynchronous Receiver/Transmitter)
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_UART_H_
+#define __LPC177X_8X_UART_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros  UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT			(0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR	(3)			/*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+/** UART Received Buffer mask bit (8 bits) */
+#define UART_RBR_MASKBIT   	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+/** UART Transmit Holding mask bit (8 bits) */
+#define UART_THR_MASKBIT   	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+/** Macro for loading least significant halfs of divisors */
+#define UART_LOAD_DLL(div)	((div) & 0xFF)
+/** Divisor latch LSB bit mask */
+#define UART_DLL_MASKBIT	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+/** Divisor latch MSB bit mask */
+#define UART_DLM_MASKBIT	((uint8_t)0xFF)
+/** Macro for loading most significant halfs of divisors */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+/** RBR Interrupt enable*/
+#define UART_IER_RBRINT_EN		((uint32_t)(1<<0))
+/** THR Interrupt enable*/
+#define UART_IER_THREINT_EN		((uint32_t)(1<<1))
+/** RX line status interrupt enable*/
+#define UART_IER_RLSINT_EN		((uint32_t)(1<<2))
+/** Modem status interrupt enable */
+#define UART1_IER_MSINT_EN		((uint32_t)(1<<3))
+/** CTS1 signal transition interrupt enable */
+#define UART1_IER_CTSINT_EN		((uint32_t)(1<<7))
+/** Enables the end of auto-baud interrupt */
+#define UART_IER_ABEOINT_EN		((uint32_t)(1<<8))
+/** Enables the auto-baud time-out interrupt */
+#define UART_IER_ABTOINT_EN		((uint32_t)(1<<9))
+/** UART interrupt enable register bit mask */
+#define UART_IER_BITMASK		((uint32_t)(0x307))
+/** UART1 interrupt enable register bit mask */
+#define UART1_IER_BITMASK		((uint32_t)(0x38F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+/** Interrupt Status - Active low */
+#define UART_IIR_INTSTAT_PEND	((uint32_t)(1<<0))
+/** Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RLS		((uint32_t)(3<<1))
+/** Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_RDA		((uint32_t)(2<<1))
+/** Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_CTI		((uint32_t)(6<<1))
+/** Interrupt identification: THRE interrupt*/
+#define UART_IIR_INTID_THRE		((uint32_t)(1<<1))
+/** Interrupt identification: Modem interrupt*/
+#define UART1_IIR_INTID_MODEM	((uint32_t)(0<<1))
+/** Interrupt identification: Interrupt ID mask */
+#define UART_IIR_INTID_MASK		((uint32_t)(7<<1))
+/** These bits are equivalent to UnFCR[0] */
+#define UART_IIR_FIFO_EN		((uint32_t)(3<<6))
+/** End of auto-baud interrupt */
+#define UART_IIR_ABEO_INT		((uint32_t)(1<<8))
+/** Auto-baud time-out interrupt */
+#define UART_IIR_ABTO_INT		((uint32_t)(1<<9))
+/** UART interrupt identification register bit mask */
+#define UART_IIR_BITMASK		((uint32_t)(0x3CF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+/** UART FIFO enable */
+#define UART_FCR_FIFO_EN		((uint8_t)(1<<0))
+/** UART FIFO RX reset */
+#define UART_FCR_RX_RS			((uint8_t)(1<<1))
+/** UART FIFO TX reset */
+#define UART_FCR_TX_RS			((uint8_t)(1<<2))
+/** UART DMA mode selection */
+#define UART_FCR_DMAMODE_SEL 	((uint8_t)(1<<3))
+/** UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV0		((uint8_t)(0))
+/** UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV1		((uint8_t)(1<<6))
+/** UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV2		((uint8_t)(2<<6))
+/** UART FIFO trigger level 3: 14 character */
+#define UART_FCR_TRG_LEV3		((uint8_t)(3<<6))
+/** UART FIFO control bit mask */
+#define UART_FCR_BITMASK		((uint8_t)(0xCF))
+
+#define UART_TX_FIFO_SIZE		(16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+/** UART 5 bit data mode */
+#define UART_LCR_WLEN5     		((uint8_t)(0))
+/** UART 6 bit data mode */
+#define UART_LCR_WLEN6     		((uint8_t)(1<<0))
+/** UART 7 bit data mode */
+#define UART_LCR_WLEN7     		((uint8_t)(2<<0))
+/** UART 8 bit data mode */
+#define UART_LCR_WLEN8     		((uint8_t)(3<<0))
+/** UART Two Stop Bits Select */
+#define UART_LCR_STOPBIT_SEL	((uint8_t)(1<<2))
+/** UART Parity Enable */
+#define UART_LCR_PARITY_EN		((uint8_t)(1<<3))
+/** UART Odd Parity Select */
+#define UART_LCR_PARITY_ODD		((uint8_t)(0))
+/** UART Even Parity Select */
+#define UART_LCR_PARITY_EVEN	((uint8_t)(1<<4))
+/** UART force 1 stick parity */
+#define UART_LCR_PARITY_F_1		((uint8_t)(2<<4))
+/** UART force 0 stick parity */
+#define UART_LCR_PARITY_F_0		((uint8_t)(3<<4))
+/** UART Transmission Break enable */
+#define UART_LCR_BREAK_EN		((uint8_t)(1<<6))
+/** UART Divisor Latches Access bit enable */
+#define UART_LCR_DLAB_EN		((uint8_t)(1<<7))
+/** UART line control bit mask */
+#define UART_LCR_BITMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+/** Source for modem output pin DTR */
+#define UART1_MCR_DTR_CTRL		((uint8_t)(1<<0))
+/** Source for modem output pin RTS */
+#define UART1_MCR_RTS_CTRL		((uint8_t)(1<<1))
+/** Loop back mode select */
+#define UART1_MCR_LOOPB_EN		((uint8_t)(1<<4))
+/** Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_RTS_EN	((uint8_t)(1<<6))
+/** Enable Auto CTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN	((uint8_t)(1<<7))
+/** UART1 bit mask value */
+#define UART1_MCR_BITMASK		((uint8_t)(0x0F3))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+/** Line status register: Receive data ready*/
+#define UART_LSR_RDR		((uint8_t)(1<<0))
+/** Line status register: Overrun error*/
+#define UART_LSR_OE			((uint8_t)(1<<1))
+/** Line status register: Parity error*/
+#define UART_LSR_PE			((uint8_t)(1<<2))
+/** Line status register: Framing error*/
+#define UART_LSR_FE			((uint8_t)(1<<3))
+/** Line status register: Break interrupt*/
+#define UART_LSR_BI			((uint8_t)(1<<4))
+/** Line status register: Transmit holding register empty*/
+#define UART_LSR_THRE		((uint8_t)(1<<5))
+/** Line status register: Transmitter empty*/
+#define UART_LSR_TEMT		((uint8_t)(1<<6))
+/** Error in RX FIFO*/
+#define UART_LSR_RXFE		((uint8_t)(1<<7))
+/** UART Line status bit mask */
+#define UART_LSR_BITMASK	((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+/** Set upon state change of input CTS */
+#define UART1_MSR_DELTA_CTS		((uint8_t)(1<<0))
+/** Set upon state change of input DSR */
+#define UART1_MSR_DELTA_DSR		((uint8_t)(1<<1))
+/** Set upon low to high transition of input RI */
+#define UART1_MSR_LO2HI_RI		((uint8_t)(1<<2))
+/** Set upon state change of input DCD */
+#define UART1_MSR_DELTA_DCD		((uint8_t)(1<<3))
+/** Clear To Send State */
+#define UART1_MSR_CTS			((uint8_t)(1<<4))
+/** Data Set Ready State */
+#define UART1_MSR_DSR			((uint8_t)(1<<5))
+/** Ring Indicator State */
+#define UART1_MSR_RI			((uint8_t)(1<<6))
+/** Data Carrier Detect State */
+#define UART1_MSR_DCD			((uint8_t)(1<<7))
+/** MSR register bit-mask value */
+#define UART1_MSR_BITMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+/** UART Scratch Pad bit mask */
+#define UART_SCR_BIMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+/** UART Auto-baud start */
+#define UART_ACR_START				((uint32_t)(1<<0))
+/** UART Auto baudrate Mode 1 */
+#define UART_ACR_MODE				((uint32_t)(1<<1))
+/** UART Auto baudrate restart */
+#define UART_ACR_AUTO_RESTART		((uint32_t)(1<<2))
+/** UART End of auto-baud interrupt clear */
+#define UART_ACR_ABEOINT_CLR		((uint32_t)(1<<8))
+/** UART Auto-baud time-out interrupt clear */
+#define UART_ACR_ABTOINT_CLR		((uint32_t)(1<<9))
+/** UART Auto Baudrate register bit mask */
+#define UART_ACR_BITMASK			((uint32_t)(0x307))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+/** IrDA mode enable */
+#define UART_ICR_IRDAEN			((uint32_t)(1<<0))
+/** IrDA serial input inverted */
+#define UART_ICR_IRDAINV		((uint32_t)(1<<1))
+/** IrDA fixed pulse width mode */
+#define UART_ICR_FIXPULSE_EN	((uint32_t)(1<<2))
+/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_PULSEDIV(n)	((uint32_t)((n&0x07)<<3))
+/** UART IRDA bit mask */
+#define UART_ICR_BITMASK		((uint32_t)(0x3F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+/** Baud-rate generation pre-scaler divisor */
+#define UART_FDR_DIVADDVAL(n)	((uint32_t)(n&0x0F))
+/** Baud-rate pre-scaler multiplier value */
+#define UART_FDR_MULVAL(n)		((uint32_t)((n<<4)&0xF0))
+/** UART Fractional Divider register bit mask */
+#define UART_FDR_BITMASK		((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+/** Transmit enable bit */
+#define UART_TER_TXEN			((uint8_t)(1<<7))
+/** UART Transmit Enable Register bit mask */
+#define UART_TER_BITMASK		((uint8_t)(0x80))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
+#define UART1_RS485CTRL_NMM_EN		((uint32_t)(1<<0))
+/** The receiver is disabled */
+#define UART1_RS485CTRL_RX_DIS		((uint32_t)(1<<1))
+/** Auto Address Detect (AAD) is enabled */
+#define UART1_RS485CTRL_AADEN		((uint32_t)(1<<2))
+/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
+#define UART1_RS485CTRL_SEL_DTR		((uint32_t)(1<<3))
+/** Enable Auto Direction Control */
+#define UART1_RS485CTRL_DCTRL_EN	((uint32_t)(1<<4))
+/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 
+The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
+#define UART1_RS485CTRL_OINV_1		((uint32_t)(1<<5))
+
+/** RS485 control bit-mask value */
+#define UART1_RS485CTRL_BITMASK		((uint32_t)(0x3F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) 	/**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART1_RS485DLY_BITMASK		((uint8_t)(0xFF)) 	/** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+/** Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_RXFIFOLVL(n)	((uint32_t)(n&0x0F))
+/** Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)	((uint32_t)((n>>8)&0x0F))
+/** UART FIFO Level Register bit mask */
+#define UART_FIFOLVL_BITMASK		((uint32_t)(0x0F0F))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+	UART_DATABIT_5		= 0,     		/*!< UART 5 bit data mode */
+	UART_DATABIT_6,		     			/*!< UART 6 bit data mode */
+	UART_DATABIT_7,		     			/*!< UART 7 bit data mode */
+	UART_DATABIT_8		     			/*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+	UART_STOPBIT_1		= (0),   					/*!< UART 1 Stop Bits Select */
+	UART_STOPBIT_2,		 							/*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+	UART_PARITY_NONE 	= 0,					/*!< No parity */
+	UART_PARITY_ODD,	 						/*!< Odd parity */
+	UART_PARITY_EVEN, 							/*!< Even parity */
+	UART_PARITY_SP_1, 							/*!< Forced "1" stick parity */
+	UART_PARITY_SP_0 							/*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+	UART_FIFO_TRGLEV0 = 0,	/*!< UART FIFO trigger level 0: 1 character */
+	UART_FIFO_TRGLEV1, 		/*!< UART FIFO trigger level 1: 4 character */
+	UART_FIFO_TRGLEV2,		/*!< UART FIFO trigger level 2: 8 character */
+	UART_FIFO_TRGLEV3		/*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+	UART_INTCFG_RBR = 0,	/*!< RBR Interrupt enable*/
+	UART_INTCFG_THRE,		/*!< THR Interrupt enable*/
+	UART_INTCFG_RLS,		/*!< RX line status interrupt enable*/
+	UART1_INTCFG_MS,		/*!< Modem status interrupt enable (UART1 only) */
+	UART1_INTCFG_CTS,		/*!< CTS1 signal transition interrupt enable (UART1 only) */
+	UART_INTCFG_ABEO,		/*!< Enables the end of auto-baud interrupt */
+	UART_INTCFG_ABTO		/*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+	UART_LINESTAT_RDR	= UART_LSR_RDR,			/*!<Line status register: Receive data ready*/
+	UART_LINESTAT_OE	= UART_LSR_OE,			/*!<Line status register: Overrun error*/
+	UART_LINESTAT_PE	= UART_LSR_PE,			/*!<Line status register: Parity error*/
+	UART_LINESTAT_FE	= UART_LSR_FE,			/*!<Line status register: Framing error*/
+	UART_LINESTAT_BI	= UART_LSR_BI,			/*!<Line status register: Break interrupt*/
+	UART_LINESTAT_THRE	= UART_LSR_THRE,		/*!<Line status register: Transmit holding register empty*/
+	UART_LINESTAT_TEMT	= UART_LSR_TEMT,		/*!<Line status register: Transmitter empty*/
+	UART_LINESTAT_RXFE	= UART_LSR_RXFE			/*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_MODE0				= 0,			/**< UART Auto baudrate Mode 0 */
+	UART_AUTOBAUD_MODE1,							/**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+	UART_AB_MODE_Type	ABMode;			/**< Autobaudrate mode */
+	FunctionalState		AutoRestart;	/**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_INTSTAT_ABEO		= UART_IIR_ABEO_INT,		/**< UART End of auto-baud interrupt  */
+	UART_AUTOBAUD_INTSTAT_ABTO		= UART_IIR_ABTO_INT			/**< UART Auto-baud time-out interrupt  */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum 
+{
+	/** Pulse width = 2 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV2		= 0,
+
+	/** Pulse width = 4 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV4,
+
+	/** Pulse width = 8 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV8,
+
+	/** Pulse width = 16 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV16,
+
+	/** Pulse width = 32 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV32,
+
+	/**< Pulse width = 64 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV64,
+
+	/**< Pulse width = 128 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV128,
+
+	/**< Pulse width = 256 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV256
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  Signal states definition
+**********************************************************************/
+typedef enum {
+	INACTIVE = 0,			/* In-active state */
+	ACTIVE = !INACTIVE 		/* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+	UART1_MODEM_STAT_DELTA_CTS	= UART1_MSR_DELTA_CTS,		/*!< Set upon state change of input CTS */
+	UART1_MODEM_STAT_DELTA_DSR	= UART1_MSR_DELTA_DSR,		/*!< Set upon state change of input DSR */
+	UART1_MODEM_STAT_LO2HI_RI	= UART1_MSR_LO2HI_RI,		/*!< Set upon low to high transition of input RI */
+	UART1_MODEM_STAT_DELTA_DCD	= UART1_MSR_DELTA_DCD,		/*!< Set upon state change of input DCD */
+	UART1_MODEM_STAT_CTS		= UART1_MSR_CTS,			/*!< Clear To Send State */
+	UART1_MODEM_STAT_DSR		= UART1_MSR_DSR,			/*!< Data Set Ready State */
+	UART1_MODEM_STAT_RI			= UART1_MSR_RI,				/*!< Ring Indicator State */
+	UART1_MODEM_STAT_DCD		= UART1_MSR_DCD				/*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+	UART1_MODEM_PIN_DTR			= 0,		/*!< Source for modem output pin DTR */
+	UART1_MODEM_PIN_RTS						/*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+	UART1_MODEM_MODE_LOOPBACK	= 0,		/*!< Loop back mode select */
+	UART1_MODEM_MODE_AUTO_RTS,				/*!< Enable Auto RTS flow-control */
+	UART1_MODEM_MODE_AUTO_CTS 				/*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+	UART1_RS485_DIRCTRL_RTS = 0,	/**< Pin RTS is used for direction control */
+	UART1_RS485_DIRCTRL_DTR			/**< Pin DTR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+  uint32_t Baud_rate;   		/**< UART baud rate */
+  UART_PARITY_Type Parity;    	/**< Parity selection, should be:
+							   - UART_PARITY_NONE: No parity
+							   - UART_PARITY_ODD: Odd parity
+							   - UART_PARITY_EVEN: Even parity
+							   - UART_PARITY_SP_1: Forced "1" stick parity
+							   - UART_PARITY_SP_0: Forced "0" stick parity
+							   */
+  UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
+							   - UART_DATABIT_5: UART 5 bit data mode
+							   - UART_DATABIT_6: UART 6 bit data mode
+							   - UART_DATABIT_7: UART 7 bit data mode
+							   - UART_DATABIT_8: UART 8 bit data mode
+							   */
+  UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
+							   - UART_STOPBIT_1: UART 1 Stop Bits Select
+							   - UART_STOPBIT_2: UART 2 Stop Bits Select
+							   */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+	FunctionalState FIFO_ResetRxBuf;	/**< Reset Rx FIFO command state , should be:
+										 - ENABLE: Reset Rx FIFO in UART
+										 - DISABLE: Do not reset Rx FIFO  in UART
+										 */
+	FunctionalState FIFO_ResetTxBuf;	/**< Reset Tx FIFO command state , should be:
+										 - ENABLE: Reset Tx FIFO in UART
+										 - DISABLE: Do not reset Tx FIFO  in UART
+										 */
+	FunctionalState FIFO_DMAMode;		/**< DMA mode, should be:
+										 - ENABLE: Enable DMA mode in UART
+										 - DISABLE: Disable DMA mode in UART
+										 */
+	UART_FITO_LEVEL_Type FIFO_Level;	/**< Rx FIFO trigger level, should be:
+										- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+										- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+										- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+										- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+										*/
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+	FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+													- ENABLE: Enable this function.
+													- DISABLE: Disable this function. */
+	FunctionalState Rx_State;					/*!< Receiver State:
+													- ENABLE: Enable Receiver.
+													- DISABLE: Disable Receiver. */
+	FunctionalState AutoAddrDetect_State;		/*!< Auto Address Detect mode state:
+												- ENABLE: ENABLE this function.
+												- DISABLE: Disable this function. */
+	FunctionalState AutoDirCtrl_State;			/*!< Auto Direction Control State:
+												- ENABLE: Enable this function.
+												- DISABLE: Disable this function. */
+	UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;		/*!< If direction control is enabled, state:
+												- UART1_RS485_DIRCTRL_RTS:
+												pin RTS is used for direction control.
+												- UART1_RS485_DIRCTRL_DTR:
+												pin DTR is used for direction control. */
+	 SetState DirCtrlPol_Level;					/*!< Polarity of the direction control signal on
+												the RTS (or DTR) pin:
+												- RESET: The direction control pin will be driven
+												to logic "0" when the transmitter has data to be sent.
+												- SET: The direction control pin will be driven
+												to logic "1" when the transmitter has data to be sent. */
+	uint8_t MatchAddrValue;					/*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+	uint8_t DelayValue;						/*!< delay time is in periods of the baud clock, 8-bit long */
+} UART1_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_UART_TypeDef* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART get information functions -----------------------------------------------*/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
+				FunctionalState NewState);
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
+
+/* UART Auto-baud functions -----------------------------------------------------*/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+				FunctionalState NewState);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+							UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+							FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_UART_TypeDef *UARTx,
+									UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC177X_8X_UART_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

bsp/lpc178x/drivers/lpc_types.h

@@ -0,0 +1,201 @@
+/**********************************************************************
+* $Id$		lpc_types.h			2011-06-02
+*//**
+* @file		lpc_types.h
+* @brief	Contains the NXP ABL typedefs for C standard types.
+*			It is intended to be used in ISO C conforming development
+*			environments and checks for this insofar as it is possible
+*			to do so.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+#ifndef __LPC_TYPES_H
+#define __LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+/** @defgroup LPC_Type_Def Data Types Definitions
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+ 
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types Basic Public Data Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+	NONE_BLOCKING = 0,		/**< None Blocking type */
+	BLOCKING,				/**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros  Basic Public Macros
+ * @{
+ */
+
+/** _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/** Set bit macro */
+#define _BIT(n)	(1<<n)
+
+/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef	uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef	int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef	uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef	int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* __LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

bsp/lpc178x/drivers/uart.c

@@ -0,0 +1,353 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-03-08     Bernard      The first version for LPC17xx
+ * 2010-05-02     Aozima       update CMSIS to 130
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "LPC177x_8x.h"
+#include "lpc177x_8x_uart.h"
+#include "lpc177x_8x_pinsel.h"
+
+#define IER_RBR		0x01
+#define IER_THRE	0x02
+#define IER_RLS		0x04
+
+#define IIR_PEND	0x01
+#define IIR_RLS		0x03
+#define IIR_RDA		0x02
+#define IIR_CTI		0x06
+#define IIR_THRE	0x01
+
+#define LSR_RDR		0x01
+#define LSR_OE		0x02
+#define LSR_PE		0x04
+#define LSR_FE		0x08
+#define LSR_BI		0x10
+#define LSR_THRE	0x20
+#define LSR_TEMT	0x40
+#define LSR_RXFE	0x80
+
+/**
+ * @addtogroup LPC11xx
+ */
+
+/*@{*/
+
+#define UART_BAUDRATE   115200
+#define LPC_UART		LPC_UART0
+#define UART_IRQn		UART0_IRQn
+
+struct rt_uart_lpc
+{
+	struct rt_device parent;
+
+	LPC_UART_TypeDef * UART;
+
+	/* buffer for reception */
+	rt_uint8_t read_index, save_index;
+	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+};
+
+#ifdef RT_USING_UART1
+struct rt_uart_lpc uart1_device;
+#endif
+
+void UART0_IRQHandler(void)
+{
+//	rt_ubase_t level, iir;
+//    struct rt_uart_lpc* uart = &uart_device;
+//
+//    /* read IIR and clear it */
+//	iir = LPC_UART->IIR;
+//
+//	iir >>= 1;			    /* skip pending bit in IIR */
+//	iir &= 0x07;			/* check bit 1~3, interrupt identification */
+//
+//	if (iir == IIR_RDA)	    /* Receive Data Available */
+//	{
+//		/* Receive Data Available */
+//        uart->rx_buffer[uart->save_index] = LPC_UART->RBR;
+//
+//        level = rt_hw_interrupt_disable();
+//		uart->save_index ++;
+//        if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+//            uart->save_index = 0;
+//        rt_hw_interrupt_enable(level);
+//
+//		/* invoke callback */
+//		if(uart->parent.rx_indicate != RT_NULL)
+//		{
+//		    rt_size_t length;
+//		    if (uart->read_index > uart->save_index)
+//                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+//            else
+//                length = uart->save_index - uart->read_index;
+//
+//            uart->parent.rx_indicate(&uart->parent, length);
+//		}
+//	}
+//
+//	return;
+}
+
+static rt_err_t rt_uart_init (rt_device_t dev)
+{
+//	rt_uint32_t Fdiv;
+//	rt_uint32_t pclkdiv, pclk;
+//
+//	/* Init UART Hardware */
+//	if (LPC_UART == LPC_UART0)
+//	{
+//		LPC_PINCON->PINSEL0 &= ~0x000000F0;
+//		LPC_PINCON->PINSEL0 |= 0x00000050;  /* RxD0 is P0.3 and TxD0 is P0.2 */
+//		/* By default, the PCLKSELx value is zero, thus, the PCLK for
+//		all the peripherals is 1/4 of the SystemFrequency. */
+//		/* Bit 6~7 is for UART0 */
+//		pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
+//		switch ( pclkdiv )
+//		{
+//		  case 0x00:
+//		  default:
+//			pclk = SystemCoreClock/4;
+//			break;
+//		  case 0x01:
+//			pclk = SystemCoreClock;
+//			break;
+//		  case 0x02:
+//			pclk = SystemCoreClock/2;
+//			break;
+//		  case 0x03:
+//			pclk = SystemCoreClock/8;
+//			break;
+//		}
+//
+//	    LPC_UART0->LCR = 0x83;		/* 8 bits, no Parity, 1 Stop bit */
+//		Fdiv = ( pclk / 16 ) / UART_BAUDRATE;	/*baud rate */
+//	    LPC_UART0->DLM = Fdiv / 256;
+//	    LPC_UART0->DLL = Fdiv % 256;
+//		LPC_UART0->LCR = 0x03;		/* DLAB = 0 */
+//	    LPC_UART0->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
+//	}
+//	else if ((LPC_UART1_TypeDef*)LPC_UART == LPC_UART1)
+//	{
+//		LPC_PINCON->PINSEL4 &= ~0x0000000F;
+//		LPC_PINCON->PINSEL4 |= 0x0000000A;	/* Enable RxD1 P2.1, TxD1 P2.0 */
+//
+//		/* By default, the PCLKSELx value is zero, thus, the PCLK for
+//		all the peripherals is 1/4 of the SystemFrequency. */
+//		/* Bit 8,9 are for UART1 */
+//		pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
+//		switch ( pclkdiv )
+//		{
+//		  case 0x00:
+//		  default:
+//			pclk = SystemCoreClock/4;
+//			break;
+//		  case 0x01:
+//			pclk = SystemCoreClock;
+//			break;
+//		  case 0x02:
+//			pclk = SystemCoreClock/2;
+//			break;
+//		  case 0x03:
+//			pclk = SystemCoreClock/8;
+//			break;
+//		}
+//
+//	    LPC_UART1->LCR = 0x83;		/* 8 bits, no Parity, 1 Stop bit */
+//		Fdiv = ( pclk / 16 ) / UART_BAUDRATE ;	/*baud rate */
+//	    LPC_UART1->DLM = Fdiv / 256;
+//	    LPC_UART1->DLL = Fdiv % 256;
+//		LPC_UART1->LCR = 0x03;		/* DLAB = 0 */
+//	    LPC_UART1->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
+//	}
+//
+//	/* Ensure a clean start, no data in either TX or RX FIFO. */
+//	while (( LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
+//	while ( LPC_UART->LSR & LSR_RDR )
+//	{
+//		Fdiv = LPC_UART->RBR;	/* Dump data from RX FIFO */
+//	}
+//	LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
+{
+//	RT_ASSERT(dev != RT_NULL);
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		/* Enable the UART Interrupt */
+//		NVIC_EnableIRQ(UART_IRQn);
+//	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_close(rt_device_t dev)
+{
+//	RT_ASSERT(dev != RT_NULL);
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		/* Disable the UART Interrupt */
+//		NVIC_DisableIRQ(UART_IRQn);
+//	}
+
+	return RT_EOK;
+}
+
+static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+//	rt_uint8_t* ptr;
+//	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+//	RT_ASSERT(uart != RT_NULL);
+//
+//	/* point to buffer */
+//	ptr = (rt_uint8_t*) buffer;
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		while (size)
+//		{
+//			/* interrupt receive */
+//			rt_base_t level;
+//
+//			/* disable interrupt */
+//			level = rt_hw_interrupt_disable();
+//			if (uart->read_index != uart->save_index)
+//			{
+//				*ptr = uart->rx_buffer[uart->read_index];
+//
+//				uart->read_index ++;
+//				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+//					uart->read_index = 0;
+//			}
+//			else
+//			{
+//				/* no data in rx buffer */
+//
+//				/* enable interrupt */
+//				rt_hw_interrupt_enable(level);
+//				break;
+//			}
+//
+//			/* enable interrupt */
+//			rt_hw_interrupt_enable(level);
+//
+//			ptr ++;
+//			size --;
+//		}
+//
+//		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+//	}
+
+	return 0;
+}
+
+static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+//    rt_uint32_t i = size;
+//	char *ptr;
+//	ptr = (char*)buffer;
+//
+//    while(i)
+//    {
+//        UART_SendByte((LPC_UART_TypeDef*)LPC_UART1,*ptr);
+//        i--;
+//        ptr++;
+//    }
+//    return size;
+
+	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+	char *ptr;
+	ptr = (char*)buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+                UART_SendByte( uart->UART,'\r');
+			}
+
+			UART_SendByte( uart->UART,*ptr);
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+		while ( size != 0 )
+		{
+		    UART_SendByte( uart->UART,*ptr);
+			ptr++;
+			size--;
+		}
+	}
+
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_hw_uart_init(void)
+{
+#ifdef RT_USING_UART1
+	struct rt_uart_lpc* uart;
+	UART_CFG_Type UART_ConfigStruct;
+
+	/*
+	 * Initialize UART1 pin connect
+	 * P3.16: TXD
+	 * P3.17: RXD
+	 */
+	PINSEL_ConfigPin(3, 16, 3);
+	PINSEL_ConfigPin(3, 17, 3);
+
+	UART_ConfigStruct.Baud_rate = 115200;
+	UART_ConfigStruct.Databits = UART_DATABIT_8;
+	UART_ConfigStruct.Parity = UART_PARITY_NONE;
+	UART_ConfigStruct.Stopbits = UART_STOPBIT_1;
+
+	UART_Init((LPC_UART_TypeDef *)LPC_UART1,&UART_ConfigStruct);
+
+	// Enable UART Transmit
+	UART_TxCmd((LPC_UART_TypeDef *)LPC_UART1, ENABLE);
+
+	/* get uart device */
+	uart = &uart1_device;
+	uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
+
+	/* device initialization */
+	uart->parent.type = RT_Device_Class_Char;
+	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+	uart->read_index = uart->save_index = 0;
+
+	/* device interface */
+	uart->parent.init 	    = rt_uart_init;
+	uart->parent.open 	    = rt_uart_open;
+	uart->parent.close      = rt_uart_close;
+	uart->parent.read 	    = rt_uart_read;
+	uart->parent.write      = rt_uart_write;
+	uart->parent.control    = RT_NULL;
+	uart->parent.user_data  = RT_NULL;
+
+	rt_device_register(&uart->parent,
+		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+#endif
+}
+
+/*@}*/

bsp/lpc178x/drivers/uart.h

@@ -0,0 +1,6 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+void rt_hw_uart_init(void);
+
+#endif

bsp/lpc178x/project.uvproj

@@ -0,0 +1,694 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread LPC17xx</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1788</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC177x_8x\startup_LPC177x_8x.s" ("NXP LPC177x_8x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</FlashDriverDll>
+          <DeviceId>5325</DeviceId>
+          <RegisterFile>LPC177x_8x.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC177x_8x\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC177x_8x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\obj\</OutputDirectory>
+          <OutputName>rtthread-lpc</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\obj\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DARMP1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pLPC1788</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TARMP1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pLPC1788</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x;.;..\..\libcpu\arm\lpc17xx;..\..\include;..\..\libcpu\arm\common;CMSIS\CM3\CoreSupport;..\..\components\finsh</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep __fsym_* --keep __vsym_* </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Startup</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>2</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath>.\drivers</IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>LPC17XX</GroupName>
+          <Files>
+            <File>
+              <FileName>cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>fault.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\fault.c</FilePath>
+            </File>
+            <File>
+              <FileName>interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>stack.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\stack.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>fault_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\lpc17xx\fault_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>CMSIS\CM3\CoreSupport\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_LPC177x_8x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x\system_LPC177x_8x.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_LPC177x_8x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x\startup\arm\startup_LPC177x_8x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>driver</GroupName>
+          <Files>
+            <File>
+              <FileName>lpc177x_8x_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\lpc177x_8x_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>lpc177x_8x_clkpwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\lpc177x_8x_clkpwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>lpc177x_8x_pinsel.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\lpc177x_8x_pinsel.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\board.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

bsp/lpc178x/rtconfig.h

@@ -0,0 +1,150 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+/* #define RT_THREAD_DEBUG */
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem support */
+//#define RT_USING_DFS
+#define RT_USING_DFS_ELMFAT
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+/* the max number of cached sector 		*/
+#define DFS_CACHE_MAX_NUM   		4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+//#define RT_USING_LWIP
+#define RT_LWIP_USING_RT_MEM
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+/* SECTION: RT-Thread/GUI */
+/* #define RT_USING_RTGUI */
+
+/* name length of RTGUI object */
+#define RTGUI_NAME_MAX		12
+/* support 16 weight font */
+#define RTGUI_USING_FONT16
+/* support Chinese font */
+#define RTGUI_USING_FONTHZ
+/* use DFS as file interface */
+#define RTGUI_USING_DFS_FILERW
+/* use font file as Chinese font */
+#define RTGUI_USING_HZ_FILE
+/* use small size in RTGUI */
+#define RTGUI_USING_SMALL_SIZE
+/* use mouse cursor */
+/* #define RTGUI_USING_MOUSE_CURSOR */
+/* default font size in RTGUI */
+#define RTGUI_DEFAULT_FONT_SIZE	16
+
+#endif

bsp/lpc178x/rtconfig.py

@@ -0,0 +1,87 @@
+# toolchains options
+ARCH='arm'
+CPU='lpc17xx'
+CROSS_TOOL='keil'
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= 'E:/Program Files/IAR Systems/Embedded Workbench 6.0/arm/bin'
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb'
+    CFLAGS = DEVICE + ' -DRT_USING_MINILIBC'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc17xx.map,-cref,-u,Reset_Handler -T lpc17xx_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMP1'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc17xx.map --scatter lpc17xx_rom.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' --cpu DARMP1 --thumb'
+
+    CFLAGS = ''
+    AFLAGS = ''
+    LFLAGS = ' --config lpc17xx_flash.icf'
+
+    EXEC_PATH += '/arm/bin/'
+    RT_USING_MINILIBC = False
+    POST_ACTION = ''

bsp/lpc178x/startup.c

@@ -0,0 +1,141 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2010-03-04     Magicoe      for LPC17xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "LPC177x_8x.h"
+#include "board.h"
+
+#ifdef RT_USING_DFS
+#include "sd.h"
+#endif
+
+/**
+ * @addtogroup LPC17
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+#ifdef  DEBUG
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+	#ifdef __CC_ARM
+		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
+	#elif __ICCARM__
+	    rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
+	#else
+		/* init memory system */
+		rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
+	#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+#ifdef RT_USING_DEVICE
+#ifdef RT_USING_DFS
+	rt_hw_sdcard_init();
+#endif
+	/* init all device */
+	rt_device_init_all();
+#endif
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device( FINSH_DEVICE_NAME );
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/

bsp/lpc178x/template.uvproj

@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread LPC17xx</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1788</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC177x_8x\startup_LPC177x_8x.s" ("NXP LPC177x_8x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</FlashDriverDll>
+          <DeviceId>5325</DeviceId>
+          <RegisterFile>LPC177x_8x.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC177x_8x\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC177x_8x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\obj\</OutputDirectory>
+          <OutputName>rtthread-lpc</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\obj\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DARMP1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pLPC1788</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TARMP1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pLPC1788</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>