Merge pull request #2139 from Guozhanxin/imxrt

更新 imxrt 工程

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c

@@ -33,7 +33,6 @@
  */
 
 #include "fsl_flexspi.h"
-
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.flexspi"
@@ -113,21 +112,21 @@ static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
 #endif
 
 /*! @brief Pointers to flexspi bases for each instance. */
-static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
+static FLEXSPI_Type *const s_flexspiBases[] SECTION("itcm") = FLEXSPI_BASE_PTRS;
 
 /*! @brief Pointers to flexspi IRQ number for each instance. */
-static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
+static const IRQn_Type s_flexspiIrqs[] SECTION("itcm") = FLEXSPI_IRQS;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Clock name array */
-static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
+static const clock_ip_name_t s_flexspiClock[] SECTION("itcm") = FLEXSPI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
-uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
+SECTION("itcm") uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
 {
     uint32_t instance;
 
@@ -145,7 +144,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
     return instance;
 }
 
-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+SECTION("itcm") static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
 {
     bool isUnifiedConfig = true;
     uint32_t flexspiDllValue;
@@ -199,7 +198,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
     return flexspiDllValue;
 }
 
-status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
+SECTION("itcm") status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
 {
     status_t result = kStatus_Success;
 
@@ -236,7 +235,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
     return result;
 }
 
-void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 {
     uint32_t configValue = 0;
     uint8_t i = 0;
@@ -309,7 +308,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
     base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
 }
 
-void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
 {
     config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
     config->enableSckFreeRunning = false;
@@ -339,13 +338,13 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
     config->ahbConfig.enableAHBCachable = false;
 }
 
-void FLEXSPI_Deinit(FLEXSPI_Type *base)
+SECTION("itcm") void FLEXSPI_Deinit(FLEXSPI_Type *base) 
 {
     /* Reset peripheral. */
     FLEXSPI_SoftwareReset(base);
 }
 
-void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+SECTION("itcm") void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
 {
     uint32_t configValue = 0;
     uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */
@@ -416,7 +415,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
 }
 
-void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
+SECTION("itcm") void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
 {
     assert(index < 64U);
 
@@ -443,7 +442,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
     base->LUTCR = 0x01;
 }
 
-status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
     uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
     uint32_t status;
@@ -491,7 +490,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
     return result;
 }
 
-status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
     uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
     uint32_t status;
@@ -561,7 +560,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
     return result;
 }
 
-status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
     status_t result = kStatus_Success;
@@ -618,7 +617,7 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     return result;
 }
 
-void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+SECTION("itcm") void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
                                   flexspi_handle_t *handle,
                                   flexspi_transfer_callback_t callback,
                                   void *userData)
@@ -643,7 +642,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
     EnableIRQ(s_flexspiIrqs[instance]);
 }
 
-status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
     status_t result = kStatus_Success;
@@ -709,7 +708,7 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
     return result;
 }
 
-status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
+SECTION("itcm") status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
 {
     assert(handle);
 
@@ -727,7 +726,7 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle,
     return result;
 }
 
-void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
     assert(handle);
 
@@ -735,7 +734,7 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
     handle->state = kFLEXSPI_Idle;
 }
 
-void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
     uint8_t status;
     status_t result;
@@ -832,7 +831,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 
 #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
 #if defined(FLEXSPI)
-void FLEXSPI_DriverIRQHandler(void)
+SECTION("itcm") void FLEXSPI_DriverIRQHandler(void)
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -844,7 +843,7 @@ void FLEXSPI_DriverIRQHandler(void)
 #endif
 
 #if defined(FLEXSPI0)
-void FLEXSPI0_DriverIRQHandler(void)
+void FLEXSPI0_DriverIRQHandler(void) SECTION("itcm")
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -855,7 +854,7 @@ void FLEXSPI0_DriverIRQHandler(void)
 }
 #endif
 #if defined(FLEXSPI1)
-void FLEXSPI1_DriverIRQHandler(void)
+void FLEXSPI1_DriverIRQHandler(void) SECTION("itcm")
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h

@@ -34,7 +34,7 @@
 
 #ifndef __FSL_FLEXSPI_H_
 #define __FSL_FLEXSPI_H_
-
+#include <rtthread.h>
 #include <stddef.h>
 #include "fsl_device_registers.h"
 #include "fsl_common.h"
@@ -401,7 +401,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
  *
  * @param base FLEXSPI peripheral base address.
  */
-static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+static SECTION("itcm") inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
 {
     base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
     while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
@@ -415,7 +415,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable FLEXSPI, false means disable.
  */
-static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -439,7 +439,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param mask FLEXSPI interrupt source.
  */
-static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTEN |= mask;
 }
@@ -450,7 +450,7 @@ static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  * @param base FLEXSPI peripheral base address.
  * @param mask FLEXSPI interrupt source.
  */
-static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTEN &= ~mask;
 }
@@ -466,7 +466,7 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  * @param base FLEXSPI peripheral base address.
  * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
  */
-static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -484,7 +484,7 @@ static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
  */
-static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -502,7 +502,7 @@ static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @retval The tx fifo address.
  */
-static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
 {
     return (uint32_t)&base->TFDR[0];
 }
@@ -513,7 +513,7 @@ static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @retval The rx fifo address.
  */
-static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
 {
     return (uint32_t)&base->RFDR[0];
 }
@@ -529,7 +529,7 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
  * @param txFifo Pass true to reset TX FIFO.
  * @param rxFifo Pass true to reset RX FIFO.
  */
-static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
+static SECTION("itcm") inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
 {
     if (txFifo)
     {
@@ -550,7 +550,7 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi
  * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
  *      Pass NULL if this value is not required.
  */
-static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
+static SECTION("itcm") inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
 {
     if (txCount)
     {
@@ -574,7 +574,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si
  * @param base FLEXSPI peripheral base address.
  * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
  */
-static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
 {
     return base->INTR;
 }
@@ -585,7 +585,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param interrupt status flag.
  */
-static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTR |= mask;
 }
@@ -616,7 +616,7 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
  * @param base FLEXSPI peripheral base address.
  * @retval trigger source of current command sequence.
  */
-static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
+static SECTION("itcm") inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
 {
     return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
 }
@@ -627,7 +627,7 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL
  * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  * @retval error code when IP command error detected.
  */
-static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
     *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
     return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
@@ -639,7 +639,7 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type
  * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  * @retval error code when AHB command error detected.
  */
-static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
     *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
     return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
@@ -652,7 +652,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
  * @retval true Bus is idle.
  * @retval false Bus is busy.
  */
-static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+static SECTION("itcm") inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
 {
     return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
 }
@@ -668,7 +668,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable parallel mode, false means disable parallel mode.
  */
-static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -685,7 +685,7 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable parallel mode, false means disable parallel mode.
  */
-static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -715,7 +715,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
  * @param data The data bytes to send
  * @param fifoIndex Destination fifo index.
  */
-static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
+static SECTION("itcm") inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
 {
     base->TFDR[fifoIndex] = data;
 }
@@ -727,7 +727,7 @@ static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t
  * @param fifoIndex Source fifo index.
  * @return The data in the FIFO.
  */
-static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
+static SECTION("itcm") inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
 {
     return base->RFDR[fifoIndex];
 }

bsp/imxrt/Libraries/imxrt1050/drivers/SConscript

@@ -11,7 +11,13 @@ drv_cache.c
 CPPPATH = [cwd]
 CPPDEFINES = []
 
-# add sdram driver code
+if GetDepend('BOARD_USING_QSPIFLASH'):
+    src += ['drv_flexspi_nor.c'] 
+
+if GetDepend('BOARD_USING_HYPERFLASH'):
+    src += ['drv_flexspi_hyper.c'] 
+    
+# add sdram driver code 
 if GetDepend('RT_USING_SDRAM'):
     src = src + ['drv_sdram.c'] 
 
@@ -21,7 +27,7 @@ if GetDepend('RT_USING_PIN'):
 
 # add rtc driver code
 if GetDepend('RT_USING_RTC_HP'):
-    src = src + ['drv_rtc.c'] 
+    src += ['drv_rtc.c'] 
 
 # add spibus driver code
 if GetDepend('RT_USING_SPI'):

bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c

@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[Hyper]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
+#define CUSTOM_LUT_LENGTH 48
+
+static flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */
+    .isSck2Enabled = false,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 0,
+    .CSSetupTime = 3,
+    .dataValidTime = 1,
+    .columnspace = 3,
+    .enableWordAddress = true,
+    .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
+    .AWRSeqNumber = 1,
+    .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 20,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+        /* Read Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+        /* Write Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
+        /* Read Status */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+        /* Write Enable */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+
+        /* Erase Sector  */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* program page */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
+};
+
+
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) 
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 2;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (readValue & 0x8000)
+        {
+            isBusy = false;
+        }
+        else
+        {
+            isBusy = true;
+        }
+
+        if (readValue & 0x3200)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+    } while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) 
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write enable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 4;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+ SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base)
+{
+    /*
+     * Read ID-CFI Parameters
+     */
+    // CFI Entry
+    status_t status;
+    uint32_t buffer[2];
+    uint32_t data = 0x9800;
+    status = flexspi_nor_hyperbus_write(base, 0x555, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    // ID-CFI Read
+    // Read Query Unique ASCII String
+    status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer));
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    buffer[1] &= 0xFFFF;
+    // Check that the data read out is  unicode "QRY" in big-endian order
+    if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900))
+    {
+        status = kStatus_Fail;
+        return status;
+    }
+    // ASO Exit
+    data = 0xF000;
+    status = flexspi_nor_hyperbus_write(base, 0x0, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    // Set flexspi root clock to 166MHZ.
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26);   /* Set PLL3 PFD0 clock 332MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);   /* flexspi clock 83M, DDR mode, internal clock 42M. */
+
+    
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    /*Allow AHB read start address do not follow the alignment requirement. */
+    config.ahbConfig.enableReadAddressOpt = true;
+    /* enable diff clock and DQS */
+    config.enableSckBDiffOpt = true;
+    config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+    config.enableCombination = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+    
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+    
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    status = flexspi_nor_hyperflash_cfi(FLEXSPI);
+    /* Get vendor ID. */
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return 0;
+}

bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c

@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[FLEXSPI]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 1
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 3
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
+#define NOR_CMD_LUT_SEQ_IDX_READID 8
+#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
+#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
+#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
+#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 13
+#define CUSTOM_LUT_LENGTH 60
+#define FLASH_BUSY_STATUS_POL 1
+#define FLASH_BUSY_STATUS_OFFSET 0
+
+static flexspi_device_config_t deviceconfig =
+{
+    .flexspiRootClk = 100000000,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 3,
+    .CSSetupTime = 3,
+    .dataValidTime = 0,
+    .columnspace = 0,
+    .enableWordAddress = 0,
+    .AWRSeqIndex = 0,
+    .AWRSeqNumber = 0,
+    .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 0,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] =
+{
+    /* Normal read mode -SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Fast read mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Fast read quad mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
+
+    /* Read extend parameters */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Write Enable */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Erase Sector  */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+
+    /* Page Program - single mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Page Program - quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read ID */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xAB, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Enable Quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enter QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Exit QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xFF, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read status register */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Erase Chip */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+};
+
+
+
+SECTION("itcm") static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 1;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (FLASH_BUSY_STATUS_POL)
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = true;
+            }
+            else
+            {
+                isBusy = false;
+            }
+        }
+        else
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = false;
+            }
+            else
+            {
+                isBusy = true;
+            }
+        }
+
+    }
+    while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    uint32_t writeValue = 0x40;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, 0);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Enable quad mode. */
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
+    flashXfer.data = &writeValue;
+    flashXfer.dataSize = 1;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write enable */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
+{
+    uint32_t temp;
+    flexspi_transfer_t flashXfer;
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
+    flashXfer.data = &temp;
+    flashXfer.dataSize = 1;
+
+    status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    *vendorId = temp;
+
+    return status;
+}
+
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    uint8_t vendorID = 0;
+
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);   /* Set PLL3 PFD0 clock 360MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);   /* flexspi clock 120M. */
+
+    dbg_log(DBG_INFO, "NorFlash Init\r\n");
+
+    FLEXSPI_GetDefaultConfig(&config);
+
+    config.ahbConfig.enableAHBPrefetch = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    dbg_log(DBG_INFO, "Vendor ID: 0x%x\r\n", vendorID);
+
+    status = flexspi_nor_enable_quad_mode(FLEXSPI);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "Entry Quad mode failed\r\n");
+        return status;
+    }
+    dbg_log(DBG_INFO, "NorFlash Init Done\r\n");
+    rt_hw_interrupt_enable(level);
+    return 0;
+}

bsp/imxrt/imxrt1050-ArchMix/.config

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=100
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -60,10 +62,12 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_FPU=y
 CONFIG_ARCH_ARM_CORTEX_M7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -102,8 +106,8 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_RT_USING_DFS_ELMFAT=y
@@ -143,13 +147,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y
 CONFIG_RT_USING_I2C=y
 CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
-# CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
 CONFIG_RT_SDIO_STACK_SIZE=512
 CONFIG_RT_SDIO_THREAD_PRIORITY=15
@@ -158,6 +163,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
 CONFIG_RT_MMCSD_MAX_PARTITION=16
 # CONFIG_RT_SDIO_DEBUG is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 # CONFIG_RT_USING_SFUD is not set
 # CONFIG_RT_USING_W25QXX is not set
@@ -220,12 +226,15 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -236,6 +245,7 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
@@ -270,6 +280,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
 
 #
 # security packages
@@ -300,6 +311,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
 
 #
 # system packages
@@ -316,6 +329,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -327,6 +341,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 
 #
 # miscellaneous packages
@@ -340,10 +358,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
+# CONFIG_PKG_USING_TINYFRAME is not set
 
 #
 # samples: kernel and components samples
@@ -352,14 +367,9 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
 CONFIG_SOC_IMXRT1052=y
 CONFIG_BOARD_RT1050_ArchMix=y
-# CONFIG_BOARD_USING_HYPERFLASH is not set
 CONFIG_BOARD_USING_QSPIFLASH=y
 
 #

bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript

@@ -5,11 +5,23 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 board.c
+drv_flexspi.c
 """)
 
 CPPPATH = [cwd]
 CPPDEFINES = []
 
+if GetDepend('PKG_USING_EASYFLASH'):
+    src += ['ports/ef_fal_port.c'] 
+
+if GetDepend('PKG_USING_FAL'):
+    src += ['ports/fal_flexspi_nor_flash_port.c'] 
+
+if GetDepend('PKG_USING_FAL') and GetDepend('PKG_USING_EASYFLASH'):
+    src += ['ports/fal_flash_init.c', 'ports/ef_update.c'] 
+
+CPPPATH += [cwd + '/ports']
+
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
 
 Return('group')

bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <rtthread.h>
+#include <drv_flexspi.h>
+
+INIT_PREV_EXPORT(rt_hw_flexspi_init);

bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#ifndef __DRV_FLEXSPI_H__
+#define __DRV_FLEXSPI_H__
+#include "fsl_flexspi.h"
+#include "fsl_common.h"
+#ifdef BOARD_USING_QSPIFLASH
+#define FLASH_SIZE 0x2000 /* 64Mb/KByte */
+#define FLASH_PAGE_SIZE 256
+#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */
+#elif defined(BOARD_USING_HYPERFLASH)
+#define FLASH_SIZE 0x10000 /* 512Mb/KByte */
+#define FLASH_PAGE_SIZE 512
+#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */
+#endif
+#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
+extern int      rt_hw_flexspi_init(void);
+extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
+extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src);
+#endif

bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-19     armink       the first version
+ */
+
+#include <easyflash.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <fal.h>
+
+/* EasyFlash partition name on FAL partition table */
+#define FAL_EF_PART_NAME               "env"
+
+/* default ENV set for user */
+static const ef_env default_env_set[] = {
+        {"stay_in_bootloader","0"},
+        {"check_upgrade","0"},
+        {"bootdelay","1"},
+};
+
+static char log_buf[RT_CONSOLEBUF_SIZE];
+static struct rt_semaphore env_cache_lock;
+static const struct fal_partition *part = NULL;
+
+/**
+ * Flash port for hardware initialize.
+ *
+ * @param default_env default ENV set for user
+ * @param default_env_size default ENV size
+ *
+ * @return result
+ */
+EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) {
+    EfErrCode result = EF_NO_ERR;
+
+    *default_env = default_env_set;
+    *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]);
+
+    rt_sem_init(&env_cache_lock, "env lock", 1, RT_IPC_FLAG_PRIO);
+
+    part = fal_partition_find(FAL_EF_PART_NAME);
+    EF_ASSERT(part);
+
+    return result;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_read(uint32_t addr, uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    EF_ASSERT(size % 4 == 0);
+
+    fal_partition_read(part, addr, (uint8_t *)buf, size);
+
+    return result;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_erase(uint32_t addr, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    /* make sure the start address is a multiple of FLASH_ERASE_MIN_SIZE */
+    EF_ASSERT(addr % EF_ERASE_MIN_SIZE == 0);
+
+    if (fal_partition_erase(part, addr, size) < 0)
+    {
+        result = EF_ERASE_ERR;
+    }
+
+    return result;
+}
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    EF_ASSERT(size % 4 == 0);
+
+    if (fal_partition_write(part, addr, (uint8_t *)buf, size) < 0)
+    {
+        result = EF_WRITE_ERR;
+    }
+
+    return result;
+}
+
+/**
+ * lock the ENV ram cache
+ */
+void ef_port_env_lock(void) {
+    rt_sem_take(&env_cache_lock, RT_WAITING_FOREVER);
+}
+
+/**
+ * unlock the ENV ram cache
+ */
+void ef_port_env_unlock(void) {
+    rt_sem_release(&env_cache_lock);
+}
+
+/**
+ * This function is print flash debug info.
+ *
+ * @param file the file which has call this function
+ * @param line the line number which has call this function
+ * @param format output format
+ * @param ... args
+ *
+ */
+void ef_log_debug(const char *file, const long line, const char *format, ...) {
+
+#ifdef PRINT_DEBUG
+
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] (%s:%ld) ", file, line);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+
+#endif
+
+}
+
+/**
+ * This function is print flash routine info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_log_info(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] ");
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+}
+/**
+ * This function is print flash non-package info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_print(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    rt_kprintf("%s", log_buf);
+    va_end(args);
+}

bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <easyflash.h>
+#include <rtthread.h>
+#include <fsl_wdog.h>
+
+void reset(void)
+{
+    SCB->AIRCR = 0x05fa0000 | 0x04UL;
+    while (1)
+    {
+    }
+}
+MSH_CMD_EXPORT(reset, reset system.);
+
+#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) && defined(EF_USING_ENV)
+#include <finsh.h>
+#if defined(EF_USING_ENV)
+
+static void update(uint8_t argc, char **argv)
+{
+    ef_set_env("check_upgrade", "1");
+    ef_save_env();
+    reset();
+}
+MSH_CMD_EXPORT(update, reset and check update.);
+
+#endif /* defined(EF_USING_ENV) */
+#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */

bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h

@@ -0,0 +1,52 @@
+/*
+ * File      : fal_cfg.h
+ * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-17     armink       the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+#define RT_FAL_BL_PART_LEN              (256*1024)
+#define RT_FAL_ENV_PART_LEN             (1*1024)
+#define RT_FAL_PT_PART_LEN              (1*1024)
+#define RT_FAL_APP_PART_LEN             (1*1024*1024)
+#define RT_FAL_DL_PART_LEN              (1*1024*1024)
+
+#define RT_FAL_FLASH_BASE               0
+#define RT_FAL_BL_PART_OFFSET           RT_FAL_FLASH_BASE
+#define RT_FAL_ENV_PART_OFFSET          (RT_FAL_BL_PART_OFFSET  + RT_FAL_BL_PART_LEN)
+#define RT_FAL_PT_PART_OFFSET           (RT_FAL_ENV_PART_OFFSET + RT_FAL_ENV_PART_LEN)
+#define RT_FAL_APP_PART_OFFSET          (RT_FAL_PT_PART_OFFSET  + RT_FAL_PT_PART_LEN)
+#define RT_FAL_DL_PART_OFFSET           (RT_FAL_APP_PART_OFFSET + RT_FAL_APP_PART_LEN)
+#define RT_FAL_FS_PART_OFFSET           (RT_FAL_DL_PART_OFFSET  + RT_FAL_DL_PART_LEN)
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                          \
+{                                                                               \
+    {FAL_PART_MAGIC_WROD,       "bl",   "norflash0",  RT_FAL_BL_PART_OFFSET,   RT_FAL_BL_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,      "env",   "norflash0", RT_FAL_ENV_PART_OFFSET,  RT_FAL_ENV_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,       "pt",   "norflash0",  RT_FAL_PT_PART_OFFSET,   RT_FAL_PT_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,      "app",   "norflash0", RT_FAL_APP_PART_OFFSET,  RT_FAL_APP_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD, "download",   "norflash0",  RT_FAL_DL_PART_OFFSET,   RT_FAL_DL_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,       "fs",   "norflash0",  RT_FAL_FS_PART_OFFSET,                    0, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */

bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <rtthread.h>
+#include <fal.h>
+#include <easyflash.h>
+
+#define FAL_FS_PART_NAME               "fs"
+#define FAL_DOWNLOAD_PART_NAME         "download"
+
+int rt_fal_flash_init(void)
+{
+    fal_init();
+    easyflash_init();
+
+    fal_blk_device_create(FAL_FS_PART_NAME);
+    fal_char_device_create(FAL_DOWNLOAD_PART_NAME);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_fal_flash_init);

bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c

@@ -0,0 +1,75 @@
+/*
+ * File      : rt_ota_flash_sfud_port.c
+ * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-26     armink       the first version
+ */
+
+#include <rtthread.h>
+#include <fal.h>
+#include <drv_flexspi.h>
+#include <rthw.h>
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    memcpy(buf,(const void *)(FLEXSPI_AMBA_BASE+offset),size);
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    static char write_buffer[FLASH_PAGE_SIZE];
+    size_t writen_size = 0;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    while(size)
+    {
+        if(size >= FLASH_PAGE_SIZE)
+        {
+            flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)buf);
+            size -= FLASH_PAGE_SIZE;
+            writen_size += FLASH_PAGE_SIZE;
+        }
+        else
+        {
+            memcpy(write_buffer,(const void *)(FLEXSPI_AMBA_BASE+offset),FLASH_PAGE_SIZE);
+            memcpy(write_buffer,buf,size);
+            flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)write_buffer);
+            writen_size += size;
+            size = 0;
+        }
+        offset += FLASH_PAGE_SIZE;
+        buf += FLASH_PAGE_SIZE;
+    }
+    rt_hw_interrupt_enable(level);
+    return writen_size;
+}
+
+static int erase(long offset, size_t size)
+{
+    size_t erase_size = size;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    size = offset;
+    offset = (offset/FLEXSPI_NOR_SECTOR_SIZE)*FLEXSPI_NOR_SECTOR_SIZE;
+    size = erase_size + size - offset;
+    while(size)
+    {
+        flexspi_nor_flash_erase_sector(FLEXSPI,offset);
+        if(size >= FLEXSPI_NOR_SECTOR_SIZE)
+        {
+            size -= FLEXSPI_NOR_SECTOR_SIZE;
+        }
+        else
+        {
+            size = 0;
+        }
+        offset += FLEXSPI_NOR_SECTOR_SIZE;
+    }
+    rt_hw_interrupt_enable(level);
+    return erase_size;
+}
+struct fal_flash_dev nor_flash0 = { "norflash0", 0, FLASH_SIZE*1024, FLEXSPI_NOR_SECTOR_SIZE, {NULL, read, write, erase} };
+

bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf

@@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size
         * (NonCacheable.init)
         * (NonCacheable)
     }
+  ITCM 0x400 0xFBFF {
+		;drv_flexspi_hyper.o(+RO)
+		;fsl_flexspi.o(+RO)
+		* (*CLOCK_DisableClock)
+		* (*CLOCK_ControlGate)
+		* (*CLOCK_EnableClock)
+		* (*CLOCK_SetDiv)
+		* (itcm)
+	}
 }

bsp/imxrt/imxrt1050-ArchMix/project.ewp

@@ -1,2478 +1,2335 @@
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>21</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Automatic choice of formatter.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Automatic choice of formatter.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>6.30.6.53380</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>6.30.6.53380</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MIMXRT1052xxx6A	NXP MIMXRT1052xxx6A</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>28</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          <state />
-          <state>FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE</state>
-          <state>CPU_MIMXRT1052DVL6B</state>
-          <state>SKIP_SYSCLK_INIT</state>
-          <state>EVK_MCIMXRM</state>
-          <state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
-          <state>RT_USING_DLIBC</state>
-          <state>_DLIB_FILE_DESCRIPTOR</state>
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa082,Pa050,Pe167</state>
-        </option>
-        <option>
-          <name>CCDiagRemark</name>
-          <state />
-        </option>
-        <option>
-          <name>CCDiagWarning</name>
-          <state />
-        </option>
-        <option>
-          <name>CCDiagError</name>
-          <state />
-        </option>
-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCAllowList</name>
-          <version>1</version>
-          <state>0000000</state>
-        </option>
-        <option>
-          <name>CCDebugInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IEndianMode</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IExtraOptions</name>
-          <state />
-        </option>
-        <option>
-          <name>CCLangConformance</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSignedPlainChar</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRequirePrototypes</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMultibyteSupport</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCDiagWarnAreErr</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCompilerRuntimeInfo</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OutputFile</name>
-          <state>$FILE_BNAME$.o</state>
-        </option>
-        <option>
-          <name>CCLibConfigHeader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>PreInclude</name>
-          <state />
-        </option>
-        <option>
-          <name>CompilerMisraOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCIncludePath2</name>
-          <state />
-          <state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
-          <state>$PROJ_DIR$\Libraries</state>
-          <state>$PROJ_DIR$\..\..\include</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
-          <state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
-          <state>$PROJ_DIR$\..\..\components\drivers\include</state>
-          <state>$PROJ_DIR$\Libraries\drivers</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
-          <state>$PROJ_DIR$\drivers</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
-          <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\xip</state>
-          <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
-          <state>$PROJ_DIR$\..\..\components\dfs\include</state>
-          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
-          <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
-          <state>$PROJ_DIR$\Libraries\utilities</state>
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+      <name>ARM</name>
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+          <name>ExePath</name>
+          <state>Debug\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
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+          <name>ListPath</name>
+          <state>Debug\List</state>
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+          <version>19</version>
+          <state>37</state>
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+          <state>0</state>
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+          <name>Output variant</name>
+          <version>2</version>
+          <state>0</state>
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+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
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+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+          <version>0</version>
+          <state>1</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
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+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
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+          <name>OGChipSelectEditMenu</name>
+          <state>MIMXRT1052xxx6A	NXP MIMXRT1052xxx6A</state>
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+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+          <name>GEndianModeBE</name>
+          <state>1</state>
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+          <state>0</state>
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+          <name>GenStdoutInterface</name>
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+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <state>0</state>
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+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>19</version>
+          <state>37</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>19</version>
+          <state>37</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
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+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
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+          <state />
+          <state>RT_USING_DLIBC</state>
+          <state>_DLIB_FILE_DESCRIPTOR</state>
+          <state>_DLIB_THREAD_SUPPORT</state>
+          <state>CPU_MIMXRT1052DVL6B</state>
+          <state>SKIP_SYSCLK_INIT</state>
+          <state>EVK_MCIMXRM</state>
+          <state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
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+          <name>CCPreprocFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
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+          <name>CCListCFile</name>
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+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+          <name>CCListAssSource</name>
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+          <name>CCDiagSuppress</name>
+          <state>Pa082,Pa050,Pe167</state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state />
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+        <option>
+          <name>CCDiagWarning</name>
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+        </option>
+        <option>
+          <name>CCDiagError</name>
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+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+          <version>1</version>
+          <state>0000000</state>
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+          <name>CCDebugInfo</name>
+          <state>1</state>
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+          <name>IEndianMode</name>
+          <state>1</state>
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+          <name>IProcessor</name>
+          <state>1</state>
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+          <name>IExtraOptionsCheck</name>
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+        </option>
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+          <name>IExtraOptions</name>
+          <state />
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+          <name>CCLangConformance</name>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
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+          <name>CCMultibyteSupport</name>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
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+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
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+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state />
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+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state />
+          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs</state>
+          <state>$PROJ_DIR$\..\..\..\components\finsh</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\spi</state>
+          <state>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052</state>
+          <state>$PROJ_DIR$\drivers\ports</state>
+          <state>$PROJ_DIR$\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
+          <state>$PROJ_DIR$\.</state>
+          <state>$PROJ_DIR$\applications</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib</state>
+          <state>$PROJ_DIR$\..\Libraries\imxrt1050\CMSIS\Include</state>
+          <state>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\utilities</state>
+          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
+          <state>$PROJ_DIR$\..\..\..\include</state>
+          <state>$PROJ_DIR$\..\Libraries\imxrt1050\drivers</state>
+          <state>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers</state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
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+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevel</name>
+          <state>1</state>
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+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
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+          <name>CCOptLevelSlave</name>
+          <state>1</state>
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+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
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+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
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+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
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+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
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+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
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+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
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+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
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+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>ACaseSensitivity</name>
+          <state>1</state>
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+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\iar\startup_MIMXRT1052.s</name>
+    </file>
+  </group>
+</project>

bsp/imxrt/imxrt1050-ArchMix/project.eww

@@ -1,10 +1,10 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
-  <project>
-    <path>$WS_DIR$\project.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
-
-
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/imxrt/imxrt1050-ArchMix/rtconfig.h

@@ -13,6 +13,7 @@
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 #define RT_DEBUG
@@ -38,6 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_FPU
@@ -73,8 +75,8 @@
 
 #define RT_USING_DFS
 #define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
 #define DFS_FD_MAX 16
 #define RT_USING_DFS_ELMFAT
 
@@ -180,13 +182,8 @@
 /* miscellaneous packages */
 
 
-/* sample package */
-
 /* samples: kernel and components samples */
 
-
-/* example package: hello */
-
 #define SOC_IMXRT1052
 #define BOARD_RT1050_ArchMix
 #define BOARD_USING_QSPIFLASH

bsp/imxrt/imxrt1050-evk/.config

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=100
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -60,10 +62,12 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_FPU=y
 CONFIG_ARCH_ARM_CORTEX_M7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -144,13 +148,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y
 CONFIG_RT_USING_I2C=y
 CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
-# CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
 CONFIG_RT_SDIO_STACK_SIZE=512
 CONFIG_RT_SDIO_THREAD_PRIORITY=15
@@ -159,6 +164,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
 CONFIG_RT_MMCSD_MAX_PARTITION=16
 # CONFIG_RT_SDIO_DEBUG is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 # CONFIG_RT_USING_SFUD is not set
 # CONFIG_RT_USING_W25QXX is not set
@@ -205,6 +211,7 @@ CONFIG_RT_USING_POSIX=y
 CONFIG_RT_USING_LWIP=y
 # CONFIG_RT_USING_LWIP141 is not set
 CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP210 is not set
 # CONFIG_RT_USING_LWIP_IPV6 is not set
 # CONFIG_RT_LWIP_IGMP is not set
 CONFIG_RT_LWIP_ICMP=y
@@ -272,12 +279,15 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -288,6 +298,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
@@ -313,6 +324,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
 
 #
 # IoT Cloud
@@ -321,6 +333,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
 
 #
 # security packages
@@ -341,6 +354,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_BEEPPLAYER is not set
 
 #
 # tools packages
@@ -349,6 +363,9 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
 
 #
 # system packages
@@ -364,9 +381,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
-# CONFIG_PKG_USING_CMSIS_LATEST_VERSION is not set
-# CONFIG_PKG_USING_CMSIS_V500 is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -377,6 +393,11 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_AP3216C is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 
 #
 # miscellaneous packages
@@ -390,10 +411,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
+# CONFIG_PKG_USING_TINYFRAME is not set
 
 #
 # samples: kernel and components samples
@@ -402,10 +420,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
 CONFIG_SOC_IMXRT1052=y
 CONFIG_BOARD_USING_HYPERFLASH=y

bsp/imxrt/imxrt1050-evk/drivers/SConscript

@@ -5,6 +5,7 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 board.c
+drv_flexspi.c
 """)
 
 CPPPATH = [cwd]

bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <rtthread.h>
+#include <drv_flexspi.h>
+
+INIT_PREV_EXPORT(rt_hw_flexspi_init);

bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#ifndef __DRV_FLEXSPI_H__
+#define __DRV_FLEXSPI_H__
+#include "fsl_flexspi.h"
+#include "fsl_common.h"
+#ifdef BOARD_USING_QSPIFLASH
+#define FLASH_SIZE 0x8000 /* 256Mb/KByte */
+#define FLASH_PAGE_SIZE 256
+#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */
+#elif defined(BOARD_USING_HYPERFLASH)
+#define FLASH_SIZE 0x10000 /* 512Mb/KByte */
+#define FLASH_PAGE_SIZE 512
+#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */
+#endif
+#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
+extern int      rt_hw_flexspi_init(void);
+extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
+extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src);
+#endif

bsp/imxrt/imxrt1050-evk/flexspi_nor.scf

@@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size
         * (NonCacheable.init)
         * (NonCacheable)
     }
+  ITCM 0x400 0xFBFF {
+		;drv_flexspi_hyper.o(+RO)
+		;fsl_flexspi.o(+RO)
+		* (*CLOCK_DisableClock)
+		* (*CLOCK_ControlGate)
+		* (*CLOCK_EnableClock)
+		* (*CLOCK_SetDiv)
+		* (itcm)
+	}
 }

bsp/imxrt/imxrt1050-evk/project.ewp

@@ -1,2478 +1,2527 @@
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>21</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Automatic choice of formatter.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Automatic choice of formatter.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>6.30.6.53380</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>6.30.6.53380</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MIMXRT1052xxx6A	NXP MIMXRT1052xxx6A</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>28</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          <state />
-          <state>FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE</state>
-          <state>CPU_MIMXRT1052DVL6B</state>
-          <state>SKIP_SYSCLK_INIT</state>
-          <state>EVK_MCIMXRM</state>
-          <state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
-          <state>RT_USING_DLIBC</state>
-          <state>_DLIB_FILE_DESCRIPTOR</state>
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
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+        <option>
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+          <name>PageLength</name>
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+          <state>8</state>
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+          <name>AFpuProcessor</name>
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+          <state />
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+          <name>AMultibyteSupport</name>
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+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
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+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
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+          <name>AIgnoreStdInclude</name>
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+          <name>AUserIncludes</name>
+          <state />
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+        <option>
+          <name>AExtraOptionsV2</name>
+          <state />
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+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
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+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state />
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
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+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions />
+        <cmdline />
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+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
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+        <prebuild />
+        <postbuild />
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+      <archiveVersion>0</archiveVersion>
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+        <version>14</version>
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+          <state>1</state>
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+          <name>XLinkMisraHandler</name>
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+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>###Unitialized###</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
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+          <name>IlinkKeepSymbols</name>
+          <state />
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+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state />
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+          <name>IlinkRawBinarySymbol</name>
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+          <name>IlinkRawBinarySegment</name>
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+          <name>IlinkRawBinaryAlign</name>
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+          <name>IlinkConfigDefines</name>
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+          <name>IlinkMapFile</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
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+          <name>IlinkLogInitialization</name>
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+          <name>IlinkLogModule</name>
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+          <name>IlinkLogVeneer</name>
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+          <name>IlinkIcfOverride</name>
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+        <option>
+          <name>IlinkIcfFile</name>
+          <state>lnk0t.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state />
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+          <name>IlinkEnableRemarks</name>
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+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state />
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+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state />
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+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state />
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+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state />
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
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+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlgo</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state />
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
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+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data />
+    </settings>
+  </configuration>
+  <group>
+    <name>Applications</name>
+    <file>
+      <name>$PROJ_DIR$\applications\lcd_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applications\main.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Drivers</name>
+    <file>
+      <name>$PROJ_DIR$\drivers\board.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_flexspi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_cache.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_flexspi_hyper.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_sdram.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_rtc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_spi_bus.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_i2c.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_lcd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_sdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\drv_eth.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\drivers\fsl_phy.c</name>
+    </file>
+  </group>
+  <group>
+    <name>xip</name>
+    <file>
+      <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\xip\fsl_flexspi_nor_flash.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\cpu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\signal.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+    </file>
+  </group>
+  <group>
+    <name>CORTEX-M7</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Filesystem</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\poll.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\select.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c</name>
+    </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\cputime\cputime_cortexm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\rtc\rtc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\block_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmcsd_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\completion.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c</name>
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+      <name>$PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c</name>
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+    <file>
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+    </file>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c</name>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c</name>
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+    </file>
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+    </file>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c</name>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c</name>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c</name>
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+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c</name>
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+    <file>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c</name>
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+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\iar\startup_MIMXRT1052.s</name>
+    </file>
+  </group>
+</project>

bsp/imxrt/imxrt1050-evk/project.eww

@@ -1,10 +1,10 @@
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-
-<workspace>
-  <project>
-    <path>$WS_DIR$\project.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
-
-
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/imxrt/imxrt1050-evk/project.uvoptx

@@ -173,2358 +173,6 @@
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   </Target>
 
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-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
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-      <bShared>0</bShared>
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bsp/imxrt/imxrt1050-evk/rtconfig.h

@@ -13,6 +13,7 @@
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 #define RT_DEBUG
@@ -38,6 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_FPU
@@ -217,13 +219,8 @@
 /* miscellaneous packages */
 
 
-/* sample package */
-
 /* samples: kernel and components samples */
 
-
-/* example package: hello */
-
 #define SOC_IMXRT1052
 #define BOARD_USING_HYPERFLASH
 #define BOARD_RT1050_EVK