raspi4.h 4.7 KB

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  1. #ifndef __RASPI4_H__
  2. #define __RASPI4_H__
  3. //https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf
  4. #define __REG32(x) (*((volatile unsigned int *)(x)))
  5. #define __REG16(x) (*((volatile unsigned short *)(x)))
  6. /* GIC IRQ MAX */
  7. #define MAX_HANDLERS (256)
  8. /* base address */
  9. #define PER_BASE (0xFE000000)
  10. //gpio offset
  11. #define GPIO_BASE_OFFSET (0x00200000)
  12. //pl011 offset
  13. #define PL011_UART0_BASE_OFFSET (0x00201000)
  14. #define PL011_UART2_BASE_OFFSET (0x00201400)
  15. #define PL011_UART3_BASE_OFFSET (0x00201600)
  16. #define PL011_UART4_BASE_OFFSET (0x00201800)
  17. #define PL011_UART5_BASE_OFFSET (0x00201A00)
  18. //pactl cs offset
  19. #define PACTL_CS_OFFSET (0x00204E00)
  20. //aux offset
  21. #define AUX_BASE_OFFSET (0x00215000)
  22. /* GPIO */
  23. #define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
  24. #define GPIO_IRQ_NUM (3) //40 pin mode
  25. #define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27)
  26. #define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45)
  27. #define IRQ_GPIO2 (96 + 51) //bank2 (46 to 57)
  28. #define IRQ_GPIO3 (96 + 52) //bank3
  29. /* Timer (ARM side) */
  30. #define ARM_TIMER_IRQ (64)
  31. #define ARM_TIMER_BASE (PER_BASE + 0xB000)
  32. #define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
  33. #define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
  34. #define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
  35. #define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
  36. #define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
  37. #define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
  38. #define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
  39. #define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
  40. #define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
  41. /* UART PL011 */
  42. #define UART0_BASE (PER_BASE + PL011_UART0_BASE_OFFSET)
  43. #define UART2_BASE (PER_BASE + PL011_UART2_BASE_OFFSET)
  44. #define UART3_BASE (PER_BASE + PL011_UART3_BASE_OFFSET)
  45. #define UART4_BASE (PER_BASE + PL011_UART4_BASE_OFFSET)
  46. #define UART5_BASE (PER_BASE + PL011_UART5_BASE_OFFSET)
  47. #define IRQ_AUX_UART (96 + 29)
  48. #define UART_REFERENCE_CLOCK (48000000)
  49. /* AUX */
  50. #define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
  51. #define IRQ_PL011 (96 + 57)
  52. /* SPI */
  53. #define SPI_0_BASE_OFFSET (0x00204000)
  54. #define SPI_3_BASE_OFFSET (0x00204600)
  55. #define SPI_4_BASE_OFFSET (0x00204800)
  56. #define SPI_5_BASE_OFFSET (0x00204A00)
  57. #define SPI_6_BASE_OFFSET (0x00204C00)
  58. #define SPI_0_BASE (PER_BASE + SPI_0_BASE_OFFSET)
  59. #define SPI_3_BASE (PER_BASE + SPI_3_BASE_OFFSET)
  60. #define SPI_4_BASE (PER_BASE + SPI_4_BASE_OFFSET)
  61. #define SPI_5_BASE (PER_BASE + SPI_5_BASE_OFFSET)
  62. #define SPI_6_BASE (PER_BASE + SPI_6_BASE_OFFSET)
  63. /* Peripheral IRQ OR-ing */
  64. #define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET))
  65. typedef enum {
  66. IRQ_SPI0 = 0x00000000,
  67. IRQ_SPI1 = 0x00000002,
  68. IRQ_SPI2 = 0x00000004,
  69. IRQ_SPI3 = 0x00000008,
  70. IRQ_SPI4 = 0x00000010,
  71. IRQ_SPI5 = 0x00000020,
  72. IRQ_SPI6 = 0x00000040,
  73. IRQ_I2C0 = 0x00000100,
  74. IRQ_I2C1 = 0x00000200,
  75. IRQ_I2C2 = 0x00000400,
  76. IRQ_I2C3 = 0x00000800,
  77. IRQ_I2C4 = 0x00001000,
  78. IRQ_I2C5 = 0x00002000,
  79. IRQ_I2C6 = 0x00004000,
  80. IRQ_I2C7 = 0x00008000,
  81. IRQ_UART5 = 0x00010000,
  82. IRQ_UART4 = 0x00020000,
  83. IRQ_UART3 = 0x00040000,
  84. IRQ_UART2 = 0x00080000,
  85. IRQ_UART0 = 0x00100000
  86. } PACTL_CS_VAL;
  87. // 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
  88. #define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
  89. #define TIMER_IRQ 30
  90. #define NON_SECURE_TIMER_IRQ (1 << 1)
  91. /* GIC */
  92. #define INTC_BASE (0xff800000)
  93. #define ARM_GIC_NR_IRQS (512)
  94. #define ARM_GIC_MAX_NR (512)
  95. #define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
  96. #define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
  97. #define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)
  98. #define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000)
  99. #define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
  100. #define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
  101. #define GIC_IRQ_START 0
  102. #define GIC_ACK_INTID_MASK 0x000003ff
  103. /* the basic constants and interfaces needed by gic */
  104. rt_inline rt_uint32_t platform_get_gic_dist_base(void)
  105. {
  106. return GIC_PL400_DISTRIBUTOR_PPTR;
  107. }
  108. rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
  109. {
  110. return GIC_PL400_CONTROLLER_PPTR;
  111. }
  112. static inline void __DSB(void)
  113. {
  114. __asm__ volatile ("dsb 0xF":::"memory");
  115. }
  116. #endif