ccm_pll_reg_define.h 6.3 KB

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  1. /*
  2. * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
  3. * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
  4. * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
  5. * Freescale Semiconductor, Inc.
  6. */
  7. #ifndef _CCM_PLL_REG_DEFINE_H_
  8. #define _CCM_PLL_REG_DEFINE_H_
  9. //#########################################
  10. //# DPLLIP peripheral defines
  11. //#########################################
  12. #define DPLLIP_DP_CTL_OFFSET 0x000
  13. #define DPLLIP_DP_CONFIG_OFFSET 0x004
  14. #define DPLLIP_DP_OP_OFFSET 0x008
  15. #define DPLLIP_DP_MFD_OFFSET 0x00C
  16. #define DPLLIP_DP_MFN_OFFSET 0x010
  17. #define DPLLIP_DP_MFNMINUS_OFFSET 0x014
  18. #define DPLLIP_DP_MFNPLUS_OFFSET 0x018
  19. #define DPLLIP_DP_HFS_OP_OFFSET 0x01C
  20. #define DPLLIP_DP_HFS_MFD_OFFSET 0x020
  21. #define DPLLIP_DP_HFS_MFN_OFFSET 0x024
  22. #define DPLLIP_DP_MFN_TOGC_OFFSET 0x028
  23. #define DPLLIP_DP_DESTAT_OFFSET 0x02C
  24. #define DPLLIP1_DP_CONFIG DPLLIP1_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
  25. #define DPLLIP1_DP_CTL DPLLIP1_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
  26. #define DPLLIP1_DP_OP DPLLIP1_BASE_ADDR+DPLLIP_DP_OP_OFFSET
  27. #define DPLLIP1_DP_MFD DPLLIP1_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
  28. #define DPLLIP1_DP_MFN DPLLIP1_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
  29. #define DPLLIP2_DP_CONFIG DPLLIP2_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
  30. #define DPLLIP2_DP_CTL DPLLIP2_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
  31. #define DPLLIP2_DP_OP DPLLIP2_BASE_ADDR+DPLLIP_DP_OP_OFFSET
  32. #define DPLLIP2_DP_MFD DPLLIP2_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
  33. #define DPLLIP2_DP_MFN DPLLIP2_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
  34. #define DPLLIP3_DP_CONFIG DPLLIP3_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
  35. #define DPLLIP3_DP_CTL DPLLIP3_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
  36. #define DPLLIP3_DP_OP DPLLIP3_BASE_ADDR+DPLLIP_DP_OP_OFFSET
  37. #define DPLLIP3_DP_MFD DPLLIP3_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
  38. #define DPLLIP3_DP_MFN DPLLIP3_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
  39. //#########################################
  40. //# CCM peripheral defines
  41. //#########################################
  42. #define CCM_CCR_OFFSET 0x00
  43. #define CCM_CCDR_OFFSET 0x04
  44. #define CCM_CSR_OFFSET 0x08
  45. #define CCM_CCSR_OFFSET 0x0C
  46. #define CCM_CACRR_OFFSET 0x10
  47. #define CCM_CBCDR_OFFSET 0x14
  48. #define CCM_CBCMR_OFFSET 0X18
  49. #define CCM_CSCMR1_OFFSET 0x1c
  50. #define CCM_CSCMR2_OFFSET 0x20
  51. #define CCM_CSCDR1_OFFSET 0x24
  52. #define CCM_CS1CDR_OFFSET 0x28
  53. #define CCM_CS2CDR_OFFSET 0x2c
  54. #define CCM_CDCDR_OFFSET 0x30
  55. #define CCM_CHSCCDR_OFFSET 0x34
  56. #define CCM_CSCDR2_OFFSET 0x38
  57. #define CCM_CSCDR3_OFFSET 0x3c
  58. #define CCM_CSCDR4_OFFSET 0x40
  59. #define CCM_CWDR_OFFSET 0x44
  60. #define CCM_CDHIPR_OFFSET 0x48
  61. #define CCM_CDCR_OFFSET 0x4c
  62. #define CCM_CTOR_OFFSET 0x50
  63. #define CCM_CLPCR_OFFSET 0x54
  64. #define CCM_CISR_OFFSET 0x58
  65. #define CCM_CIMR_OFFSET 0x5c
  66. #define CCM_CCOSR_OFFSET 0x60
  67. #define CCM_CGPR_OFFSET 0x64
  68. #define CCM_CCGR0_OFFSET 0x68
  69. #define CCM_CCGR1_OFFSET 0x6c
  70. #define CCM_CCGR2_OFFSET 0x70
  71. #define CCM_CCGR3_OFFSET 0x74
  72. #define CCM_CCGR4_OFFSET 0x78
  73. #define CCM_CCGR5_OFFSET 0x7c
  74. #define CCM_CCGR6_OFFSET 0x80
  75. #define CCM_CCGR7_OFFSET 0x84
  76. #define CCM_CMEOR_OFFSET 0x88
  77. #define CCM_CCR CCM_BASE_ADDR+CCM_CCR_OFFSET
  78. #define CCM_CCDR CCM_BASE_ADDR+CCM_CCDR_OFFSET
  79. #define CCM_CSR CCM_BASE_ADDR+CCM_CSR_OFFSET
  80. #define CCM_CCSR CCM_BASE_ADDR+CCM_CCSR_OFFSET
  81. #define CCM_CACRR CCM_BASE_ADDR+CCM_CACRR_OFFSET
  82. #define CCM_CBCDR CCM_BASE_ADDR+CCM_CBCDR_OFFSET
  83. #define CCM_CBCMR CCM_BASE_ADDR+CCM_CBCMR_OFFSET
  84. #define CCM_CSCMR1 CCM_BASE_ADDR+CCM_CSCMR1_OFFSET
  85. #define CCM_CSCMR2 CCM_BASE_ADDR+CCM_CSCMR2_OFFSET
  86. #define CCM_CSCDR1 CCM_BASE_ADDR+CCM_CSCDR1_OFFSET
  87. #define CCM_CS1CDR CCM_BASE_ADDR+CCM_CS1CDR_OFFSET
  88. #define CCM_CS2CDR CCM_BASE_ADDR+CCM_CS2CDR_OFFSET
  89. #define CCM_CDCDR CCM_BASE_ADDR+CCM_CDCDR_OFFSET
  90. #define CCM_CHSCCDR CCM_BASE_ADDR+CCM_CHSCCDR_OFFSET
  91. #define CCM_CSCDR2 CCM_BASE_ADDR+CCM_CSCDR2_OFFSET
  92. #define CCM_CSCDR3 CCM_BASE_ADDR+CCM_CSCDR3_OFFSET
  93. #define CCM_CSCDR4 CCM_BASE_ADDR+CCM_CSCDR4_OFFSET
  94. #define CCM_CWDR CCM_BASE_ADDR+CCM_CWDR_OFFSET
  95. #define CCM_CDHIPR CCM_BASE_ADDR+CCM_CDHIPR_OFFSET
  96. #define CCM_CDCR CCM_BASE_ADDR+CCM_CDCR_OFFSET
  97. #define CCM_CTOR CCM_BASE_ADDR+CCM_CTOR_OFFSET
  98. #define CCM_CLPCR CCM_BASE_ADDR+CCM_CLPCR_OFFSET
  99. #define CCM_CISR CCM_BASE_ADDR+CCM_CISR_OFFSET
  100. #define CCM_CIMR CCM_BASE_ADDR+CCM_CIMR_OFFSET
  101. #define CCM_CCOSR CCM_BASE_ADDR+CCM_CCOSR_OFFSET
  102. #define CCM_CGPR CCM_BASE_ADDR+CCM_CGPR_OFFSET
  103. #define CCM_CCGR0 CCM_BASE_ADDR+CCM_CCGR0_OFFSET
  104. #define CCM_CCGR1 CCM_BASE_ADDR+CCM_CCGR1_OFFSET
  105. #define CCM_CCGR2 CCM_BASE_ADDR+CCM_CCGR2_OFFSET
  106. #define CCM_CCGR3 CCM_BASE_ADDR+CCM_CCGR3_OFFSET
  107. #define CCM_CCGR4 CCM_BASE_ADDR+CCM_CCGR4_OFFSET
  108. #define CCM_CCGR5 CCM_BASE_ADDR+CCM_CCGR5_OFFSET
  109. #define CCM_CCGR6 CCM_BASE_ADDR+CCM_CCGR6_OFFSET
  110. #define CCM_CCGR7 CCM_BASE_ADDR+CCM_CCGR7_OFFSET
  111. #define CCM_CMEOR CCM_BASE_ADDR+CCM_CMEOR_OFFSET
  112. //#########################################
  113. //# CCM peripheral defines used by prog_pll.c and hardware.c
  114. //#########################################
  115. #define CLKCTL_CCGR1 CCM_CCGR1_OFFSET
  116. #define CLKCTL_CSCMR1 CCM_CSCMR1_OFFSET
  117. #define CLKCTL_CSCDR1 CCM_CSCDR1_OFFSET
  118. #define CLKCTL_CBCMR CCM_CBCMR_OFFSET
  119. #define CLKCTL_CBCDR CCM_CBCDR_OFFSET
  120. #define CLKCTL_CCSR CCM_CCSR_OFFSET
  121. #define CLKCTL_CDHIPR CCM_CDHIPR_OFFSET
  122. #define CLKCTL_CACRR CCM_CACRR_OFFSET
  123. #define CLKCTL_CSCDR2 CCM_CSCDR2_OFFSET
  124. #define CLKCTL_CS1CDR CCM_CS1CDR_OFFSET
  125. #define CLKCTL_CS2CDR CCM_CS2CDR_OFFSET
  126. #define CLKCTL_CSCMR2 CCM_CSCMR2_OFFSET
  127. #define PLL1_BASE_ADDR DPLLIP1_BASE_ADDR
  128. #define PLL2_BASE_ADDR DPLLIP2_BASE_ADDR
  129. #define PLL3_BASE_ADDR DPLLIP3_BASE_ADDR
  130. #define PLL4_BASE_ADDR DPLLIP4_BASE_ADDR
  131. #define PLL_DP_CTL DPLLIP_DP_CTL_OFFSET
  132. #define PLL_DP_CONFIG DPLLIP_DP_CONFIG_OFFSET
  133. #define PLL_DP_OP DPLLIP_DP_OP_OFFSET
  134. #define PLL_DP_MFD DPLLIP_DP_MFD_OFFSET
  135. #define PLL_DP_MFN DPLLIP_DP_MFN_OFFSET
  136. #define PLL_DP_MFNMINUS DPLLIP_DP_MFNMINUS_OFFSET
  137. #define PLL_DP_MFNPLUS DPLLIP_DP_MFNPLUS_OFFSET
  138. #define PLL_DP_HFS_OP DPLLIP_DP_HFS_OP_OFFSET
  139. #define PLL_DP_HFS_MFD DPLLIP_DP_HFS_MFD_OFFSET
  140. #define PLL_DP_HFS_MFN DPLLIP_DP_HFS_MFN_OFFSET
  141. #define PLL_DP_TOGC DPLLIP_DP_MFN_TOGC_OFFSET
  142. #define PLL_DP_DESTAT DPLLIP_DP_DESTAT_OFFSET
  143. #endif