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Branch: stable-v2.0.x
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rt-thread
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libcpu
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arm
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realview-a8-vmm
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interrupt.h

interrupt.h 2.2 KB
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  1. /*
    2. 

  2.  * File      : interrupt.h
    3. 

  3.  * This file is part of RT-Thread RTOS
    4. 

  4.  * COPYRIGHT (C) 2011, RT-Thread Development Team
    5. 

  5.  *
    6. 

  6.  * The license and distribution terms for this file may be
    7. 

  7.  * found in the file LICENSE in this distribution or at
    8. 

  8.  * http://www.rt-thread.org/license/LICENSE
    9. 

  9.  *
    10. 

  10.  * Change Logs:
    11. 

  11.  * Date           Author       Notes
    12. 

  12.  * 2013-07-06     Bernard      first version
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __INTERRUPT_H__
    16. 

  16. #define __INTERRUPT_H__
    17. 

  17. 

  18. #define INT_IRQ     0x00
    19. 

  19. #define INT_FIQ     0x01
    20. 

  20. 

  21. #define INTC_REVISION(hw_base) 		    REG32((hw_base) + 0x0)
    22. 

  22. #define INTC_SYSCONFIG(hw_base) 		REG32((hw_base) + 0x10)
    23. 

  23. #define INTC_SYSSTATUS(hw_base) 		REG32((hw_base) + 0x14)
    24. 

  24. #define INTC_SIR_IRQ(hw_base) 		    REG32((hw_base) + 0x40)
    25. 

  25. #define INTC_SIR_FIQ(hw_base) 		    REG32((hw_base) + 0x44)
    26. 

  26. #define INTC_CONTROL(hw_base) 		    REG32((hw_base) + 0x48)
    27. 

  27. #define INTC_PROTECTION(hw_base) 	    REG32((hw_base) + 0x4c)
    28. 

  28. #define INTC_IDLE(hw_base)  			REG32((hw_base) + 0x50)
    29. 

  29. #define INTC_IRQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x60)
    30. 

  30. #define INTC_FIQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x64)
    31. 

  31. #define INTC_THRESHOLD(hw_base) 		REG32((hw_base) + 0x68)
    32. 

  32. #define INTC_SICR(hw_base)  			REG32((hw_base) + 0x6c)
    33. 

  33. #define INTC_SCR(hw_base, n) 		    REG32((hw_base) + 0x70 + ((n) * 0x04))
    34. 

  34. #define INTC_ITR(hw_base, n) 		    REG32((hw_base) + 0x80 + ((n) * 0x20))
    35. 

  35. #define INTC_MIR(hw_base, n) 		    REG32((hw_base) + 0x84 + ((n) * 0x20))
    36. 

  36. #define INTC_MIR_CLEAR(hw_base, n)  	REG32((hw_base) + 0x88 + ((n) * 0x20))
    37. 

  37. #define INTC_MIR_SET(hw_base, n) 	    REG32((hw_base) + 0x8c + ((n) * 0x20))
    38. 

  38. #define INTC_ISR_SET(hw_base, n) 	    REG32((hw_base) + 0x90 + ((n) * 0x20))
    39. 

  39. #define INTC_ISR_CLEAR(hw_base, n) 	    REG32((hw_base) + 0x94 + ((n) * 0x20))
    40. 

  40. #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
    41. 

  41. #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
    42. 

  42. #define INTC_ILR(hw_base, n)  		    REG32((hw_base) + 0x100 + ((n) * 0x04))
    43. 

  43. 

  44. void rt_hw_interrupt_control(int vector, int priority, int route);
    45. 

  45. int rt_hw_interrupt_get_active(int fiq_irq);
    46. 

  46. void rt_hw_interrupt_ack(int fiq_irq);
    47. 

  47. void rt_hw_interrupt_trigger(int vector);
    48. 

  48. void rt_hw_interrupt_clear(int vector);
    49. 

  49. 

  50. #endif
    51.