format files in zynqmp-r5-axu4ev bsp

bsp/zynqmp-r5-axu4ev/applications/SConscript

@@ -3,7 +3,7 @@ Import('rtconfig')
 from building import *
 
 cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
+src    = Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c

@@ -20,7 +20,7 @@
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a wsy  01/10/10 First release
 * 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
-*		      64-bit changes.
+*              64-bit changes.
 * 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
 *                    Disable extended mode. Perform all 64 bit changes under
@@ -51,7 +51,7 @@
 
 /************************** Function Prototypes ******************************/
 
-void XEmacPs_StubHandler(void);	/* Default handler routine */
+void XEmacPs_StubHandler(void);    /* Default handler routine */
 
 /************************** Variable Definitions *****************************/
 
@@ -78,13 +78,13 @@ void XEmacPs_StubHandler(void);	/* Default handler routine */
 *
 ******************************************************************************/
 LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
-			   UINTPTR EffectiveAddress)
+               UINTPTR EffectiveAddress)
 {
-	/* Verify arguments */
+    /* Verify arguments */
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(CfgPtr != NULL);
 
-	/* Set device base address and ID */
+    /* Set device base address and ID */
     InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
     InstancePtr->Config.BaseAddress = EffectiveAddress;
     InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
@@ -92,12 +92,12 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
     InstancePtr->Config.RefClk = CfgPtr->RefClk;
 #endif
 
-	/* Set callbacks to an initial stub routine */
+    /* Set callbacks to an initial stub routine */
     InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
     InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
     InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
 
-	/* Reset the hardware and set default options */
+    /* Reset the hardware and set default options */
     InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
     XEmacPs_Reset(InstancePtr);
 
@@ -136,68 +136,68 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
 {
     u32 Reg;
 
-	/* Assert bad arguments and conditions */
+    /* Assert bad arguments and conditions */
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
 #if defined  (XCLOCKING)
     if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
-	    Xil_ClockEnable(InstancePtr->Config.RefClk);
-	}
+        Xil_ClockEnable(InstancePtr->Config.RefClk);
+    }
 #endif
 
-	/* Start DMA */
-	/* When starting the DMA channels, both transmit and receive sides
-	 * need an initialized BD list.
-	 */
+    /* Start DMA */
+    /* When starting the DMA channels, both transmit and receive sides
+     * need an initialized BD list.
+     */
     if (InstancePtr->Version == 2) {
-	    Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
-	    Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+        Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+        Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_RXQBASE_OFFSET,
-			   InstancePtr->RxBdRing.BaseBdAddr);
+               XEMACPS_RXQBASE_OFFSET,
+               InstancePtr->RxBdRing.BaseBdAddr);
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_TXQBASE_OFFSET,
-			   InstancePtr->TxBdRing.BaseBdAddr);
-	}
+               XEMACPS_TXQBASE_OFFSET,
+               InstancePtr->TxBdRing.BaseBdAddr);
+    }
 
-	/* clear any existed int status */
+    /* clear any existed int status */
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
+               XEMACPS_IXR_ALL_MASK);
 
-	/* Enable transmitter if not already enabled */
+    /* Enable transmitter if not already enabled */
     if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
-	    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET);
-	    if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					   XEMACPS_NWCTRL_OFFSET,
-				   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
-		}
-	}
-
-	/* Enable receiver if not already enabled */
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                    XEMACPS_NWCTRL_OFFSET);
+        if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                       XEMACPS_NWCTRL_OFFSET,
+                   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+        }
+    }
+
+    /* Enable receiver if not already enabled */
     if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
-	    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET);
-	    if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-					   XEMACPS_NWCTRL_OFFSET,
-				   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
-		}
-	}
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                    XEMACPS_NWCTRL_OFFSET);
+        if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                       XEMACPS_NWCTRL_OFFSET,
+                   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+        }
+    }
 
         /* Enable TX and RX interrupts */
         XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
     XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
-	(u32)XEMACPS_IXR_TXCOMPL_MASK));
+    (u32)XEMACPS_IXR_TXCOMPL_MASK));
 
-	/* Enable TX Q1 Interrupts */
+    /* Enable TX Q1 Interrupts */
     if (InstancePtr->Version > 2)
-	    XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+        XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
 
-	/* Mark as started */
+    /* Mark as started */
     InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
 
     return;
@@ -236,19 +236,19 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
-	/* Disable all interrupts */
+    /* Disable all interrupts */
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
+               XEMACPS_IXR_ALL_MASK);
 
-	/* Disable the receiver & transmitter */
+    /* Disable the receiver & transmitter */
     Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_NWCTRL_OFFSET);
+                XEMACPS_NWCTRL_OFFSET);
     Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
     Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCTRL_OFFSET, Reg);
+               XEMACPS_NWCTRL_OFFSET, Reg);
 
-	/* Mark as stopped */
+    /* Mark as stopped */
     InstancePtr->IsStarted = 0U;
 #if defined  (XCLOCKING)
     Xil_ClockDisable(InstancePtr->Config.RefClk);
@@ -297,7 +297,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
-	/* Stop the device and reset hardware */
+    /* Stop the device and reset hardware */
     XEmacPs_Stop(InstancePtr);
     InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
 
@@ -307,104 +307,104 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
 
     InstancePtr->MaxMtuSize = XEMACPS_MTU;
     InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
-				    XEMACPS_TRL_SIZE;
+                    XEMACPS_TRL_SIZE;
     InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
-				    XEMACPS_HDR_VLAN_SIZE;
+                    XEMACPS_HDR_VLAN_SIZE;
     InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
 
-	/* Setup hardware with default values */
+    /* Setup hardware with default values */
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-		    XEMACPS_NWCTRL_OFFSET,
-			(XEMACPS_NWCTRL_STATCLR_MASK |
-		    XEMACPS_NWCTRL_MDEN_MASK) &
-			(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+            XEMACPS_NWCTRL_OFFSET,
+            (XEMACPS_NWCTRL_STATCLR_MASK |
+            XEMACPS_NWCTRL_MDEN_MASK) &
+            (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
 
     Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-		    XEMACPS_NWCFG_OFFSET);
+            XEMACPS_NWCFG_OFFSET);
     Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
 
     Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
-			(u32)XEMACPS_NWCFG_FDEN_MASK |
-			(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+            (u32)XEMACPS_NWCFG_FDEN_MASK |
+            (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_NWCFG_OFFSET, Reg);
+                    XEMACPS_NWCFG_OFFSET, Reg);
     if (InstancePtr->Version > 2) {
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
-			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
-			    XEMACPS_NWCFG_DWIDTH_64_MASK));
-	}
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+            (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+                XEMACPS_NWCFG_DWIDTH_64_MASK));
+    }
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-		    XEMACPS_DMACR_OFFSET,
-			(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
-				(((((u32)XEMACPS_RX_BUF_SIZE %
-				(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
-				(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
-				(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
-				(u32)XEMACPS_DMACR_RXSIZE_MASK |
-				(u32)XEMACPS_DMACR_TXSIZE_MASK);
+            XEMACPS_DMACR_OFFSET,
+            (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+                (((((u32)XEMACPS_RX_BUF_SIZE %
+                (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+                (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+                (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+                (u32)XEMACPS_DMACR_RXSIZE_MASK |
+                (u32)XEMACPS_DMACR_TXSIZE_MASK);
 
 
     if (InstancePtr->Version > 2) {
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
-			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+            (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
 #if defined(__aarch64__) || defined(__arch64__)
-			(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+            (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
 #endif
-			(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
-	}
+            (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+    }
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
+               XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
 
     XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
     if (InstancePtr->Version > 2)
-	    XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+        XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
     XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
+               XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
 
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
-			   XEMACPS_IXR_ALL_MASK);
+               XEMACPS_IXR_ALL_MASK);
 
     Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_ISR_OFFSET);
+                XEMACPS_ISR_OFFSET);
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   Reg);
+               Reg);
 
     XEmacPs_ClearHash(InstancePtr);
 
     for (i = 1U; i < 5U; i++) {
-		(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
-		(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
-	}
+        (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+        (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+    }
 
-	/* clear all counters */
+    /* clear all counters */
     for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
-	     i++) {
-		(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+         i++) {
+        (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
                                    XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
-	}
+    }
 
-	/* Disable the receiver */
+    /* Disable the receiver */
     Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_NWCTRL_OFFSET);
+                XEMACPS_NWCTRL_OFFSET);
     Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			   XEMACPS_NWCTRL_OFFSET, Reg);
+               XEMACPS_NWCTRL_OFFSET, Reg);
 
-	/* Sync default options with hardware but leave receiver and
+    /* Sync default options with hardware but leave receiver and
          * transmitter disabled. They get enabled with XEmacPs_Start() if
-	 * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+     * XEMACPS_TRANSMITTER_ENABLE_OPTION and
          * XEMACPS_RECEIVER_ENABLE_OPTION are set.
-	 */
-	(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
-			    ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
-			      (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+     */
+    (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+                ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+                  (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
 
-	(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+    (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
 }
 
 
@@ -436,9 +436,9 @@ void XEmacPs_StubHandler(void)
 *
 ******************************************************************************/
 void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
-			 u16 Direction)
+             u16 Direction)
 {
-	/* Assert bad arguments and conditions */
+    /* Assert bad arguments and conditions */
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
@@ -448,33 +448,33 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
         }
 
     if (QueueNum == 0x00U) {
-	    if (Direction == XEMACPS_SEND) {
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_TXQBASE_OFFSET,
-				(QPtr & ULONG64_LO_MASK));
-		} else {
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_RXQBASE_OFFSET,
-				(QPtr & ULONG64_LO_MASK));
-		}
-	}
-	 else {
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-		    XEMACPS_TXQ1BASE_OFFSET,
-			(QPtr & ULONG64_LO_MASK));
-	}
+        if (Direction == XEMACPS_SEND) {
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_TXQBASE_OFFSET,
+                (QPtr & ULONG64_LO_MASK));
+        } else {
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_RXQBASE_OFFSET,
+                (QPtr & ULONG64_LO_MASK));
+        }
+    }
+     else {
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+            XEMACPS_TXQ1BASE_OFFSET,
+            (QPtr & ULONG64_LO_MASK));
+    }
 #ifdef __aarch64__
     if (Direction == XEMACPS_SEND) {
-		/* Set the MSB of TX Queue start address */
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_MSBBUF_TXQBASE_OFFSET,
-				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
-	} else {
-		/* Set the MSB of RX Queue start address */
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			    XEMACPS_MSBBUF_RXQBASE_OFFSET,
-				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
-	}
+        /* Set the MSB of TX Queue start address */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_MSBBUF_TXQBASE_OFFSET,
+                (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+    } else {
+        /* Set the MSB of RX Queue start address */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_MSBBUF_RXQBASE_OFFSET,
+                (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+    }
 #endif
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h

@@ -241,46 +241,46 @@
  * ----- ---- -------- -------------------------------------------------------
  * 1.00a wsy  01/10/10 First release
  * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
- *		       xemacps_bdring.c is modified. Earlier it was checking for
- *		       "BdLimit"(passed argument) number of BDs for finding out
- *		       which BDs are successfully processed. Now one more check
- *		       is added. It looks for BDs till the current BD pointer
- *		       reaches HwTail. By doing this processing time is saved.
+ *               xemacps_bdring.c is modified. Earlier it was checking for
+ *               "BdLimit"(passed argument) number of BDs for finding out
+ *               which BDs are successfully processed. Now one more check
+ *               is added. It looks for BDs till the current BD pointer
+ *               reaches HwTail. By doing this processing time is saved.
  * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
- *		       xemacps_bdring.c is modified. Now start of packet is
- *		       searched for returning the number of BDs processed.
+ *               xemacps_bdring.c is modified. Now start of packet is
+ *               searched for returning the number of BDs processed.
  * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
- *		       registers. Added a new API to set the bust length.
- *		       Added some new hash-defines.
+ *               registers. Added a new API to set the bust length.
+ *               Added some new hash-defines.
  * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
- *		       Rx errors. Under heavy Rx traffic, there will be a large
- *		       number of errors related to receive buffer not available.
- *		       Because of a HW bug (SI #692601), under such heavy errors,
- *		       the Rx data path can become unresponsive. To reduce the
- *		       probabilities for hitting this HW bug, the SW writes to
- *		       bit 18 to flush a packet from Rx DPRAM immediately. The
- *		       changes for it are done in the function
- *		       XEmacPs_IntrHandler.
+ *               Rx errors. Under heavy Rx traffic, there will be a large
+ *               number of errors related to receive buffer not available.
+ *               Because of a HW bug (SI #692601), under such heavy errors,
+ *               the Rx data path can become unresponsive. To reduce the
+ *               probabilities for hitting this HW bug, the SW writes to
+ *               bit 18 to flush a packet from Rx DPRAM immediately. The
+ *               changes for it are done in the function
+ *               XEmacPs_IntrHandler.
  * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
- *		       removed. It is expected that all BDs are allocated in
- *		       from uncached area.
+ *               removed. It is expected that all BDs are allocated in
+ *               from uncached area.
  * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- *			    to 0x1fff. This fixes the CR#744902.
- *			  Made changes in example file xemacps_example.h to fix compilation
- *			  issues with iarcc compiler.
+ *                to 0x1fff. This fixes the CR#744902.
+ *              Made changes in example file xemacps_example.h to fix compilation
+ *              issues with iarcc compiler.
  * 2.0   adk  10/12/13 Updated as per the New Tcl API's
  * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
  * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
- *		       address in xparameters.h when GMII to RGMII converter
- *		       is present in hw.
+ *               address in xparameters.h when GMII to RGMII converter
+ *               is present in hw.
  * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- *		       changes.
+ *               changes.
  * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
  *                    1000BASE-X mode export proper values to the xparameters.h
  *                    file. Changes are made in the driver tcl file.
  * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
  *                    configured with PCS/PMA Core. Changes are made in the
- *		       test app tcl(CR:827686).
+ *               test app tcl(CR:827686).
  * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
  * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
  *                     Disable extended mode. Perform all 64 bit changes under
@@ -302,10 +302,10 @@
  * 3.5   hk   08/14/17 Update cache coherency information of the interface in
  *                     its config structure.
  * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- *		       changed to volatile.
- *		       Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *               changed to volatile.
+ *               Add API XEmacPs_BdRingPtrReset() to reset pointers
  * 3.8   hk   07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- *	 hk   09/17/18 Fix PTP interrupt masks and cleanup comments.
+ *     hk   09/17/18 Fix PTP interrupt masks and cleanup comments.
  * 3.9   hk   01/23/19 Add RX watermark support
  * 3.11  sd   02/14/20 Add clock support
  *
@@ -313,8 +313,8 @@
  *
  ****************************************************************************/
 
-#ifndef XEMACPS_H		/* prevent circular inclusions */
-#define XEMACPS_H		/* by using protection macros */
+#ifndef XEMACPS_H        /* prevent circular inclusions */
+#define XEMACPS_H        /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -447,13 +447,13 @@ extern "C" {
 /* The next few constants help upper layers determine the size of memory
  * pools used for Ethernet buffers and descriptor lists.
  */
-#define XEMACPS_MAC_ADDR_SIZE   6U	/* size of Ethernet header */
+#define XEMACPS_MAC_ADDR_SIZE   6U    /* size of Ethernet header */
 
-#define XEMACPS_MTU             1500U	/* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO       10240U	/* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE        14U	/* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
+#define XEMACPS_MTU             1500U    /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO       10240U    /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE        14U    /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE   18U    /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE        4U    /* size of Ethernet trailer (FCS) */
 #define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
         XEMACPS_TRL_SIZE)
 #define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
@@ -464,8 +464,8 @@ extern "C" {
 /* DMACR Bust length hash defines */
 
 #define XEMACPS_SINGLE_BURST    0x00000001
-#define XEMACPS_4BYTE_BURST	    0x00000004
-#define XEMACPS_8BYTE_BURST	    0x00000008
+#define XEMACPS_4BYTE_BURST        0x00000004
+#define XEMACPS_8BYTE_BURST        0x00000008
 #define XEMACPS_16BYTE_BURST    0x00000010
 
 
@@ -499,7 +499,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
  *
  */
 typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
-				     u32 ErrorWord);
+                     u32 ErrorWord);
 
 /*@}*/
 
@@ -507,12 +507,12 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
  * This typedef contains configuration information for a device.
  */
 typedef struct {
-    u16 DeviceId;	/**< Unique ID  of device */
+    u16 DeviceId;    /**< Unique ID  of device */
     UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
     u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
-				* describes whether Cache Coherent or not */
+                * describes whether Cache Coherent or not */
 #if defined  (XCLOCKING)
-    u32 RefClk;	/**< Input clock */
+    u32 RefClk;    /**< Input clock */
 #endif
 } XEmacPs_Config;
 
@@ -523,13 +523,13 @@ typedef struct {
  * to a structure of this type is then passed to the driver API functions.
  */
 typedef struct XEmacPs_Instance {
-    XEmacPs_Config Config;	/* Hardware configuration */
-    u32 IsStarted;		/* Device is currently started */
-    u32 IsReady;		/* Device is initialized and ready */
-    u32 Options;		/* Current options word */
+    XEmacPs_Config Config;    /* Hardware configuration */
+    u32 IsStarted;        /* Device is currently started */
+    u32 IsReady;        /* Device is initialized and ready */
+    u32 Options;        /* Current options word */
 
-    XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
-    XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
+    XEmacPs_BdRing TxBdRing;    /* Transmit BD ring */
+    XEmacPs_BdRing RxBdRing;    /* Receive BD ring */
 
     XEmacPs_Handler SendHandler;
     XEmacPs_Handler RecvHandler;
@@ -599,8 +599,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntEnable(InstancePtr, Mask)                            \
     XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-	    XEMACPS_IER_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
+        XEMACPS_IER_OFFSET,                                     \
+        ((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -620,8 +620,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntDisable(InstancePtr, Mask)                           \
     XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-	    XEMACPS_IDR_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
+        XEMACPS_IDR_OFFSET,                                     \
+        ((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -641,8 +641,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
     XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-	    XEMACPS_INTQ1_IER_OFFSET,                                \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+        XEMACPS_INTQ1_IER_OFFSET,                                \
+        ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -662,8 +662,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
     XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-	    XEMACPS_INTQ1_IDR_OFFSET,                               \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+        XEMACPS_INTQ1_IDR_OFFSET,                               \
+        ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -740,17 +740,17 @@ typedef struct XEmacPs_Instance {
 *
 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
 * @param High is the non-zero RX high watermark value. When SRAM fill level
-*	 is above this, a pause frame will be sent.
+*     is above this, a pause frame will be sent.
 * @param Low is the non-zero RX low watermark value. When SRAM fill level
-*	 is below this, a zero length pause frame will be sent IF the last
-*	 pause frame sent was non-zero.
+*     is below this, a zero length pause frame will be sent IF the last
+*     pause frame sent was non-zero.
 *
 * @return None
 *
 * @note
 *
 * Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* 				    u16 Low)
+*                     u16 Low)
 *
 *****************************************************************************/
 #define XEmacPs_SetRXWatermark(InstancePtr, High, Low)                     \
@@ -780,12 +780,12 @@ typedef struct XEmacPs_Instance {
  * Initialization functions in xemacps.c
  */
 LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
-			   UINTPTR EffectiveAddress);
+               UINTPTR EffectiveAddress);
 void XEmacPs_Start(XEmacPs *InstancePtr);
 void XEmacPs_Stop(XEmacPs *InstancePtr);
 void XEmacPs_Reset(XEmacPs *InstancePtr);
 void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
-			 u16 Direction);
+             u16 Direction);
 
 /*
  * Lookup configuration in xemacps_sinit.c
@@ -797,7 +797,7 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
  * DMA only and FIFO is not supported. This DMA does not support coalescing.
  */
 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-		    void *FuncPointer, void *CallBackRef);
+            void *FuncPointer, void *CallBackRef);
 void XEmacPs_IntrHandler(void *XEmacPsPtr);
 
 /*
@@ -816,13 +816,13 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
 
 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
-			    XEmacPs_MdcDiv Divisor);
+                XEmacPs_MdcDiv Divisor);
 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
 LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
-		     u32 RegisterNum, u16 *PhyDataPtr);
+             u32 RegisterNum, u16 *PhyDataPtr);
 LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
-		      u32 RegisterNum, u16 PhyData);
+              u32 RegisterNum, u16 PhyData);
 LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
 
 LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bd.h

@@ -51,8 +51,8 @@
  * ***************************************************************************
  */
 
-#ifndef XEMACPS_BD_H		/* prevent circular inclusions */
-#define XEMACPS_BD_H		/* by using protection macros */
+#ifndef XEMACPS_BD_H        /* prevent circular inclusions */
+#define XEMACPS_BD_H        /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -117,7 +117,7 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
 *
 *****************************************************************************/
 #define XEmacPs_BdRead(BaseAddress, Offset)             \
-	(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+    (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
 
 /****************************************************************************/
 /**
@@ -153,10 +153,10 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
  *****************************************************************************/
 #if defined(__aarch64__) || defined(__arch64__)
 #define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,		\
-			(u32)((Addr) & ULONG64_LO_MASK));		\
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,		\
-	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,        \
+            (u32)((Addr) & ULONG64_LO_MASK));        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,        \
+    (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
 #else
 #define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
     XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
@@ -180,9 +180,9 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
 #define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
     XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
     ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
-	~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
-    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, 	\
-	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+    ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,     \
+    (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
 #else
 #define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
     XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
@@ -239,8 +239,8 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
  *****************************************************************************/
 #if defined(__aarch64__) || defined(__arch64__)
 #define XEmacPs_BdGetBufAddr(BdPtr)                               \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
-	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |          \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
 #else
 #define XEmacPs_BdGetBufAddr(BdPtr)                               \
     (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c

@@ -19,20 +19,20 @@
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a wsy  01/10/10 First release
 * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
-*		      Earlier it used to search in "BdLimit" number of BDs to
-*		      know which BDs are processed. Now one more check is
-*		      added. It looks for BDs till the current BD pointer
-*		      reaches HwTail. By doing this processing time is saved.
+*              Earlier it used to search in "BdLimit" number of BDs to
+*              know which BDs are processed. Now one more check is
+*              added. It looks for BDs till the current BD pointer
+*              reaches HwTail. By doing this processing time is saved.
 * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
-*		      xemacps_bdring.c is modified. Now start of packet is
-*		      searched for returning the number of BDs processed.
+*              xemacps_bdring.c is modified. Now start of packet is
+*              searched for returning the number of BDs processed.
 * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
-*		      removed. It is expected that all BDs are allocated in
-*		      from uncached area. Fix for CR #663885.
+*              removed. It is expected that all BDs are allocated in
+*              from uncached area. Fix for CR #663885.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.6   rb   09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
-* 		      pointers
+*               pointers
 *
 * </pre>
 ******************************************************************************/
@@ -174,73 +174,73 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
  * Make sure to pass in the right alignment value.
  *****************************************************************************/
 LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
-			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+              UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
 {
     u32 i;
     UINTPTR BdVirtAddr;
     UINTPTR BdPhyAddr;
     UINTPTR VirtAddrLoc = VirtAddr;
 
-	/* In case there is a failure prior to creating list, make sure the
-	 * following attributes are 0 to prevent calls to other functions
-	 * from doing anything.
-	 */
+    /* In case there is a failure prior to creating list, make sure the
+     * following attributes are 0 to prevent calls to other functions
+     * from doing anything.
+     */
     RingPtr->AllCnt = 0U;
     RingPtr->FreeCnt = 0U;
     RingPtr->HwCnt = 0U;
     RingPtr->PreCnt = 0U;
     RingPtr->PostCnt = 0U;
 
-	/* Make sure Alignment parameter meets minimum requirements */
+    /* Make sure Alignment parameter meets minimum requirements */
     if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Make sure Alignment is a power of 2 */
+    /* Make sure Alignment is a power of 2 */
     if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Make sure PhysAddr and VirtAddr are on same Alignment */
+    /* Make sure PhysAddr and VirtAddr are on same Alignment */
     if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Is BdCount reasonable? */
+    /* Is BdCount reasonable? */
     if (BdCount == 0x00000000U) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Figure out how many bytes will be between the start of adjacent BDs */
+    /* Figure out how many bytes will be between the start of adjacent BDs */
     RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
 
-	/* Must make sure the ring doesn't span address 0x00000000. If it does,
-	 * then the next/prev BD traversal macros will fail.
-	 */
+    /* Must make sure the ring doesn't span address 0x00000000. If it does,
+     * then the next/prev BD traversal macros will fail.
+     */
     if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
-	/* Initial ring setup:
-	 *  - Clear the entire space
-	 *  - Setup each BD's BDA field with the physical address of the next BD
-	 */
-	(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+    /* Initial ring setup:
+     *  - Clear the entire space
+     *  - Setup each BD's BDA field with the physical address of the next BD
+     */
+    (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
 
     BdVirtAddr = VirtAddrLoc;
     BdPhyAddr = PhysAddr + RingPtr->Separation;
     for (i = 1U; i < BdCount; i++) {
-	    BdVirtAddr += RingPtr->Separation;
-	    BdPhyAddr += RingPtr->Separation;
-	}
+        BdVirtAddr += RingPtr->Separation;
+        BdPhyAddr += RingPtr->Separation;
+    }
 
-	/* Setup and initialize pointers and counters */
+    /* Setup and initialize pointers and counters */
     RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
     RingPtr->BaseBdAddr = VirtAddrLoc;
     RingPtr->PhysBaseAddr = PhysAddr;
     RingPtr->HighBdAddr = BdVirtAddr;
     RingPtr->Length =
-		((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+        ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
     RingPtr->AllCnt = (u32)BdCount;
     RingPtr->FreeCnt = (u32)BdCount;
     RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
@@ -279,47 +279,47 @@ LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
-			 u8 Direction)
+             u8 Direction)
 {
     u32 i;
     UINTPTR CurBd;
 
-	/* Can't do this function if there isn't a ring */
+    /* Can't do this function if there isn't a ring */
     if (RingPtr->AllCnt == 0x00000000U) {
-	    return (LONG)(XST_DMA_SG_NO_LIST);
-	}
+        return (LONG)(XST_DMA_SG_NO_LIST);
+    }
 
-	/* Can't do this function with the channel running */
+    /* Can't do this function with the channel running */
     if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-	    return (LONG)(XST_DEVICE_IS_STARTED);
-	}
+        return (LONG)(XST_DEVICE_IS_STARTED);
+    }
 
-	/* Can't do this function with some of the BDs in use */
+    /* Can't do this function with some of the BDs in use */
     if (RingPtr->FreeCnt != RingPtr->AllCnt) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
     if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Starting from the top of the ring, save BD.Next, overwrite the entire
-	 * BD with the template, then restore BD.Next
-	 */
+    /* Starting from the top of the ring, save BD.Next, overwrite the entire
+     * BD with the template, then restore BD.Next
+     */
     CurBd = RingPtr->BaseBdAddr;
     for (i = 0U; i < RingPtr->AllCnt; i++) {
-	    memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+        memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
     CurBd += RingPtr->Separation;
-	}
+    }
 
     CurBd -= RingPtr->Separation;
 
     if (Direction == XEMACPS_RECV) {
-	    XEmacPs_BdSetRxWrap(CurBd);
-	}
+        XEmacPs_BdSetRxWrap(CurBd);
+    }
     else {
-	    XEmacPs_BdSetTxWrap(CurBd);
-	}
+        XEmacPs_BdSetTxWrap(CurBd);
+    }
 
     return (LONG)(XST_SUCCESS);
 }
@@ -398,20 +398,20 @@ LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			 XEmacPs_Bd ** BdSetPtr)
+             XEmacPs_Bd ** BdSetPtr)
 {
     LONG Status;
-	/* Enough free BDs available for the request? */
+    /* Enough free BDs available for the request? */
     if (RingPtr->FreeCnt < NumBd) {
-	    Status = (LONG)(XST_FAILURE);
-	} else {
-	/* Set the return argument and move FreeHead forward */
-	*BdSetPtr = RingPtr->FreeHead;
+        Status = (LONG)(XST_FAILURE);
+    } else {
+    /* Set the return argument and move FreeHead forward */
+    *BdSetPtr = RingPtr->FreeHead;
     XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
     RingPtr->FreeCnt -= NumBd;
     RingPtr->PreCnt += NumBd;
-	    Status = (LONG)(XST_SUCCESS);
-	}
+        Status = (LONG)(XST_SUCCESS);
+    }
     return Status;
 }
 
@@ -478,23 +478,23 @@ LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			   XEmacPs_Bd * BdSetPtr)
+               XEmacPs_Bd * BdSetPtr)
 {
     LONG Status;
-	(void) BdSetPtr;
+    (void) BdSetPtr;
     Xil_AssertNonvoid(RingPtr != NULL);
     Xil_AssertNonvoid(BdSetPtr != NULL);
 
-	/* Enough BDs in the free state for the request? */
+    /* Enough BDs in the free state for the request? */
     if (RingPtr->PreCnt < NumBd) {
-	    Status = (LONG)(XST_FAILURE);
-	} else {
-	/* Set the return argument and move FreeHead backward */
-	    XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+        Status = (LONG)(XST_FAILURE);
+    } else {
+    /* Set the return argument and move FreeHead backward */
+        XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
     RingPtr->FreeCnt += NumBd;
     RingPtr->PreCnt -= NumBd;
-	    Status = (LONG)(XST_SUCCESS);
-	}
+        Status = (LONG)(XST_SUCCESS);
+    }
     return Status;
 }
 
@@ -526,32 +526,32 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-		    XEmacPs_Bd * BdSetPtr)
+            XEmacPs_Bd * BdSetPtr)
 {
     XEmacPs_Bd *CurBdPtr;
     u32 i;
     LONG Status;
-	/* if no bds to process, simply return. */
+    /* if no bds to process, simply return. */
     if (0U == NumBd){
-	    Status = (LONG)(XST_SUCCESS);
-	} else {
-	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+        Status = (LONG)(XST_SUCCESS);
+    } else {
+    /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
     if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
-		    Status = (LONG)(XST_DMA_SG_LIST_ERROR);
-		} else {
+            Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+        } else {
     CurBdPtr = BdSetPtr;
-		    for (i = 0U; i < NumBd; i++) {
-			    CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
-	}
-	/* Adjust ring pointers & counters */
+            for (i = 0U; i < NumBd; i++) {
+                CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+    }
+    /* Adjust ring pointers & counters */
     XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
     RingPtr->PreCnt -= NumBd;
     RingPtr->HwTail = CurBdPtr;
     RingPtr->HwCnt += NumBd;
 
-		    Status = (LONG)(XST_SUCCESS);
-		}
-	}
+            Status = (LONG)(XST_SUCCESS);
+        }
+    }
     return Status;
 }
 
@@ -623,7 +623,7 @@ LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
  *
  *****************************************************************************/
 u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr)
+                 XEmacPs_Bd ** BdSetPtr)
 {
     XEmacPs_Bd *CurBdPtr;
     u32 BdStr = 0U;
@@ -636,65 +636,65 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
     BdCount = 0U;
     BdPartialCount = 0U;
 
-	/* If no BDs in work group, then there's nothing to search */
+    /* If no BDs in work group, then there's nothing to search */
     if (RingPtr->HwCnt == 0x00000000U) {
-		*BdSetPtr = NULL;
-	    Status = 0U;
-	} else {
-
-	    if (BdLimitLoc > RingPtr->HwCnt){
-		    BdLimitLoc = RingPtr->HwCnt;
-	}
-	/* Starting at HwHead, keep moving forward in the list until:
-	 *  - A BD is encountered with its new/used bit set which means
-	 *    hardware has not completed processing of that BD.
-	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
-	 *  - The number of requested BDs has been processed
-	 */
-	    while (BdCount < BdLimitLoc) {
-		/* Read the status */
-		    if(CurBdPtr != NULL){
-	    BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
-			}
-
-		    if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
-			    Sop = 1U;
-			}
-		    if (Sop == 0x00000001U) {
-		    BdCount++;
-		    BdPartialCount++;
-		}
-
-		/* hardware has processed this BD so check the "last" bit.
-		 * If it is clear, then there are more BDs for the current
-		 * packet. Keep a count of these partial packet BDs.
-		 */
-		    if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
-			    Sop = 0U;
-			    BdPartialCount = 0U;
-		}
-
-		/* Move on to next BD in work group */
-	    CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
-	}
-
-	/* Subtract off any partial packet BDs found */
+        *BdSetPtr = NULL;
+        Status = 0U;
+    } else {
+
+        if (BdLimitLoc > RingPtr->HwCnt){
+            BdLimitLoc = RingPtr->HwCnt;
+    }
+    /* Starting at HwHead, keep moving forward in the list until:
+     *  - A BD is encountered with its new/used bit set which means
+     *    hardware has not completed processing of that BD.
+     *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+     *  - The number of requested BDs has been processed
+     */
+        while (BdCount < BdLimitLoc) {
+        /* Read the status */
+            if(CurBdPtr != NULL){
+        BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+            }
+
+            if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+                Sop = 1U;
+            }
+            if (Sop == 0x00000001U) {
+            BdCount++;
+            BdPartialCount++;
+        }
+
+        /* hardware has processed this BD so check the "last" bit.
+         * If it is clear, then there are more BDs for the current
+         * packet. Keep a count of these partial packet BDs.
+         */
+            if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+                Sop = 0U;
+                BdPartialCount = 0U;
+        }
+
+        /* Move on to next BD in work group */
+        CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+    }
+
+    /* Subtract off any partial packet BDs found */
         BdCount -= BdPartialCount;
 
-	/* If BdCount is non-zero then BDs were found to return. Set return
-	 * parameters, update pointers and counters, return success
-	 */
-	    if (BdCount > 0x00000000U) {
-		*BdSetPtr = RingPtr->HwHead;
-	    RingPtr->HwCnt -= BdCount;
-	    RingPtr->PostCnt += BdCount;
-	    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-		    Status = (BdCount);
-		} else {
-			*BdSetPtr = NULL;
-		    Status = 0U;
-	}
-	}
+    /* If BdCount is non-zero then BDs were found to return. Set return
+     * parameters, update pointers and counters, return success
+     */
+        if (BdCount > 0x00000000U) {
+        *BdSetPtr = RingPtr->HwHead;
+        RingPtr->HwCnt -= BdCount;
+        RingPtr->PostCnt += BdCount;
+        XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+            Status = (BdCount);
+        } else {
+            *BdSetPtr = NULL;
+            Status = 0U;
+    }
+    }
     return Status;
 }
 
@@ -767,7 +767,7 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
  *
  *****************************************************************************/
 u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr)
+                 XEmacPs_Bd ** BdSetPtr)
 {
     XEmacPs_Bd *CurBdPtr;
     u32 BdStr = 0U;
@@ -779,61 +779,61 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
     BdCount = 0U;
     BdPartialCount = 0U;
 
-	/* If no BDs in work group, then there's nothing to search */
+    /* If no BDs in work group, then there's nothing to search */
     if (RingPtr->HwCnt == 0x00000000U) {
-		*BdSetPtr = NULL;
-	    Status = 0U;
-	} else {
-
-	/* Starting at HwHead, keep moving forward in the list until:
-	 *  - A BD is encountered with its new/used bit set which means
-	 *    hardware has completed processing of that BD.
-	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
-	 *  - The number of requested BDs has been processed
-	 */
+        *BdSetPtr = NULL;
+        Status = 0U;
+    } else {
+
+    /* Starting at HwHead, keep moving forward in the list until:
+     *  - A BD is encountered with its new/used bit set which means
+     *    hardware has completed processing of that BD.
+     *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+     *  - The number of requested BDs has been processed
+     */
     while (BdCount < BdLimit) {
 
-		/* Read the status */
-		    if(CurBdPtr!=NULL){
-	    BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
-			}
-		    if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
-		    break;
-		}
+        /* Read the status */
+            if(CurBdPtr!=NULL){
+        BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+            }
+            if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+            break;
+        }
 
-	    BdCount++;
+        BdCount++;
 
-		/* hardware has processed this BD so check the "last" bit. If
+        /* hardware has processed this BD so check the "last" bit. If
                  * it is clear, then there are more BDs for the current packet.
                  * Keep a count of these partial packet BDs.
-		 */
-		    if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
-			    BdPartialCount = 0U;
-			} else {
-		    BdPartialCount++;
-		}
-
-		/* Move on to next BD in work group */
-	    CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
-	}
-
-	/* Subtract off any partial packet BDs found */
+         */
+            if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+                BdPartialCount = 0U;
+            } else {
+            BdPartialCount++;
+        }
+
+        /* Move on to next BD in work group */
+        CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+    }
+
+    /* Subtract off any partial packet BDs found */
     BdCount -= BdPartialCount;
 
-	/* If BdCount is non-zero then BDs were found to return. Set return
-	 * parameters, update pointers and counters, return success
-	 */
-	    if (BdCount > 0x00000000U) {
-		*BdSetPtr = RingPtr->HwHead;
-	    RingPtr->HwCnt -= BdCount;
-	    RingPtr->PostCnt += BdCount;
-	    XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
-		    Status = (BdCount);
-	}
+    /* If BdCount is non-zero then BDs were found to return. Set return
+     * parameters, update pointers and counters, return success
+     */
+        if (BdCount > 0x00000000U) {
+        *BdSetPtr = RingPtr->HwHead;
+        RingPtr->HwCnt -= BdCount;
+        RingPtr->PostCnt += BdCount;
+        XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+            Status = (BdCount);
+    }
     else {
-		*BdSetPtr = NULL;
-		    Status = 0U;
-	}
+        *BdSetPtr = NULL;
+            Status = 0U;
+    }
 }
     return Status;
 }
@@ -860,24 +860,24 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
  *
  *****************************************************************************/
 LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-		    XEmacPs_Bd * BdSetPtr)
+            XEmacPs_Bd * BdSetPtr)
 {
     LONG Status;
-	/* if no bds to process, simply return. */
+    /* if no bds to process, simply return. */
     if (0x00000000U == NumBd){
-	    Status = (LONG)(XST_SUCCESS);
-	} else {
-	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+        Status = (LONG)(XST_SUCCESS);
+    } else {
+    /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
     if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
-		    Status = (LONG)(XST_DMA_SG_LIST_ERROR);
-		} else {
-	/* Update pointers and counters */
+            Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+        } else {
+    /* Update pointers and counters */
     RingPtr->FreeCnt += NumBd;
     RingPtr->PostCnt -= NumBd;
     XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
-		    Status = (LONG)(XST_SUCCESS);
-		}
-	}
+            Status = (LONG)(XST_SUCCESS);
+        }
+    }
     return Status;
 }
 
@@ -916,84 +916,84 @@ LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
     u32 i;
 
     if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
-	    return (LONG)(XST_INVALID_PARAM);
-	}
+        return (LONG)(XST_INVALID_PARAM);
+    }
 
-	/* Is the list created */
+    /* Is the list created */
     if (RingPtr->AllCnt == 0x00000000U) {
-	    return (LONG)(XST_DMA_SG_NO_LIST);
-	}
+        return (LONG)(XST_DMA_SG_NO_LIST);
+    }
 
-	/* Can't check if channel is running */
+    /* Can't check if channel is running */
     if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
-	    return (LONG)(XST_IS_STARTED);
-	}
+        return (LONG)(XST_IS_STARTED);
+    }
 
-	/* RunState doesn't make sense */
+    /* RunState doesn't make sense */
     if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
-	/* Verify internal pointers point to correct memory space */
+    /* Verify internal pointers point to correct memory space */
     AddrV = (UINTPTR) RingPtr->FreeHead;
     if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
     AddrV = (UINTPTR) RingPtr->PreHead;
     if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
     AddrV = (UINTPTR) RingPtr->HwHead;
     if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
     AddrV = (UINTPTR) RingPtr->HwTail;
     if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
     AddrV = (UINTPTR) RingPtr->PostHead;
     if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
-	/* Verify internal counters add up */
+    /* Verify internal counters add up */
     if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
-	     RingPtr->PostCnt) != RingPtr->AllCnt) {
-	    return (LONG)(XST_DMA_SG_LIST_ERROR);
-	}
+         RingPtr->PostCnt) != RingPtr->AllCnt) {
+        return (LONG)(XST_DMA_SG_LIST_ERROR);
+    }
 
-	/* Verify BDs are linked correctly */
+    /* Verify BDs are linked correctly */
     AddrV = RingPtr->BaseBdAddr;
     AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
 
     for (i = 1U; i < RingPtr->AllCnt; i++) {
-		/* Check BDA for this BD. It should point to next physical addr */
-	    if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
-		    return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-
-		/* Move on to next BD */
-	    AddrV += RingPtr->Separation;
-	    AddrP += RingPtr->Separation;
-	}
+        /* Check BDA for this BD. It should point to next physical addr */
+        if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+            return (LONG)(XST_DMA_SG_LIST_ERROR);
+        }
+
+        /* Move on to next BD */
+        AddrV += RingPtr->Separation;
+        AddrP += RingPtr->Separation;
+    }
 
-	/* Last BD should have wrap bit set */
+    /* Last BD should have wrap bit set */
     if (XEMACPS_SEND == Direction) {
-	    if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
-		    return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-	}
-    else {			/* XEMACPS_RECV */
-	    if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
-		    return (LONG)(XST_DMA_SG_LIST_ERROR);
-		}
-	}
-
-	/* No problems found */
+        if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+            return (LONG)(XST_DMA_SG_LIST_ERROR);
+        }
+    }
+    else {            /* XEMACPS_RECV */
+        if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+            return (LONG)(XST_DMA_SG_LIST_ERROR);
+        }
+    }
+
+    /* No problems found */
     return (LONG)(XST_SUCCESS);
 }
 
@@ -1017,10 +1017,10 @@ static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
     BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
     TempPtr = (u32 *)BdPtr;
     if(TempPtr != NULL) {
-	    DataValueRx = *TempPtr;
-	    DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
-		*TempPtr = DataValueRx;
-	}
+        DataValueRx = *TempPtr;
+        DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+        *TempPtr = DataValueRx;
+    }
 }
 
 /*****************************************************************************/
@@ -1043,10 +1043,10 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
     BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
     TempPtr = (u32 *)BdPtr;
     if(TempPtr != NULL) {
-	    DataValueTx = *TempPtr;
-	    DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
-		*TempPtr = DataValueTx;
-	}
+        DataValueTx = *TempPtr;
+        DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+        *TempPtr = DataValueTx;
+    }
 }
 
 /*****************************************************************************/

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h

@@ -22,14 +22,14 @@
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-*		      changed to volatile.
+*              changed to volatile.
 *
 * </pre>
 *
 ******************************************************************************/
 
-#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
-#define XEMACPS_BDRING_H	/* by using protection macros */
+#ifndef XEMACPS_BDRING_H    /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H    /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -41,21 +41,21 @@ extern "C" {
 /** This is an internal structure used to maintain the DMA list */
 typedef struct {
     UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
-    UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
-    UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
-    u32 Length;	 /**< Total size of ring in bytes */
-    u32 RunState;	 /**< Flag to indicate DMA is started */
-    u32 Separation;	 /**< Number of bytes between the starting address
+    UINTPTR BaseBdAddr;     /**< Virtual address of 1st BD in list */
+    UINTPTR HighBdAddr;     /**< Virtual address of last BD in the list */
+    u32 Length;     /**< Total size of ring in bytes */
+    u32 RunState;     /**< Flag to indicate DMA is started */
+    u32 Separation;     /**< Number of bytes between the starting address
                                   of adjacent BDs */
     XEmacPs_Bd *FreeHead;
-			     /**< First BD in the free group */
+                 /**< First BD in the free group */
     XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
     XEmacPs_Bd *HwHead; /**< First BD in the work group */
     XEmacPs_Bd *HwTail; /**< Last BD in the work group */
     XEmacPs_Bd *PostHead;
-			     /**< First BD in the post-work group */
+                 /**< First BD in the post-work group */
     XEmacPs_Bd *BdaRestart;
-			     /**< BDA to load when channel is started */
+                 /**< BDA to load when channel is started */
 
     volatile u32 HwCnt;    /**< Number of BDs in work group */
     u32 PreCnt;     /**< Number of BDs in pre-work group */
@@ -187,21 +187,21 @@ typedef struct {
  * Scatter gather DMA related functions in xemacps_bdring.c
  */
 LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
-			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+              UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
 LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
-			 u8 Direction);
+             u8 Direction);
 LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			 XEmacPs_Bd ** BdSetPtr);
+             XEmacPs_Bd ** BdSetPtr);
 LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
-			   XEmacPs_Bd * BdSetPtr);
+               XEmacPs_Bd * BdSetPtr);
 LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
-		    XEmacPs_Bd * BdSetPtr);
+            XEmacPs_Bd * BdSetPtr);
 LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
-		    XEmacPs_Bd * BdSetPtr);
+            XEmacPs_Bd * BdSetPtr);
 u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr);
+                 XEmacPs_Bd ** BdSetPtr);
 u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
-				 XEmacPs_Bd ** BdSetPtr);
+                 XEmacPs_Bd ** BdSetPtr);
 LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
 
 void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c

@@ -22,11 +22,11 @@
 
 XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
 {
-	{
-	    XPAR_PSU_ETHERNET_3_DEVICE_ID,
-	    XPAR_PSU_ETHERNET_3_BASEADDR,
-	    XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
-	}
+    {
+        XPAR_PSU_ETHERNET_3_DEVICE_ID,
+        XPAR_PSU_ETHERNET_3_BASEADDR,
+        XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
+    }
 };
 
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c

@@ -62,35 +62,35 @@ void XEmacPs_ResetHw(u32 BaseAddr)
 {
     u32 RegVal;
 
-	/* Disable the interrupts  */
+    /* Disable the interrupts  */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
 
-	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+    /* Stop transmission,disable loopback and Stop tx and Rx engines */
     RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
     RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
-				(u32)XEMACPS_NWCTRL_RXEN_MASK|
-				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
-				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
-	/* Clear the statistic registers, flush the packets in DPRAM*/
+                (u32)XEMACPS_NWCTRL_RXEN_MASK|
+                (u32)XEMACPS_NWCTRL_HALTTX_MASK|
+                (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+    /* Clear the statistic registers, flush the packets in DPRAM*/
     RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
-			    XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+                XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
     XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
-	/* Clear the interrupt status */
+    /* Clear the interrupt status */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
-	/* Clear the tx status */
+    /* Clear the tx status */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
-									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
-									(u32)XEMACPS_TXSR_TXGO_MASK));
-	/* Clear the rx status */
+                                    (u32)XEMACPS_TXSR_TXCOMPL_MASK|
+                                    (u32)XEMACPS_TXSR_TXGO_MASK));
+    /* Clear the rx status */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
-							    XEMACPS_RXSR_FRAMERX_MASK);
-	/* Clear the tx base address */
+                                XEMACPS_RXSR_FRAMERX_MASK);
+    /* Clear the tx base address */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
-	/* Clear the rx base address */
+    /* Clear the rx base address */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
-	/* Update the network config register with reset value */
+    /* Update the network config register with reset value */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
-	/* Update the hash address registers with reset value */
+    /* Update the hash address registers with reset value */
     XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
     XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h

@@ -25,10 +25,10 @@
 * 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
 * 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
 * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-*					  to 0x1fff. This fixes the CR#744902.
+*                      to 0x1fff. This fixes the CR#744902.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
 * 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+*                      XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
 * 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
 * 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.0  hk   03/18/15 Added support for jumbo frames.
@@ -42,8 +42,8 @@
 *
 ******************************************************************************/
 
-#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
-#define XEMACPS_HW_H		/* by using protection macros */
+#ifndef XEMACPS_HW_H        /* prevent circular inclusions */
+#define XEMACPS_HW_H        /* by using protection macros */
 
 /***************************** Include Files *********************************/
 
@@ -80,8 +80,8 @@ extern "C" {
  *  to specify whether an operation specifies a send or receive channel.
  * @{
  */
-#define XEMACPS_SEND        1U	      /**< send direction */
-#define XEMACPS_RECV        2U	      /**< receive direction */
+#define XEMACPS_SEND        1U          /**< send direction */
+#define XEMACPS_RECV        2U          /**< receive direction */
 /*@}*/
 
 /**  @name MDC clock division
@@ -250,47 +250,47 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 #define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
                                                       Counter */
 #define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
-						      offset, for clearing */
+                              offset, for clearing */
 
 #define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
 #define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
 #define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
-						      adjustment counter */
+                              adjustment counter */
 #define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
-						      increment counter */
+                              increment counter */
 #define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
-						      counter */
+                              counter */
 #define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
-						      nanosecond counter */
+                              nanosecond counter */
 #define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
-						      counter */
+                              counter */
 #define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
-						      nanosecond counter */
+                              nanosecond counter */
 #define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
-						      second counter */
+                              second counter */
 #define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
-						      nanosecond counter */
+                              nanosecond counter */
 #define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
-						      second counter */
+                              second counter */
 #define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
-						      nanosecond counter */
+                              nanosecond counter */
 
 #define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
-						    reg */
-#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
-						    reg */
-#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
-						    reg */
+                            reg */
+#define XEMACPS_TXQ1BASE_OFFSET         0x00000440U /**< TX Q1 Base address
+                            reg */
+#define XEMACPS_RXQ1BASE_OFFSET         0x00000480U /**< RX Q1 Base address
+                            reg */
 #define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
-						    reg */
+                            reg */
 #define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
-						    reg */
+                            reg */
 #define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
-						    reg */
+                            reg */
 #define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
-						    reg */
+                            reg */
 #define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
-						    reg */
+                            reg */
 
 /* Define some bit positions for registers. */
 
@@ -298,7 +298,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
  * @{
  */
 #define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK    0x00040000U /**< Flush a packet from
-						    Rx SRAM */
+                            Rx SRAM */
 #define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
                                                          pause frame */
 #define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
@@ -333,7 +333,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 #define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
                                                         Frames to memory */
 #define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U       /**< shift bits for MDC */
 #define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
 #define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
                                                         received frames */
@@ -382,19 +382,19 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 /** @name DMA control register bit definitions
  * @{
  */
-#define XEMACPS_DMACR_ADDR_WIDTH_64	    0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK	    0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK	    0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK	    0x00FF0000U /**< Mask bit for RX buffer
-												    size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 	    16U	/**< Shift bit for RX buffer
-											    size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK	    0x00000800U /**< enable/disable TX
-													    checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK	    0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK	    0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK	    0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK	    0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_ADDR_WIDTH_64        0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK        0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK        0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK        0x00FF0000U /**< Mask bit for RX buffer
+                                                    size */
+#define XEMACPS_DMACR_RXBUF_SHIFT         16U    /**< Shift bit for RX buffer
+                                                size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK        0x00000800U /**< enable/disable TX
+                                                        checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK        0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK        0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK        0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK        0x0000001FU /**< buffer burst length */
 #define XEMACPS_DMACR_SINGLE_AHB_BURST    0x00000001U /**< single AHB bursts */
 #define XEMACPS_DMACR_INCR4_AHB_BURST    0x00000004U /**< 4 bytes AHB bursts */
 #define XEMACPS_DMACR_INCR8_AHB_BURST    0x00000008U /**< 8 bytes AHB bursts */
@@ -446,8 +446,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 #define XEMACPS_INTQ1SR_TXCOMPL_MASK    0x00000080U /**< Transmit completed OK */
 #define XEMACPS_INTQ1SR_TXERR_MASK    0x00000040U /**< Transmit AMBA Error */
 
-#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
-					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+#define XEMACPS_INTQ1_IXR_ALL_MASK    ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+                     (u32)XEMACPS_INTQ1SR_TXERR_MASK)
 
 /*@}*/
 
@@ -462,27 +462,27 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 #define XEMACPS_IXR_PTPPSRX_MASK    0x00800000U /**< PTP Pdelay_resp RXed */
 #define XEMACPS_IXR_PTPPDRRX_MASK    0x00400000U /**< PTP Pdelay_req RXed */
 
-#define XEMACPS_IXR_PTPSTX_MASK	    0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPSTX_MASK        0x00200000U /**< PTP Sync TXed */
 #define XEMACPS_IXR_PTPDRTX_MASK    0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK	    0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPSRX_MASK        0x00080000U /**< PTP Sync RXed */
 #define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req RXed */
 
-#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U    /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U    /**< Pause time has reached
                                                      zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U    /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U    /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U    /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U    /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U    /**< Transmit err occurred or
                                                      no buffers*/
-#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U    /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U    /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U    /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U    /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U    /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U    /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU    /**< Everything! */
 
 #define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
                                      (u32)XEMACPS_IXR_RETRY_MASK |         \
@@ -498,22 +498,22 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 /** @name PHY Maintenance bit definitions
  * @{
  */
-#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U    /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U    /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U    /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U    /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U    /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU    /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U    /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U    /**< Shift bits for PHREG */
 /*@}*/
 
 /** @name RX watermark bit definitions
  * @{
  */
-#define XEMACPS_RXWM_HIGH_MASK	    0x0000FFFFU	/**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK	    0xFFFF0000U	/**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK    16U	/**< Shift for RXWM low */
+#define XEMACPS_RXWM_HIGH_MASK        0x0000FFFFU    /**< RXWM high mask */
+#define XEMACPS_RXWM_LOW_MASK        0xFFFF0000U    /**< RXWM low mask */
+#define XEMACPS_RXWM_LOW_SHFT_MSK    16U    /**< Shift for RXWM low */
 /*@}*/
 
 /* Transmit buffer descriptor status words offset

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c

@@ -20,16 +20,16 @@
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a wsy  01/10/10 First release
 * 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
-*		      Rx errors. Under heavy Rx traffic, there will be a large
-*		      number of errors related to receive buffer not available.
-*		      Because of a HW bug (SI #692601), under such heavy errors,
-*		      the Rx data path can become unresponsive. To reduce the
-*		      probabilities for hitting this HW bug, the SW writes to
-*		      bit 18 to flush a packet from Rx DPRAM immediately. The
-*		      changes for it are done in the function
-*		      XEmacPs_IntrHandler.
+*              Rx errors. Under heavy Rx traffic, there will be a large
+*              number of errors related to receive buffer not available.
+*              Because of a HW bug (SI #692601), under such heavy errors,
+*              the Rx data path can become unresponsive. To reduce the
+*              probabilities for hitting this HW bug, the SW writes to
+*              bit 18 to flush a packet from Rx DPRAM immediately. The
+*              changes for it are done in the function
+*              XEmacPs_IntrHandler.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
-*		       and 64-bit changes.
+*               and 64-bit changes.
 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
 *                     there is no error. CR# 869403
@@ -77,7 +77,7 @@
  *
  *****************************************************************************/
 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
-		    void *FuncPointer, void *CallBackRef)
+            void *FuncPointer, void *CallBackRef)
 {
     LONG Status;
     Xil_AssertNonvoid(InstancePtr != NULL);
@@ -86,24 +86,24 @@ LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
 
     switch (HandlerType) {
     case XEMACPS_HANDLER_DMASEND:
-	    Status = (LONG)(XST_SUCCESS);
-	    InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-	    InstancePtr->SendRef = CallBackRef;
-	    break;
+        Status = (LONG)(XST_SUCCESS);
+        InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+        InstancePtr->SendRef = CallBackRef;
+        break;
     case XEMACPS_HANDLER_DMARECV:
-	    Status = (LONG)(XST_SUCCESS);
-	    InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
-	    InstancePtr->RecvRef = CallBackRef;
-	    break;
+        Status = (LONG)(XST_SUCCESS);
+        InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+        InstancePtr->RecvRef = CallBackRef;
+        break;
     case XEMACPS_HANDLER_ERROR:
-	    Status = (LONG)(XST_SUCCESS);
-	    InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
-	    InstancePtr->ErrorRef = CallBackRef;
-	    break;
+        Status = (LONG)(XST_SUCCESS);
+        InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+        InstancePtr->ErrorRef = CallBackRef;
+        break;
     default:
-	    Status = (LONG)(XST_INVALID_PARAM);
-	    break;
-	}
+        Status = (LONG)(XST_INVALID_PARAM);
+        break;
+    }
     return Status;
 }
 
@@ -130,113 +130,113 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 
-	/* This ISR will try to handle as many interrupts as it can in a single
-	 * call. However, in most of the places where the user's error handler
+    /* This ISR will try to handle as many interrupts as it can in a single
+     * call. However, in most of the places where the user's error handler
          * is called, this ISR exits because it is expected that the user will
          * reset the device in nearly all instances.
-	 */
+     */
     RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_ISR_OFFSET);
+                   XEMACPS_ISR_OFFSET);
 
-	/* Read Transmit Q1 ISR */
+    /* Read Transmit Q1 ISR */
 
     if (InstancePtr->Version > 2)
-	    RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET);
+        RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_INTQ1_STS_OFFSET);
 
-	/* Clear the interrupt status register */
+    /* Clear the interrupt status register */
     XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
-			   RegISR);
+               RegISR);
 
-	/* Receive complete interrupt */
+    /* Receive complete interrupt */
     if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
-		/* Clear RX status register RX complete indication but preserve
-		 * error bits if there is any */
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_RXSR_OFFSET,
-				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
-				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
-	    InstancePtr->RecvHandler(InstancePtr->RecvRef);
-	}
-
-	/* Transmit Q1 complete interrupt */
+        /* Clear RX status register RX complete indication but preserve
+         * error bits if there is any */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_RXSR_OFFSET,
+                   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+                   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+        InstancePtr->RecvHandler(InstancePtr->RecvRef);
+    }
+
+    /* Transmit Q1 complete interrupt */
     if ((InstancePtr->Version > 2) &&
-			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
-		/* Clear TX status register TX complete indication but preserve
-		 * error bits if there is any */
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET,
-				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET,
-				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
-				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-	    InstancePtr->SendHandler(InstancePtr->SendRef);
-	}
-
-	/* Transmit complete interrupt */
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+        /* Clear TX status register TX complete indication but preserve
+         * error bits if there is any */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_INTQ1_STS_OFFSET,
+                   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_TXSR_OFFSET,
+                   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+                   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+        InstancePtr->SendHandler(InstancePtr->SendRef);
+    }
+
+    /* Transmit complete interrupt */
     if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
-		/* Clear TX status register TX complete indication but preserve
-		 * error bits if there is any */
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET,
-				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
-				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
-	    InstancePtr->SendHandler(InstancePtr->SendRef);
-	}
-
-	/* Receive error conditions interrupt */
+        /* Clear TX status register TX complete indication but preserve
+         * error bits if there is any */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_TXSR_OFFSET,
+                   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+                   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+        InstancePtr->SendHandler(InstancePtr->SendRef);
+    }
+
+    /* Receive error conditions interrupt */
     if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
-		/* Clear RX status register */
-	    RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_RXSR_OFFSET);
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_RXSR_OFFSET, RegSR);
-
-		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
-		 * register to flush a packet out of Rx SRAM upon
-		 * an error for receive buffer not available. */
-	    if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
-		    RegCtrl =
-		    XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					    XEMACPS_NWCTRL_OFFSET);
-		    RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET, RegCtrl);
-		}
-
-	    if(RegSR != 0) {
-		    InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
-					    XEMACPS_RECV, RegSR);
-		}
-	}
+        /* Clear RX status register */
+        RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                      XEMACPS_RXSR_OFFSET);
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_RXSR_OFFSET, RegSR);
+
+        /* Fix for CR # 692702. Write to bit 18 of net_ctrl
+         * register to flush a packet out of Rx SRAM upon
+         * an error for receive buffer not available. */
+        if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+            RegCtrl =
+            XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                        XEMACPS_NWCTRL_OFFSET);
+            RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                    XEMACPS_NWCTRL_OFFSET, RegCtrl);
+        }
+
+        if(RegSR != 0) {
+            InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+                        XEMACPS_RECV, RegSR);
+        }
+    }
 
         /* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
          * will be asserted the same time.
          * Have to distinguish this bit to handle the real error condition.
          */
-	/* Transmit Q1 error conditions interrupt */
+    /* Transmit Q1 error conditions interrupt */
         if ((InstancePtr->Version > 2) &&
-			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
             ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
-			/* Clear Interrupt Q1 status register */
-		    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
-		    InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
-					  RegQ1ISR);
-	   }
-
-	/* Transmit error conditions interrupt */
+            /* Clear Interrupt Q1 status register */
+            XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+            InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+                      RegQ1ISR);
+       }
+
+    /* Transmit error conditions interrupt */
         if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
             (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
-		/* Clear TX status register */
-	    RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
-					  XEMACPS_TXSR_OFFSET);
-	    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-				   XEMACPS_TXSR_OFFSET, RegSR);
-	    InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
-					  RegSR);
-	}
+        /* Clear TX status register */
+        RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                      XEMACPS_TXSR_OFFSET);
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XEMACPS_TXSR_OFFSET, RegSR);
+        InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+                      RegSR);
+    }
 
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c

@@ -60,11 +60,11 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
     u32 i;
 
     for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
-	    if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
-		    CfgPtr = &XEmacPs_ConfigTable[i];
-		    break;
-		}
-	}
+        if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+            CfgPtr = &XEmacPs_ConfigTable[i];
+            break;
+        }
+    }
 
     return (XEmacPs_Config *)(CfgPtr);
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c

@@ -21,8 +21,8 @@
 * 1.00a sv   01/15/10 First Release
 * 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
 *                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-*		      relevant to Zynq device. The interrupts are disabled
-*		      for output pins on all banks during initialization.
+*              relevant to Zynq device. The interrupts are disabled
+*              for output pins on all banks during initialization.
 * 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
@@ -64,48 +64,48 @@ extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    ConfigPtr points to the XGpioPs device configuration structure.
 * @param    EffectiveAddr is the device base address in the virtual memory
-*	    address space. If the address translation is not used then the
-*	    physical address should be passed.
-*	    Unexpected errors may occur if the address mapping is changed
-*	    after this function is invoked.
+*        address space. If the address translation is not used then the
+*        physical address should be passed.
+*        Unexpected errors may occur if the address mapping is changed
+*        after this function is invoked.
 *
 * @return    XST_SUCCESS always.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
-			    u32 EffectiveAddr)
+                u32 EffectiveAddr)
 {
     s32 Status = XST_SUCCESS;
     u8 i;
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(ConfigPtr != NULL);
     Xil_AssertNonvoid(EffectiveAddr != (u32)0);
-	/*
-	 * Set some default values for instance data, don't indicate the device
-	 * is ready to use until everything has been initialized successfully.
-	 */
+    /*
+     * Set some default values for instance data, don't indicate the device
+     * is ready to use until everything has been initialized successfully.
+     */
     InstancePtr->IsReady = 0U;
     InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
     InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
     InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
     InstancePtr->Platform = XGetPlatform_Info();
 
-	/* Initialize the Bank data based on platform */
+    /* Initialize the Bank data based on platform */
     if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
-		/*
-		 *    Max pins in the ZynqMP GPIO device
-		 *    0 - 25,  Bank 0
-		 *    26 - 51, Bank 1
-		 *    52 - 77, Bank 2
-		 *    78 - 109, Bank 3
-		 *    110 - 141, Bank 4
-		 *    142 - 173, Bank 5
-		 */
-	    InstancePtr->MaxPinNum = (u32)174;
-	    InstancePtr->MaxBanks = (u8)6;
-	}
+        /*
+         *    Max pins in the ZynqMP GPIO device
+         *    0 - 25,  Bank 0
+         *    26 - 51, Bank 1
+         *    52 - 77, Bank 2
+         *    78 - 109, Bank 3
+         *    110 - 141, Bank 4
+         *    142 - 173, Bank 5
+         */
+        InstancePtr->MaxPinNum = (u32)174;
+        InstancePtr->MaxBanks = (u8)6;
+    }
         else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
         {
                 if(InstancePtr->PmcGpio == (u32)FALSE)
@@ -130,21 +130,21 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
                 }
         }
         else {
-		/*
-		 *    Max pins in the GPIO device
-		 *    0 - 31,  Bank 0
-		 *    32 - 53, Bank 1
-		 *    54 - 85, Bank 2
-		 *    86 - 117, Bank 3
-		 */
-	    InstancePtr->MaxPinNum = (u32)118;
-	    InstancePtr->MaxBanks = (u8)4;
-	}
-
-	/*
-	 * By default, interrupts are not masked in GPIO. Disable
-	 * interrupts for all pins in all the 4 banks.
-	 */
+        /*
+         *    Max pins in the GPIO device
+         *    0 - 31,  Bank 0
+         *    32 - 53, Bank 1
+         *    54 - 85, Bank 2
+         *    86 - 117, Bank 3
+         */
+        InstancePtr->MaxPinNum = (u32)118;
+        InstancePtr->MaxBanks = (u8)4;
+    }
+
+    /*
+     * By default, interrupts are not masked in GPIO. Disable
+     * interrupts for all pins in all the 4 banks.
+     */
     for (i=(u8)0U;i<InstancePtr->MaxBanks;i++) {
                 if (InstancePtr->Platform == XPLAT_VERSAL){
                         if(InstancePtr->PmcGpio == (u32)FALSE)
@@ -171,13 +171,13 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
                 }
                 else
                 {
-	    XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
-					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+        XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+                      ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+                      XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
                 }
-	}
+    }
 
-	/* Indicate the component is now ready to use. */
+    /* Indicate the component is now ready to use. */
     InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
     return Status;
@@ -190,12 +190,12 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
 * @return    Current value of the Data register.
 *
-* @note	    This function is used for reading the state of all the GPIO pins
-*	    of specified bank.
+* @note        This function is used for reading the state of all the GPIO pins
+*        of specified bank.
 *
 *****************************************************************************/
 u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
@@ -212,8 +212,8 @@ u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
 #endif
 
     return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
-				 XGPIOPS_DATA_RO_OFFSET);
+                 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+                 XGPIOPS_DATA_RO_OFFSET);
 }
 
 /****************************************************************************/
@@ -223,13 +223,13 @@ u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the data has to be read.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*	    See xgpiops.h for the mapping of the pin numbers in the banks.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        See xgpiops.h for the mapping of the pin numbers in the banks.
 *
 * @return    Current value of the Pin (0 or 1).
 *
-* @note	    This function is used for reading the state of the specified
-*	    GPIO pin.
+* @note        This function is used for reading the state of the specified
+*        GPIO pin.
 *
 *****************************************************************************/
 u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
@@ -241,15 +241,15 @@ u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
     XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
     return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
-				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+                 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+                 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
 
 }
 
@@ -260,13 +260,13 @@ u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    Data is the value to be written to the Data register.
 *
 * @return    None.
 *
-* @note	    This function is used for writing to all the GPIO pins of
-*	    the bank. The previous state of the pins is not maintained.
+* @note        This function is used for writing to all the GPIO pins of
+*        the bank. The previous state of the pins is not maintained.
 *
 *****************************************************************************/
 void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
@@ -283,8 +283,8 @@ void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
-			  XGPIOPS_DATA_OFFSET, Data);
+              ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+              XGPIOPS_DATA_OFFSET, Data);
 }
 
 /****************************************************************************/
@@ -294,14 +294,14 @@ void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number to which the Data is to be written.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 * @param    Data is the data to be written to the specified pin (0 or 1).
 *
 * @return    None.
 *
-* @note	    This function does a masked write to the specified pin of
-*	    the specified GPIO bank. The previous state of other pins
-*	    is maintained.
+* @note        This function does a masked write to the specified pin of
+*        the specified GPIO bank. The previous state of other pins
+*        is maintained.
 *
 *****************************************************************************/
 void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
@@ -316,7 +316,7 @@ void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
     Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -324,22 +324,22 @@ void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
 #endif
 
     if (PinNumber > 15U) {
-		/* There are only 16 data bits in bit maskable register. */
-	    PinNumber -= (u8)16;
-	    RegOffset = XGPIOPS_DATA_MSW_OFFSET;
-	} else {
-	    RegOffset = XGPIOPS_DATA_LSW_OFFSET;
-	}
-
-	/*
-	 * Get the 32 bit value to be written to the Mask/Data register where
-	 * the upper 16 bits is the mask and lower 16 bits is the data.
-	 */
+        /* There are only 16 data bits in bit maskable register. */
+        PinNumber -= (u8)16;
+        RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+    } else {
+        RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+    }
+
+    /*
+     * Get the 32 bit value to be written to the Mask/Data register where
+     * the upper 16 bits is the mask and lower 16 bits is the data.
+     */
     DataVar &= (u32)0x01;
     Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
-			  RegOffset, Value);
+              ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+              RegOffset, Value);
 
 }
 
@@ -352,16 +352,16 @@ void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    Direction is the 32 bit mask of the Pin direction to be set for
-*	    all the pins in the Bank. Bits with 0 are set to Input mode,
-*	    bits with 1 are    set to Output Mode.
+*        all the pins in the Bank. Bits with 0 are set to Input mode,
+*        bits with 1 are    set to Output Mode.
 *
 * @return    None.
 *
-* @note	    This function is used for setting the direction of all the pins
-*	    in the specified bank. The previous state of the pins is
-*	    not maintained.
+* @note        This function is used for setting the direction of all the pins
+*        in the specified bank. The previous state of the pins is
+*        not maintained.
 *
 *****************************************************************************/
 void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
@@ -378,8 +378,8 @@ void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_DIRM_OFFSET, Direction);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_DIRM_OFFSET, Direction);
 }
 
 /****************************************************************************/
@@ -389,9 +389,9 @@ void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number to which the Data is to be written.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 * @param    Direction is the direction to be set for the specified pin.
-*	    Valid values are 0 for Input Direction, 1 for Output Direction.
+*        Valid values are 0 for Input Direction, 1 for Output Direction.
 *
 * @return    None.
 *
@@ -407,25 +407,25 @@ void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
     Xil_AssertVoid(Direction <= (u32)1);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
     XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
     DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				      XGPIOPS_DIRM_OFFSET);
+                      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                      XGPIOPS_DIRM_OFFSET);
 
     if (Direction!=(u32)0) { /*  Output Direction */
-	    DirModeReg |= ((u32)1 << (u32)PinNumber);
-	} else { /* Input Direction */
-	    DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
-	}
+        DirModeReg |= ((u32)1 << (u32)PinNumber);
+    } else { /* Input Direction */
+        DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+    }
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+             ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+             XGPIOPS_DIRM_OFFSET, DirModeReg);
 }
 
 /****************************************************************************/
@@ -435,12 +435,12 @@ void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
 * @return    Returns a 32 bit mask of the Direction register. Bits with 0 are
-* 	    in Input mode, bits with 1 are in Output Mode.
+*         in Input mode, bits with 1 are in Output Mode.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
@@ -457,8 +457,8 @@ u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
 #endif
 
     return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			    XGPIOPS_DIRM_OFFSET);
+                ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                XGPIOPS_DIRM_OFFSET);
 }
 
 /****************************************************************************/
@@ -468,14 +468,14 @@ u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the Direction is to be
-*	    retrieved.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        retrieved.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return    Direction of the specified pin.
-*		- 0 for Input Direction
-*		- 1 for Output Direction
+*        - 0 for Input Direction
+*        - 1 for Output Direction
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
@@ -487,7 +487,7 @@ u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -495,8 +495,8 @@ u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
 #endif
 
     return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+                 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
 }
 
 /****************************************************************************/
@@ -506,16 +506,16 @@ u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    OpEnable is the 32 bit mask of the Output Enables to be set for
-*	    all the pins in the Bank. The Output Enable of bits with 0 are
-*	    disabled, the Output Enable of bits with 1 are enabled.
+*        all the pins in the Bank. The Output Enable of bits with 0 are
+*        disabled, the Output Enable of bits with 1 are enabled.
 *
 * @return    None.
 *
-* @note	    This function is used for setting the Output Enables of all the
-*	    pins in the specified bank. The previous state of the Output
-*	    Enables is not maintained.
+* @note        This function is used for setting the Output Enables of all the
+*        pins in the specified bank. The previous state of the Output
+*        Enables is not maintained.
 *
 *****************************************************************************/
 void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
@@ -532,8 +532,8 @@ void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_OUTEN_OFFSET, OpEnable);
 }
 
 /****************************************************************************/
@@ -543,15 +543,15 @@ void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number to which the Data is to be written.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 * @param    OpEnable specifies whether the Output Enable for the specified
-*	    pin should be enabled.
-*	    Valid values are 0 for Disabling Output Enable,
-*	    1 for Enabling Output Enable.
+*        pin should be enabled.
+*        Valid values are 0 for Disabling Output Enable,
+*        1 for Enabling Output Enable.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
@@ -565,7 +565,7 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
     Xil_AssertVoid(OpEnable <= (u32)1);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -573,18 +573,18 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
 #endif
 
     OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				       XGPIOPS_OUTEN_OFFSET);
+                       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                       XGPIOPS_OUTEN_OFFSET);
 
     if (OpEnable != (u32)0) { /*  Enable Output Enable */
-	    OpEnableReg |= ((u32)1 << (u32)PinNumber);
-	} else { /* Disable Output Enable */
-	    OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
-	}
+        OpEnableReg |= ((u32)1 << (u32)PinNumber);
+    } else { /* Disable Output Enable */
+        OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+    }
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_OUTEN_OFFSET, OpEnableReg);
 }
 /****************************************************************************/
 /**
@@ -593,13 +593,13 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
 * @return    Returns a a 32 bit mask of the Output Enable register.
-*	    Bits with 0 are in Disabled state, bits with 1 are in
-*	    Enabled State.
+*        Bits with 0 are in Disabled state, bits with 1 are in
+*        Enabled State.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
@@ -616,8 +616,8 @@ u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
 #endif
 
     return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			    XGPIOPS_OUTEN_OFFSET);
+                ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                XGPIOPS_OUTEN_OFFSET);
 }
 
 /****************************************************************************/
@@ -627,14 +627,14 @@ u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the Output Enable status is to
-*	    be retrieved.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        be retrieved.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return    Output Enable of the specified pin.
-*		- 0 if Output Enable is disabled for this pin
-*		- 1 if Output Enable is enabled for this pin
+*        - 0 if Output Enable is disabled for this pin
+*        - 1 if Output Enable is enabled for this pin
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
@@ -646,7 +646,7 @@ u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -654,8 +654,8 @@ u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 #endif
 
     return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+                 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
 }
 
 /****************************************************************************/
@@ -666,12 +666,12 @@ u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    PinNumber is the Pin number in the GPIO device.
 * @param    BankNumber returns the Bank in which this GPIO pin is present.
-*	    Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*        Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
 * @param    PinNumberInBank returns the Pin Number within the Bank.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 #ifdef versal
@@ -687,26 +687,26 @@ void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
     u32 Platform = XGetPlatform_Info();
 
     if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
-		/*
-		 * This structure defines the mapping of the pin numbers to the banks when
-		 * the driver APIs are used for working on the individual pins.
-		 */
-
-	    XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
-	    XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
-	    XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
-	    XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
-	    XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
-	    XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
-
-		*BankNumber = 0U;
-	    while (*BankNumber < XGPIOPS_SIX) {
-		    if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
-			    break;
-			}
-			(*BankNumber)++;
-		}
-	}
+        /*
+         * This structure defines the mapping of the pin numbers to the banks when
+         * the driver APIs are used for working on the individual pins.
+         */
+
+        XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+        XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+        XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+        XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+        XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+        XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+        *BankNumber = 0U;
+        while (*BankNumber < XGPIOPS_SIX) {
+            if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+                break;
+            }
+            (*BankNumber)++;
+        }
+    }
 #ifdef versal
         else if(Platform == XPLAT_VERSAL)
         {
@@ -760,22 +760,22 @@ void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
         }
 #endif
         else {
-	    XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
-	    XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
-	    XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
-	    XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
-
-		*BankNumber = 0U;
-	    while (*BankNumber < XGPIOPS_FOUR) {
-		    if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
-			    break;
-			}
-			(*BankNumber)++;
-		}
-	}
+        XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+        XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+        XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+        XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+        *BankNumber = 0U;
+        while (*BankNumber < XGPIOPS_FOUR) {
+            if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+                break;
+            }
+            (*BankNumber)++;
+        }
+    }
     if (*BankNumber == (u8)0) {
-		*PinNumberInBank = PinNumber;
-	}
+        *PinNumberInBank = PinNumber;
+    }
 
 #ifdef versal
         else if(Platform == XPLAT_VERSAL)
@@ -801,8 +801,8 @@ void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
 #endif
 
         else {
-		*PinNumberInBank = (u8)((u32)PinNumber %
-					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+        *PinNumberInBank = (u8)((u32)PinNumber %
+                    (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
         }
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h

@@ -15,10 +15,10 @@
 * Controller.
 *
 * The GPIO Controller supports the following features:
-*	- 4 banks
-*	- Masked writes (There are no masked reads)
-*	- Bypass mode
-*	- Configurable Interrupts (Level/Edge)
+*    - 4 banks
+*    - Masked writes (There are no masked reads)
+*    - Bypass mode
+*    - Configurable Interrupts (Level/Edge)
 *
 * This driver is intended to be RTOS and processor independent. Any needs for
 * dynamic memory management, threads or thread mutual exclusion, virtual
@@ -63,12 +63,12 @@
 * 1.00a sv   01/15/10 First Release
 * 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
 *                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-*		      relevant to Zynq device.The interrupts are disabled
-*		      for output pins on all banks during initialization.
+*              relevant to Zynq device.The interrupts are disabled
+*              for output pins on all banks during initialization.
 * 1.02a hk   08/22/13 Added low level reset API
 * 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2    sk	 10/13/14 Used Pin number in Bank instead of pin number
-* 					  passed to APIs. CR# 822636
+* 2.2    sk     10/13/14 Used Pin number in Bank instead of pin number
+*                       passed to APIs. CR# 822636
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 *       ms   03/17/17 Added readme.txt file in examples folder for doxygen
@@ -96,8 +96,8 @@
 * </pre>
 *
 ******************************************************************************/
-#ifndef XGPIOPS_H		/* prevent circular inclusions */
-#define XGPIOPS_H		/* by using protection macros */
+#ifndef XGPIOPS_H        /* prevent circular inclusions */
+#define XGPIOPS_H        /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -123,37 +123,37 @@ extern "C" {
 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW    0x04U  /**< Interrupt on low level */
 /*@}*/
 
-#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0		    0x00U  /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1		    0x01U  /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2		    0x02U  /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3		    0x03U  /**< GPIO Bank 3 */
+#define XGPIOPS_BANK_MAX_PINS        (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0            0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1            0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2            0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3            0x03U  /**< GPIO Bank 3 */
 
 #ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4		    0x04U  /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5		    0x05U  /**< GPIO Bank 5 */
+#define XGPIOPS_BANK4            0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5            0x05U  /**< GPIO Bank 5 */
 #endif
 
-#define XGPIOPS_MAX_BANKS_ZYNQMP	    0x06U  /**< Max banks in a
-										*    Zynq Ultrascale+ MP GPIO device
-										*/
-#define XGPIOPS_MAX_BANKS	    0x04U  /**< Max banks in a Zynq GPIO device */
+#define XGPIOPS_MAX_BANKS_ZYNQMP        0x06U  /**< Max banks in a
+                                        *    Zynq Ultrascale+ MP GPIO device
+                                        */
+#define XGPIOPS_MAX_BANKS        0x04U  /**< Max banks in a Zynq GPIO device */
 
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
-						  *    Zynq Ultrascale+ MP GPIO device
-					      * 0 - 25,  Bank 0
-					      * 26 - 51, Bank 1
-					      *    52 - 77, Bank 2
-					      *    78 - 109, Bank 3
-					      *    110 - 141, Bank 4
-					      *    142 - 173, Bank 5
-					      */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
-					      * 0 - 31,  Bank 0
-					      * 32 - 53, Bank 1
-					      *    54 - 85, Bank 2
-					      *    86 - 117, Bank 3
-					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP    (u32)174 /**< Max pins in the
+                          *    Zynq Ultrascale+ MP GPIO device
+                          * 0 - 25,  Bank 0
+                          * 26 - 51, Bank 1
+                          *    52 - 77, Bank 2
+                          *    78 - 109, Bank 3
+                          *    110 - 141, Bank 4
+                          *    142 - 173, Bank 5
+                          */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM    (u32)118 /**< Max pins in the Zynq GPIO device
+                          * 0 - 31,  Bank 0
+                          * 32 - 53, Bank 1
+                          *    54 - 85, Bank 2
+                          *    86 - 117, Bank 3
+                          */
 
 /**************************** Type Definitions *******************************/
 
@@ -166,10 +166,10 @@ extern "C" {
  * processing should be performed.
  *
  * @param    CallBackRef is a callback reference passed in by the upper layer
- *	    when setting the callback functions for a GPIO bank. It is
- *	    passed back to the upper layer when the callback is invoked. Its
- *	    type is not important to the driver component, so it is a void
- *	    pointer.
+ *        when setting the callback functions for a GPIO bank. It is
+ *        passed back to the upper layer when the callback is invoked. Its
+ *        type is not important to the driver component, so it is a void
+ *        pointer.
  * @param    Bank is the bank for which the interrupt status has changed.
  * @param    Status is the Interrupt status of the GPIO bank.
  *
@@ -180,8 +180,8 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
  * This typedef contains configuration information for a device.
  */
 typedef struct {
-    u16 DeviceId;		/**< Unique ID of device */
-    u32 BaseAddr;		/**< Register base address */
+    u16 DeviceId;        /**< Unique ID of device */
+    u32 BaseAddr;        /**< Register base address */
 } XGpioPs_Config;
 
 /**
@@ -190,13 +190,13 @@ typedef struct {
  * to a variable of this type is then passed to the driver API functions.
  */
 typedef struct {
-    XGpioPs_Config GpioConfig;	/**< Device configuration */
-    u32 IsReady;			/**< Device is initialized and ready */
-    XGpioPs_Handler Handler;	/**< Status handlers for all banks */
-    void *CallBackRef; 		/**< Callback ref for bank handlers */
-    u32 Platform;			/**< Platform data */
-    u32 MaxPinNum;			/**< Max pins in the GPIO device */
-    u8 MaxBanks;			/**< Max banks in a GPIO device */
+    XGpioPs_Config GpioConfig;    /**< Device configuration */
+    u32 IsReady;            /**< Device is initialized and ready */
+    XGpioPs_Handler Handler;    /**< Status handlers for all banks */
+    void *CallBackRef;         /**< Callback ref for bank handlers */
+    u32 Platform;            /**< Platform data */
+    u32 MaxPinNum;            /**< Max pins in the GPIO device */
+    u8 MaxBanks;            /**< Max banks in a GPIO device */
         u32 PmcGpio;                    /**< Flag for accessing PS GPIO for versal*/
 } XGpioPs;
 
@@ -206,7 +206,7 @@ typedef struct {
 
 /* Functions in xgpiops.c */
 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
-			   u32 EffectiveAddr);
+               u32 EffectiveAddr);
 
 /* Bank APIs in xgpiops.c */
 u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
@@ -240,11 +240,11 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
 u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
 void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
-			  u32 IntrPolarity, u32 IntrOnAny);
+              u32 IntrPolarity, u32 IntrOnAny);
 void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
-			  u32 *IntrPolarity, u32 *IntrOnAny);
+              u32 *IntrPolarity, u32 *IntrOnAny);
 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
-			     XGpioPs_Handler FuncPointer);
+                 XGpioPs_Handler FuncPointer);
 void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
 
 /* Pin APIs in xgpiops_intr.c */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c

@@ -22,10 +22,10 @@
 
 XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
 {
-	{
-	    XPAR_PSU_GPIO_0_DEVICE_ID,
-	    XPAR_PSU_GPIO_0_BASEADDR
-	}
+    {
+        XPAR_PSU_GPIO_0_DEVICE_ID,
+        XPAR_PSU_GPIO_0_BASEADDR
+    }
 };
 
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c

@@ -56,7 +56,7 @@
 *
 * @return    None
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 void XGpioPs_ResetHw(u32 BaseAddress)

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h

@@ -28,8 +28,8 @@
 * </pre>
 *
 ******************************************************************************/
-#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
-#define XGPIOPS_HW_H		/* by using protection macros */
+#ifndef XGPIOPS_HW_H        /* prevent circular inclusions */
+#define XGPIOPS_HW_H        /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -48,17 +48,17 @@ extern "C" {
  */
 #define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
 #define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+#define XGPIOPS_DATA_OFFSET     0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET     0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET     0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET     0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET     0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET     0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET     0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET     0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET     0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET     0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET     0x00000224U  /* Interrupt On Any Register, RW */
 /* @} */
 
 /** @name Register offsets for each Bank.
@@ -70,7 +70,7 @@ extern "C" {
 /* @} */
 
 /* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+#define XGPIOPS_BYPM_MASK_OFFSET    (u32)0x40
 
 /** @name Interrupt type reset values for each bank
  *  @{
@@ -111,11 +111,11 @@ extern "C" {
 *
 * @return    The 32-bit value of the register
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
-	    Xil_In32((BaseAddr) + (u32)(RegOffset))
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)        \
+        Xil_In32((BaseAddr) + (u32)(RegOffset))
 
 /****************************************************************************/
 /**
@@ -128,11 +128,11 @@ extern "C" {
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
-	    Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)    \
+        Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
 
 /************************** Function Prototypes ******************************/
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c

@@ -18,8 +18,8 @@
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a sv   01/18/10 First Release
-* 2.2    sk	 10/13/14 Used Pin number in Bank instead of pin number
-* 					  passed to API's. CR# 822636
+* 2.2    sk     10/13/14 Used Pin number in Bank instead of pin number
+*                       passed to API's. CR# 822636
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.1    kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
 * 3.1   aru  07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
@@ -63,14 +63,14 @@ void StubHandler(const void *CallBackRef, u32 Bank, u32 Status);
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    Mask is the bit mask of the pins for which interrupts are to
-*	    be enabled. Bit positions of 1 will be enabled. Bit positions
-*	    of 0 will keep the previous setting.
+*        be enabled. Bit positions of 1 will be enabled. Bit positions
+*        of 0 will keep the previous setting.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
@@ -87,8 +87,8 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTEN_OFFSET, Mask);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTEN_OFFSET, Mask);
 }
 
 /****************************************************************************/
@@ -98,11 +98,11 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the interrupt is to be enabled.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
@@ -115,7 +115,7 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -124,8 +124,8 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 
     IntrReg = ((u32)1 << (u32)PinNumber);
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTEN_OFFSET, IntrReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTEN_OFFSET, IntrReg);
 }
 
 /****************************************************************************/
@@ -136,14 +136,14 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    Mask is the bit mask of the pins for which interrupts are
-*	    to be disabled. Bit positions of 1 will be disabled. Bit
-*	    positions of 0 will keep the previous setting.
+*        to be disabled. Bit positions of 1 will be disabled. Bit
+*        positions of 0 will keep the previous setting.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
@@ -160,8 +160,8 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTDIS_OFFSET, Mask);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTDIS_OFFSET, Mask);
 }
 
 /****************************************************************************/
@@ -171,11 +171,11 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the interrupt is to be disabled.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
@@ -188,7 +188,7 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -197,8 +197,8 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
 
     IntrReg = ((u32)1 << (u32)PinNumber);
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTDIS_OFFSET, IntrReg);
 }
 
 /****************************************************************************/
@@ -208,14 +208,14 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
 * @return    Enabled interrupt(s) in a 32-bit format. Bit positions with 1
-*	    indicate that the interrupt for that pin is enabled, bit
-*	    positions with 0 indicate that the interrupt for that pin is
-*	    disabled.
+*        indicate that the interrupt for that pin is enabled, bit
+*        positions with 0 indicate that the interrupt for that pin is
+*        disabled.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
@@ -234,8 +234,8 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
 #endif
 
     IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				    XGPIOPS_INTMASK_OFFSET);
+                    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                    XGPIOPS_INTMASK_OFFSET);
     return (~IntrMask);
 }
 
@@ -246,14 +246,14 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the interrupt enable status
-*	    is to be known.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        is to be known.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return
-*		- TRUE if the interrupt is enabled.
-*		- FALSE if the interrupt is disabled.
+*        - TRUE if the interrupt is enabled.
+*        - FALSE if the interrupt is disabled.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
@@ -266,7 +266,7 @@ u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -274,8 +274,8 @@ u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
 #endif
 
     IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				    XGPIOPS_INTMASK_OFFSET);
+                    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                    XGPIOPS_INTMASK_OFFSET);
 
     return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
 }
@@ -287,11 +287,11 @@ u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 *
 * @return    The value read from Interrupt Status Register.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
@@ -308,8 +308,8 @@ u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
 #endif
 
     return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			    XGPIOPS_INTSTS_OFFSET);
+                ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                XGPIOPS_INTSTS_OFFSET);
 }
 
 /****************************************************************************/
@@ -319,14 +319,14 @@ u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the interrupt enable status
-*	    is to be known.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        is to be known.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return
-*		- TRUE if the interrupt has occurred.
-*		- FALSE if the interrupt has not occurred.
+*        - TRUE if the interrupt has occurred.
+*        - FALSE if the interrupt has not occurred.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
@@ -339,7 +339,7 @@ u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -347,8 +347,8 @@ u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
 #endif
 
     IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				   XGPIOPS_INTSTS_OFFSET);
+                   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                   XGPIOPS_INTSTS_OFFSET);
 
     return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
 }
@@ -362,12 +362,12 @@ u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    Mask is the mask of the interrupts to be cleared. Bit positions
-*	    of 1 will be cleared. Bit positions of 0 will not change the
-*	    previous interrupt status.
+*        of 1 will be cleared. Bit positions of 0 will not change the
+*        previous interrupt status.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
@@ -383,10 +383,10 @@ void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
         }
 #endif
 
-	/* Clear the currently pending interrupts. */
+    /* Clear the currently pending interrupts. */
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTSTS_OFFSET, Mask);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTSTS_OFFSET, Mask);
 }
 
 /****************************************************************************/
@@ -397,9 +397,9 @@ void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    Pin is the pin number for which the interrupt status is to be
-*	    cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
@@ -412,22 +412,22 @@ void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
     XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
 #endif
 
-	/* Clear the specified pending interrupts. */
+    /* Clear the specified pending interrupts. */
     IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				   XGPIOPS_INTSTS_OFFSET);
+                   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                   XGPIOPS_INTSTS_OFFSET);
 
     IntrReg &= ((u32)1 << PinNumber);
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTSTS_OFFSET, IntrReg);
 }
 
 /****************************************************************************/
@@ -438,28 +438,28 @@ void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to an XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    IntrType is the 32 bit mask of the interrupt type.
-*	    0 means Level Sensitive and 1 means Edge Sensitive.
+*        0 means Level Sensitive and 1 means Edge Sensitive.
 * @param    IntrPolarity is the 32 bit mask of the interrupt polarity.
-*	    0 means Active Low or Falling Edge and 1 means Active High or
-*	    Rising Edge.
+*        0 means Active Low or Falling Edge and 1 means Active High or
+*        Rising Edge.
 * @param    IntrOnAny is the 32 bit mask of the interrupt trigger for
-*	    edge triggered interrupts. 0 means trigger on single edge using
-*	    the configured interrupt polarity and 1 means  trigger on both
-*	    edges.
+*        edge triggered interrupts. 0 means trigger on single edge using
+*        the configured interrupt polarity and 1 means  trigger on both
+*        edges.
 *
 * @return    None.
 *
-* @note	    This function is used for setting the interrupt related
-*	    properties of all the pins in the specified bank. The previous
-*	    state of the pins is not maintained.
-*	    To change the Interrupt properties of a single GPIO pin, use the
-*	    function XGpioPs_SetPinIntrType().
+* @note        This function is used for setting the interrupt related
+*        properties of all the pins in the specified bank. The previous
+*        state of the pins is not maintained.
+*        To change the Interrupt properties of a single GPIO pin, use the
+*        function XGpioPs_SetPinIntrType().
 *
 *****************************************************************************/
 void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
-			  u32 IntrPolarity, u32 IntrOnAny)
+              u32 IntrPolarity, u32 IntrOnAny)
 {
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -473,16 +473,16 @@ void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
 #endif
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTTYPE_OFFSET, IntrType);
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTPOL_OFFSET, IntrPolarity);
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTANY_OFFSET, IntrOnAny);
 }
 
 /****************************************************************************/
@@ -493,24 +493,24 @@ void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
 *
 * @param    InstancePtr is a pointer to an XGpioPs instance.
 * @param    Bank is the bank number of the GPIO to operate on.
-*	    Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*        Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
 * @param    IntrType returns the 32 bit mask of the interrupt type.
-*	    0 means Level Sensitive and 1 means Edge Sensitive.
+*        0 means Level Sensitive and 1 means Edge Sensitive.
 * @param    IntrPolarity returns the 32 bit mask of the interrupt
-*	    polarity. 0 means Active Low or Falling Edge and 1 means
-*	    Active High or Rising Edge.
+*        polarity. 0 means Active Low or Falling Edge and 1 means
+*        Active High or Rising Edge.
 * @param    IntrOnAny returns the 32 bit mask of the interrupt trigger for
-*	    edge triggered interrupts. 0 means trigger on single edge using
-*	    the configured interrupt polarity and 1 means trigger on both
-*	    edges.
+*        edge triggered interrupts. 0 means trigger on single edge using
+*        the configured interrupt polarity and 1 means trigger on both
+*        edges.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
-			  u32 *IntrPolarity, u32 *IntrOnAny)
+              u32 *IntrPolarity, u32 *IntrOnAny)
 
 {
     Xil_AssertVoid(InstancePtr != NULL);
@@ -524,17 +524,17 @@ void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
         }
 #endif
 
-	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				     XGPIOPS_INTTYPE_OFFSET);
+    *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                     XGPIOPS_INTTYPE_OFFSET);
 
-	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-					 XGPIOPS_INTPOL_OFFSET);
+    *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                     XGPIOPS_INTPOL_OFFSET);
 
-	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				      XGPIOPS_INTANY_OFFSET);
+    *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                      XGPIOPS_INTANY_OFFSET);
 }
 
 /****************************************************************************/
@@ -544,13 +544,13 @@ void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
 *
 * @param    InstancePtr is a pointer to an XGpioPs instance.
 * @param    Pin is the pin number whose IRQ type is to be set.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 * @param    IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
-*	    defined in xgpiops.h to specify the IRQ type.
+*        defined in xgpiops.h to specify the IRQ type.
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 *****************************************************************************/
 void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
@@ -566,7 +566,7 @@ void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
     Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
     Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -574,56 +574,56 @@ void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
 #endif
 
     IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				       XGPIOPS_INTTYPE_OFFSET);
+                       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                       XGPIOPS_INTTYPE_OFFSET);
 
     IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				      XGPIOPS_INTPOL_OFFSET);
+                      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                      XGPIOPS_INTPOL_OFFSET);
 
     IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				    XGPIOPS_INTANY_OFFSET);
+                    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                    XGPIOPS_INTANY_OFFSET);
 
     switch (IrqType) {
-	    case XGPIOPS_IRQ_TYPE_EDGE_RISING:
-		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-		    IntrPolReg |= ((u32)1 << (u32)PinNumber);
-		    IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
-		    break;
-	    case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
-		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-		    IntrPolReg &= ~((u32)1 << (u32)PinNumber);
-		    IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
-		    break;
-	    case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
-		    IntrTypeReg |= ((u32)1 << (u32)PinNumber);
-		    IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
-		    break;
-	    case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
-		    IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
-		    IntrPolReg |= ((u32)1 << (u32)PinNumber);
-		    break;
-	    case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
-		    IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
-		    IntrPolReg &= ~((u32)1 << (u32)PinNumber);
-		    break;
-	    default:
-			/**< Default statement is added for MISRA C compliance. */
-		    break;
-	}
+        case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+            IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+            IntrPolReg |= ((u32)1 << (u32)PinNumber);
+            IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+            break;
+        case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+            IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+            IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+            IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+            break;
+        case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+            IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+            IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+            break;
+        case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+            IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+            IntrPolReg |= ((u32)1 << (u32)PinNumber);
+            break;
+        case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+            IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+            IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+            break;
+        default:
+            /**< Default statement is added for MISRA C compliance. */
+            break;
+    }
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTPOL_OFFSET, IntrPolReg);
 
     XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
-			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+              ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+              XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
 }
 
 /****************************************************************************/
@@ -633,12 +633,12 @@ void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
 *
 * @param    InstancePtr is a pointer to an XGpioPs instance.
 * @param    Pin is the pin number whose IRQ type is to be obtained.
-*	    Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*        Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
 *
 * @return    None.
 *
-* @note	    Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
-*	    returned by this function.
+* @note        Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*        returned by this function.
 *
 *****************************************************************************/
 u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
@@ -654,7 +654,7 @@ u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
     Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
 
-	/* Get the Bank number and Pin number within the bank. */
+    /* Get the Bank number and Pin number within the bank. */
 #ifdef versal
     XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
 #else
@@ -662,39 +662,39 @@ u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
 #endif
 
     IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+                    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
 
     if (IntrType == ((u32)1 << PinNumber)) {
 
-	    IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+        IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
 
-	    IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+        IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
 
 
-	    if (IntrOnAny == ((u32)1 << PinNumber)) {
-		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
-		} else if (IntrPol == ((u32)1 << PinNumber)) {
-		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
-		} else {
-		    IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
-		}
-	} else {
+        if (IntrOnAny == ((u32)1 << PinNumber)) {
+            IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+        } else if (IntrPol == ((u32)1 << PinNumber)) {
+            IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+        } else {
+            IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+        }
+    } else {
 
-	    IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
-				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
-				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+        IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+                   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+                   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
 
-	    if (IntrPol == ((u32)1 << PinNumber)) {
-		    IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
-		} else {
-		    IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
-		}
-	}
+        if (IntrPol == ((u32)1 << PinNumber)) {
+            IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+        } else {
+            IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+        }
+    }
 
     return IrqType;
 }
@@ -707,19 +707,19 @@ u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
 *
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 * @param    CallBackRef is the upper layer callback reference passed back
-*	    when the callback function is invoked.
+*        when the callback function is invoked.
 * @param    FuncPointer is the pointer to the callback function.
 *
 *
 * @return    None.
 *
-* @note	    The handler is called within interrupt context, so it should do
-*	    its work quickly and queue potentially time-consuming work to a
-*	    task-level thread.
+* @note        The handler is called within interrupt context, so it should do
+*        its work quickly and queue potentially time-consuming work to a
+*        task-level thread.
 *
 ******************************************************************************/
 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
-				 XGpioPs_Handler FuncPointer)
+                 XGpioPs_Handler FuncPointer)
 {
     Xil_AssertVoid(InstancePtr != NULL);
     Xil_AssertVoid(FuncPointer != NULL);
@@ -742,8 +742,8 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
 *
 * @return    None.
 *
-* @note	    This function does not save and restore the processor context
-*	    such that the user must provide this processing.
+* @note        This function does not save and restore the processor context
+*        such that the user must provide this processing.
 *
 ******************************************************************************/
 void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
@@ -757,26 +757,26 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
 
     for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
 #ifdef versal
-	    if(InstancePtr->PmcGpio == TRUE) {
-		    if(Bank == XGPIOPS_TWO) {
-			    continue;
-			}
-		} else {
-		    if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
-			    continue;
-			}
-		}
+        if(InstancePtr->PmcGpio == TRUE) {
+            if(Bank == XGPIOPS_TWO) {
+                continue;
+            }
+        } else {
+            if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
+                continue;
+            }
+        }
 #endif
-	    IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
-	    IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
-	    if ((IntrStatus & IntrEnabled) != (u32)0) {
-		    XGpioPs_IntrClear(InstancePtr, Bank,
-					(IntrStatus & IntrEnabled));
-		    InstancePtr->Handler(InstancePtr->
-				    CallBackRef, Bank,
-					(IntrStatus & IntrEnabled));
-		}
-	}
+        IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+        IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
+        if ((IntrStatus & IntrEnabled) != (u32)0) {
+            XGpioPs_IntrClear(InstancePtr, Bank,
+                    (IntrStatus & IntrEnabled));
+            InstancePtr->Handler(InstancePtr->
+                    CallBackRef, Bank,
+                    (IntrStatus & IntrEnabled));
+        }
+    }
 }
 
 /*****************************************************************************/
@@ -791,14 +791,14 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
 *
 * @return    None.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 void StubHandler(const void *CallBackRef, u32 Bank, u32 Status)
 {
-	(void) CallBackRef;
-	(void) Bank;
-	(void) Status;
+    (void) CallBackRef;
+    (void) Bank;
+    (void) Status;
 
     Xil_AssertVoidAlways();
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c

@@ -55,8 +55,8 @@
 * @param    InstancePtr is a pointer to the XGpioPs instance.
 *
 * @return
-*		- XST_SUCCESS if the self-test passed.
-* 		- XST_FAILURE otherwise.
+*        - XST_SUCCESS if the self-test passed.
+*         - XST_FAILURE otherwise.
 *
 *
 ******************************************************************************/
@@ -75,35 +75,35 @@ s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/* Disable the Interrupts for Bank 0 . */
+    /* Disable the Interrupts for Bank 0 . */
     IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
     XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
 
-	/*
-	 * Get the Current Interrupt properties for Bank 0.
-	 * Set them to a known value, read it back and compare.
-	 */
+    /*
+     * Get the Current Interrupt properties for Bank 0.
+     * Set them to a known value, read it back and compare.
+     */
     XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
-			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+                 &CurrentIntrPolarity, &CurrentIntrOnAny);
 
     XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
-			     IntrTestValue, IntrTestValue);
+                 IntrTestValue, IntrTestValue);
 
     XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
-			     &IntrPolarity, &IntrOnAny);
+                 &IntrPolarity, &IntrOnAny);
 
     if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
-	    (IntrOnAny != IntrTestValue)) {
+        (IntrOnAny != IntrTestValue)) {
 
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
-	/*
-	 * Restore the contents of all the interrupt registers modified in this
-	 * test.
-	 */
+    /*
+     * Restore the contents of all the interrupt registers modified in this
+     * test.
+     */
     XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
-			     CurrentIntrPolarity, CurrentIntrOnAny);
+                 CurrentIntrPolarity, CurrentIntrOnAny);
 
     XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c

@@ -13,7 +13,7 @@
 * This file contains the implementation of the XGpioPs driver's static
 * initialization functionality.
 *
-* @note	    None.
+* @note        None.
 *
 * <pre>
 *
@@ -53,9 +53,9 @@ extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
 * @param    DeviceId is the unique device ID of the device being looked up.
 *
 * @return    A pointer to the configuration table entry corresponding to the
-*	    given device ID, or NULL if no match is found.
+*        given device ID, or NULL if no match is found.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
@@ -64,11 +64,11 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
     u32 Index;
 
     for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
-	    if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
-		    CfgPtr = &XGpioPs_ConfigTable[Index];
-		    break;
-		}
-	}
+        if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+            CfgPtr = &XGpioPs_ConfigTable[Index];
+            break;
+        }
+    }
 
     return (XGpioPs_Config *)CfgPtr;
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c

@@ -24,14 +24,14 @@
 * 2.2   hk     07/28/14 Make changes to enable use of data cache.
 * 2.3   sk     09/23/14 Send command for relative card address
 *                       when re-initialization is done.CR# 819614.
-*					    Use XSdPs_Change_ClkFreq API whenever changing
-*					    clock.CR# 816586.
-* 2.4    sk	   12/04/14 Added support for micro SD without
-* 					    WP/CD. CR# 810655.
-*					    Checked for DAT Inhibit mask instead of CMD
-* 					    Inhibit mask in Cmd Transfer API.
-*					    Added Support for SD Card v1.0
-* 2.5     sg	   07/09/15 Added SD 3.0 features
+*                        Use XSdPs_Change_ClkFreq API whenever changing
+*                        clock.CR# 816586.
+* 2.4    sk       12/04/14 Added support for micro SD without
+*                         WP/CD. CR# 810655.
+*                        Checked for DAT Inhibit mask instead of CMD
+*                         Inhibit mask in Cmd Transfer API.
+*                        Added Support for SD Card v1.0
+* 2.5     sg       07/09/15 Added SD 3.0 features
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
 * 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -104,32 +104,32 @@
 *
 * @param    InstancePtr is a pointer to the XSdPs instance.
 * @param    ConfigPtr is a reference to a structure containing information
-*	    about a specific SD device. This function initializes an
-*	    InstancePtr object for a specific device specified by the
-*	    contents of Config.
+*        about a specific SD device. This function initializes an
+*        InstancePtr object for a specific device specified by the
+*        contents of Config.
 * @param    EffectiveAddr is the device base address in the virtual memory
-*	    address space. The caller is responsible for keeping the address
-*	    mapping from EffectiveAddr to the device physical base address
-*	    unchanged once this function is invoked. Unexpected errors may
-*	    occur if the address mapping changes after this function is
-*	    called. If address translation is not used, use
-*	    ConfigPtr->Config.BaseAddress for this device.
+*        address space. The caller is responsible for keeping the address
+*        mapping from EffectiveAddr to the device physical base address
+*        unchanged once this function is invoked. Unexpected errors may
+*        occur if the address mapping changes after this function is
+*        called. If address translation is not used, use
+*        ConfigPtr->Config.BaseAddress for this device.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_DEVICE_IS_STARTED if the device is already started.
-*	    It must be stopped to re-initialize.
+*        - XST_SUCCESS if successful.
+*        - XST_DEVICE_IS_STARTED if the device is already started.
+*        It must be stopped to re-initialize.
 *
-* @note	    This function initializes the host controller.
-*	    Initial clock of 400KHz is set.
-*	    Voltage of 3.3V is selected as that is supported by host.
-*	    Interrupts status is enabled and signal disabled by default.
-*	    Default data direction is card to host and
-*	    32 bit ADMA2 is selected. Default Block size is 512 bytes.
+* @note        This function initializes the host controller.
+*        Initial clock of 400KHz is set.
+*        Voltage of 3.3V is selected as that is supported by host.
+*        Interrupts status is enabled and signal disabled by default.
+*        Default data direction is card to host and
+*        32 bit ADMA2 is selected. Default Block size is 512 bytes.
 *
 ******************************************************************************/
 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-			    u32 EffectiveAddr)
+                u32 EffectiveAddr)
 {
     s32 Status;
 
@@ -140,13 +140,13 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
     InstancePtr->Config.RefClk = ConfigPtr->RefClk;
     Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
-	/* If this API is getting called twice, return value accordingly */
+    /* If this API is getting called twice, return value accordingly */
     if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
-	    Status = (s32)XST_DEVICE_IS_STARTED;
-	    goto RETURN_PATH ;
-	}
+        Status = (s32)XST_DEVICE_IS_STARTED;
+        goto RETURN_PATH ;
+    }
 
-	/* Set some default values. */
+    /* Set some default values. */
     InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
     InstancePtr->Config.BaseAddress = EffectiveAddr;
     InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
@@ -163,26 +163,26 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
     InstancePtr->Dma64BitAddr = 0U;
     InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
 
-	/* Host Controller version is read. */
+    /* Host Controller version is read. */
     InstancePtr->HC_Version =
-			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-		    XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+            (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+            XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
 
-	/*
-	 * Read capabilities register and update it in Instance pointer.
-	 * It is sufficient to read this once on power on.
-	 */
+    /*
+     * Read capabilities register and update it in Instance pointer.
+     * It is sufficient to read this once on power on.
+     */
     InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
-					    XSDPS_CAPS_OFFSET);
+                        XSDPS_CAPS_OFFSET);
 
-	/* Reset the SD bus lines */
+    /* Reset the SD bus lines */
     Status = XSdPs_ResetConfig(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH ;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH ;
+    }
 
-	/* Configure the SD Host Controller */
+    /* Configure the SD Host Controller */
     XSdPs_HostConfig(InstancePtr);
 
     InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
@@ -205,12 +205,12 @@ RETURN_PATH:
 * @param    InstancePtr is a pointer to the instance to be worked on.
 *
 * @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because
-* 		    a) SD is already initialized
-* 		    b) There is no card inserted
-* 		    c) One of the steps (commands) in the
-*			   initialization cycle failed
+*         - XST_SUCCESS if initialization was successful
+*         - XST_FAILURE if failure - could be because
+*             a) SD is already initialized
+*             b) There is no card inserted
+*             c) One of the steps (commands) in the
+*               initialization cycle failed
 *
 *
 ******************************************************************************/
@@ -221,7 +221,7 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/* Default settings */
+    /* Default settings */
     InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
     InstancePtr->CardType = XSDPS_CARD_SD;
     InstancePtr->Switch1v8 = 0U;
@@ -231,34 +231,34 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
     Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
-	/* Change the clock frequency to 400 KHz */
+    /* Change the clock frequency to 400 KHz */
     Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH ;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH ;
+    }
 
-	/* Identify the Card whether it is SD, MMC or eMMC */
+    /* Identify the Card whether it is SD, MMC or eMMC */
     Status = XSdPs_IdentifyCard(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Initialize the identified card */
+    /* Initialize the identified card */
     if (InstancePtr->CardType == XSDPS_CARD_SD) {
-	    Status = XSdPs_SdCardInitialize(InstancePtr);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	} else {
-	    Status = XSdPs_MmcCardInitialize(InstancePtr);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	}
+        Status = XSdPs_SdCardInitialize(InstancePtr);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    } else {
+        Status = XSdPs_MmcCardInitialize(InstancePtr);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    }
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
@@ -274,14 +274,14 @@ RETURN_PATH:
 *
 * @param    InstancePtr is a pointer to the instance to be worked on.
 * @param    Arg is the address passed by the user that is to be sent as
-* 	    argument along with the command.
+*         argument along with the command.
 * @param    BlkCnt - Block count passed by the user.
 * @param    Buff - Pointer to the data buffer for a DMA transfer.
 *
 * @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because another transfer
-* 	    is in progress or command or data inhibit is set
+*         - XST_SUCCESS if initialization was successful
+*         - XST_FAILURE if failure - could be because another transfer
+*         is in progress or command or data inhibit is set
 *
 ******************************************************************************/
 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
@@ -295,19 +295,19 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
     Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
-	/* Setup the Read Transfer */
+    /* Setup the Read Transfer */
     Status = XSdPs_SetupTransfer(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Read from the card */
+    /* Read from the card */
     Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
@@ -323,14 +323,14 @@ RETURN_PATH:
 *
 * @param    InstancePtr is a pointer to the instance to be worked on.
 * @param    Arg is the address passed by the user that is to be sent as
-* 	    argument along with the command.
+*         argument along with the command.
 * @param    BlkCnt - Block count passed by the user.
 * @param    Buff - Pointer to the data buffer for a DMA transfer.
 *
 * @return
-* 		- XST_SUCCESS if initialization was successful
-* 		- XST_FAILURE if failure - could be because another transfer
-* 	    is in progress or command or data inhibit is set
+*         - XST_SUCCESS if initialization was successful
+*         - XST_FAILURE if failure - could be because another transfer
+*         is in progress or command or data inhibit is set
 *
 ******************************************************************************/
 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
@@ -344,19 +344,19 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
     Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
-	/* Setup the Write Transfer */
+    /* Setup the Write Transfer */
     Status = XSdPs_SetupTransfer(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Write to the card */
+    /* Write to the card */
     Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
 RETURN_PATH:
 #if defined  (XCLOCKING)
@@ -376,7 +376,7 @@ RETURN_PATH:
 *
 * @return    None
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Idle(XSdPs *InstancePtr)
@@ -390,24 +390,24 @@ s32 XSdPs_Idle(XSdPs *InstancePtr)
     Xil_ClockEnable(InstancePtr->Config.RefClk);
 #endif
 
-	/* Check if the bus is idle */
+    /* Check if the bus is idle */
     Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
-										| XSDPS_PSR_INHIBIT_DAT_MASK
-										| XSDPS_PSR_DAT_ACTIVE_MASK);
+                                        | XSDPS_PSR_INHIBIT_DAT_MASK
+                                        | XSDPS_PSR_DAT_ACTIVE_MASK);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH ;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH ;
+    }
 
-	/* Disable the Bus Power */
+    /* Disable the Bus Power */
     XSdPs_DisableBusPower(InstancePtr);
 
-	/* Reset Command and Data Lines */
+    /* Reset Command and Data Lines */
     Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH ;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH ;
+    }
 
     Status = XST_SUCCESS;
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h

@@ -83,14 +83,14 @@
 * 2.2   hk     07/28/14 Make changes to enable use of data cache.
 * 2.3   sk     09/23/14 Send command for relative card address
 *                       when re-initialization is done.CR# 819614.
-*					    Use XSdPs_Change_ClkFreq API whenever changing
-*					    clock.CR# 816586.
-* 2.4    sk	   12/04/14 Added support for micro SD without
-* 					    WP/CD. CR# 810655.
-*					    Checked for DAT Inhibit mask instead of CMD
-* 					    Inhibit mask in Cmd Transfer API.
-*					    Added Support for SD Card v1.0
-* 2.5     sg	    07/09/15 Added SD 3.0 features
+*                        Use XSdPs_Change_ClkFreq API whenever changing
+*                        clock.CR# 816586.
+* 2.4    sk       12/04/14 Added support for micro SD without
+*                         WP/CD. CR# 810655.
+*                        Checked for DAT Inhibit mask instead of CMD
+*                         Inhibit mask in Cmd Transfer API.
+*                        Added Support for SD Card v1.0
+* 2.5     sg        07/09/15 Added SD 3.0 features
 *       kvn     07/15/15 Modified the code according to MISRAC-2012.
 * 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
 * 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -155,9 +155,9 @@ extern "C" {
 
 /************************** Constant Definitions *****************************/
 
-#define XSDPS_CT_ERROR    0x2L	/**< Command timeout flag */
-#define MAX_TUNING_COUNT    40U		/**< Maximum Tuning count */
-#define MAX_TIMEOUT	    0x1FFFFFFFU		/**< Maximum Timeout */
+#define XSDPS_CT_ERROR    0x2L    /**< Command timeout flag */
+#define MAX_TUNING_COUNT    40U        /**< Maximum Tuning count */
+#define MAX_TIMEOUT        0x1FFFFFFFU        /**< Maximum Timeout */
 #define XSDPS_CMD8_VOL_PATTERN    0x1AAU
 #define XSDPS_RESPOCR_READY    0x80000000U
 #define XSDPS_ACMD41_HCS    0x40000000U
@@ -171,21 +171,21 @@ extern "C" {
 #define UHS_SDR104_SUPPORT    0x8U
 #define UHS_DDR50_SUPPORT    0x10U
 #define WIDTH_4_BIT_SUPPORT    0x4U
-#define SD_CLK_25_MHZ	    25000000U
-#define SD_CLK_19_MHZ	    19000000U
-#define SD_CLK_26_MHZ	    26000000U
+#define SD_CLK_25_MHZ        25000000U
+#define SD_CLK_19_MHZ        19000000U
+#define SD_CLK_26_MHZ        26000000U
 #define EXT_CSD_DEVICE_TYPE_BYTE    196U
-#define EXT_CSD_SEC_COUNT_BYTE1	    212U
-#define EXT_CSD_SEC_COUNT_BYTE2	    213U
-#define EXT_CSD_SEC_COUNT_BYTE3	    214U
-#define EXT_CSD_SEC_COUNT_BYTE4	    215U
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED		    0x2U
+#define EXT_CSD_SEC_COUNT_BYTE1        212U
+#define EXT_CSD_SEC_COUNT_BYTE2        213U
+#define EXT_CSD_SEC_COUNT_BYTE3        214U
+#define EXT_CSD_SEC_COUNT_BYTE4        215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED            0x2U
 #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED    0x4U
 #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED    0x8U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200	    0x10U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200	    0x20U
-#define CSD_SPEC_VER_3	    0x3U
-#define SCR_SPEC_VER_3	    0x80U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200        0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200        0x20U
+#define CSD_SPEC_VER_3        0x3U
+#define SCR_SPEC_VER_3        0x80U
 #define ADDRESS_BEYOND_32BIT    0x100000000U
 
 /**************************** Type Definitions *******************************/
@@ -196,25 +196,25 @@ typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
  * This typedef contains configuration information for the device.
  */
 typedef struct {
-    u16 DeviceId;			/**< Unique ID  of device */
-    u32 BaseAddress;		/**< Base address of the device */
-    u32 InputClockHz;		/**< Input clock frequency */
-    u32 CardDetect;			/**< Card Detect */
-    u32 WriteProtect;			/**< Write Protect */
-    u32 BusWidth;			/**< Bus Width */
-    u32 BankNumber;			/**< MIO Bank selection for SD */
-    u32 HasEMIO;			/**< If SD is connected to EMIO */
-    u8 IsCacheCoherent; 		/**< If SD is Cache Coherent or not */
+    u16 DeviceId;            /**< Unique ID  of device */
+    u32 BaseAddress;        /**< Base address of the device */
+    u32 InputClockHz;        /**< Input clock frequency */
+    u32 CardDetect;            /**< Card Detect */
+    u32 WriteProtect;            /**< Write Protect */
+    u32 BusWidth;            /**< Bus Width */
+    u32 BankNumber;            /**< MIO Bank selection for SD */
+    u32 HasEMIO;            /**< If SD is connected to EMIO */
+    u8 IsCacheCoherent;         /**< If SD is Cache Coherent or not */
 #if defined  (XCLOCKING)
-    u32 RefClk;			/**< Input clocks */
+    u32 RefClk;            /**< Input clocks */
 #endif
 } XSdPs_Config;
 
 /* ADMA2 32-Bit descriptor table */
 typedef struct {
-    u16 Attribute;		/**< Attributes of descriptor */
-    u16 Length;		/**< Length of current dma transfer */
-    u32 Address;		/**< Address of current dma transfer */
+    u16 Attribute;        /**< Attributes of descriptor */
+    u16 Length;        /**< Length of current dma transfer */
+    u32 Address;        /**< Address of current dma transfer */
 #ifdef __ICCARM__
 #pragma data_alignment = 32
 } XSdPs_Adma2Descriptor32;
@@ -224,9 +224,9 @@ typedef struct {
 
 /* ADMA2 64-Bit descriptor table */
 typedef struct {
-    u16 Attribute;		/**< Attributes of descriptor */
-    u16 Length;		/**< Length of current dma transfer */
-    u64 Address;		/**< Address of current dma transfer */
+    u16 Attribute;        /**< Attributes of descriptor */
+    u16 Length;        /**< Length of current dma transfer */
+    u64 Address;        /**< Address of current dma transfer */
 #ifdef __ICCARM__
 #pragma data_alignment = 32
 } XSdPs_Adma2Descriptor64;
@@ -240,28 +240,28 @@ typedef struct {
  * to a variable of this type is then passed to the driver API functions.
  */
 typedef struct {
-    XSdPs_Config Config;	/**< Configuration structure */
-    u32 IsReady;		/**< Device is initialized and ready */
-    u32 Host_Caps;		/**< Capabilities of host controller */
-    u32 Host_CapsExt;	/**< Extended Capabilities */
-    u32 HCS;		/**< High capacity support in card */
-    u8  CardType;		/**< Type of card - SD/MMC/eMMC */
-    u8  Card_Version;	/**< Card version */
-    u8  HC_Version;		/**< Host controller version */
-    u8  BusWidth;		/**< Current operating bus width */
-    u32 BusSpeed;		/**< Current operating bus speed */
-    u8  Switch1v8;		/**< 1.8V Switch support */
-    u32 CardID[4];		/**< Card ID Register */
-    u32 RelCardAddr;	/**< Relative Card Address */
-    u32 CardSpecData[4];	/**< Card Specific Data Register */
-    u32 SectorCount;		/**< Sector Count */
-    u32 SdCardConfig;	/**< Sd Card Configuration Register */
-    u32 Mode;			/**< Bus Speed Mode */
-    u32 OTapDelay;		/**< Output Tap Delay */
-    u32 ITapDelay;		/**< Input Tap Delay */
-    u64 Dma64BitAddr;	/**< 64 Bit DMA Address */
-    u16 TransferMode;	/**< Transfer Mode */
-    u32 SlcrBaseAddr;	/**< SLCR base address*/
+    XSdPs_Config Config;    /**< Configuration structure */
+    u32 IsReady;        /**< Device is initialized and ready */
+    u32 Host_Caps;        /**< Capabilities of host controller */
+    u32 Host_CapsExt;    /**< Extended Capabilities */
+    u32 HCS;        /**< High capacity support in card */
+    u8  CardType;        /**< Type of card - SD/MMC/eMMC */
+    u8  Card_Version;    /**< Card version */
+    u8  HC_Version;        /**< Host controller version */
+    u8  BusWidth;        /**< Current operating bus width */
+    u32 BusSpeed;        /**< Current operating bus speed */
+    u8  Switch1v8;        /**< 1.8V Switch support */
+    u32 CardID[4];        /**< Card ID Register */
+    u32 RelCardAddr;    /**< Relative Card Address */
+    u32 CardSpecData[4];    /**< Card Specific Data Register */
+    u32 SectorCount;        /**< Sector Count */
+    u32 SdCardConfig;    /**< Sd Card Configuration Register */
+    u32 Mode;            /**< Bus Speed Mode */
+    u32 OTapDelay;        /**< Output Tap Delay */
+    u32 ITapDelay;        /**< Input Tap Delay */
+    u64 Dma64BitAddr;    /**< 64 Bit DMA Address */
+    u16 TransferMode;    /**< Transfer Mode */
+    u32 SlcrBaseAddr;    /**< SLCR base address*/
 } XSdPs;
 
 /***************** Macros (Inline Functions) Definitions *********************/
@@ -269,7 +269,7 @@ typedef struct {
 /************************** Function Prototypes ******************************/
 XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
-			    u32 EffectiveAddr);
+                u32 EffectiveAddr);
 s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c

@@ -22,28 +22,28 @@
 
 XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
 {
-	{
-	    XPAR_PSU_SD_0_DEVICE_ID,
-	    XPAR_PSU_SD_0_BASEADDR,
-	    XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
-	    XPAR_PSU_SD_0_HAS_CD,
-	    XPAR_PSU_SD_0_HAS_WP,
-	    XPAR_PSU_SD_0_BUS_WIDTH,
-	    XPAR_PSU_SD_0_MIO_BANK,
-	    XPAR_PSU_SD_0_HAS_EMIO,
-	    XPAR_PSU_SD_0_IS_CACHE_COHERENT
-	},
-	{
-	    XPAR_PSU_SD_1_DEVICE_ID,
-	    XPAR_PSU_SD_1_BASEADDR,
-	    XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
-	    XPAR_PSU_SD_1_HAS_CD,
-	    XPAR_PSU_SD_1_HAS_WP,
-	    XPAR_PSU_SD_1_BUS_WIDTH,
-	    XPAR_PSU_SD_1_MIO_BANK,
-	    XPAR_PSU_SD_1_HAS_EMIO,
-	    XPAR_PSU_SD_1_IS_CACHE_COHERENT
-	}
+    {
+        XPAR_PSU_SD_0_DEVICE_ID,
+        XPAR_PSU_SD_0_BASEADDR,
+        XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
+        XPAR_PSU_SD_0_HAS_CD,
+        XPAR_PSU_SD_0_HAS_WP,
+        XPAR_PSU_SD_0_BUS_WIDTH,
+        XPAR_PSU_SD_0_MIO_BANK,
+        XPAR_PSU_SD_0_HAS_EMIO,
+        XPAR_PSU_SD_0_IS_CACHE_COHERENT
+    },
+    {
+        XPAR_PSU_SD_1_DEVICE_ID,
+        XPAR_PSU_SD_1_BASEADDR,
+        XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+        XPAR_PSU_SD_1_HAS_CD,
+        XPAR_PSU_SD_1_HAS_WP,
+        XPAR_PSU_SD_1_BUS_WIDTH,
+        XPAR_PSU_SD_1_MIO_BANK,
+        XPAR_PSU_SD_1_HAS_EMIO,
+        XPAR_PSU_SD_1_IS_CACHE_COHERENT
+    }
 };
 
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c

@@ -22,8 +22,8 @@
 * 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
 *                       Add sleep for microblaze designs. CR# 781117.
 * 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-*					    clock.CR# 816586.
-* 2.5     sg	   07/09/15 Added SD 3.0 features
+*                        clock.CR# 816586.
+* 2.5     sg       07/09/15 Added SD 3.0 features
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
 *                       of SDR50, SDR104 and HS200.
@@ -44,7 +44,7 @@
 *       sk     03/20/17 Add support for EL1 non-secure mode.
 * 3.3   mn     07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
 *       mn     08/07/17    Properly set OTAPDLY value by clearing previous bit
-* 		    settings
+*             settings
 *       mn     08/17/17 Added CCI support for A53 and disabled data cache
 *                       operations when it is enabled.
 *       mn     08/22/17 Updated for Word Access System support
@@ -84,8 +84,8 @@
 *
 * @return    None
 *
-* @note	    This API will change clock frequency to the value less than
-*	    or equal to the given value using the permissible dividors.
+* @note        This API will change clock frequency to the value less than
+*        or equal to the given value using the permissible dividors.
 *
 ******************************************************************************/
 s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
@@ -96,14 +96,14 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
-		/* Program the Tap delays */
-	    XSdPs_SetTapDelay(InstancePtr);
-	}
+        /* Program the Tap delays */
+        XSdPs_SetTapDelay(InstancePtr);
+    }
 
     Status = XSdPs_SetClock(InstancePtr, SelFreq);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     return Status;
 }
@@ -127,24 +127,24 @@ s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK
-											| XSDPS_PSR_INHIBIT_DAT_MASK
-											| XSDPS_PSR_WR_ACTIVE_MASK
-											| XSDPS_PSR_RD_ACTIVE_MASK));
+                                            | XSDPS_PSR_INHIBIT_DAT_MASK
+                                            | XSDPS_PSR_WR_ACTIVE_MASK
+                                            | XSDPS_PSR_RD_ACTIVE_MASK));
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH ;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH ;
+    }
 
-	/* Send block write command */
+    /* Send block write command */
     Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Set block size to the value passed */
+    /* Set block size to the value passed */
     XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
-			 BlkSize & XSDPS_BLK_SIZE_MASK);
+             BlkSize & XSDPS_BLK_SIZE_MASK);
 
 RETURN_PATH:
     return Status;
@@ -161,10 +161,10 @@ RETURN_PATH:
 * @param    SCR - buffer to store SCR register returned by card.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
@@ -178,16 +178,16 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
-	    ReadBuff[LoopCnt] = 0U;
-	}
+        ReadBuff[LoopCnt] = 0U;
+    }
 
-	/* Send block write command */
+    /* Send block write command */
     Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-		    InstancePtr->RelCardAddr, 0U);
+            InstancePtr->RelCardAddr, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
     BlkCnt = XSDPS_SCR_BLKCNT;
     BlkSize = XSDPS_SCR_BLKSIZE;
@@ -196,25 +196,25 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
 
     Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Check for transfer done */
+    /* Check for transfer done */
     Status = XSdps_CheckTransferDone(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     if (InstancePtr->Config.IsCacheCoherent == 0U) {
-	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
-				(INTPTR)BlkCnt * BlkSize);
-	}
+        Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+                (INTPTR)BlkCnt * BlkSize);
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -228,10 +228,10 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
 * @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
@@ -243,81 +243,81 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/*
-	 * check for bus width for 3.0 controller and return if
-	 * bus width is <4
-	 */
+    /*
+     * check for bus width for 3.0 controller and return if
+     * bus width is <4
+     */
     if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
-			(InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
-	    Status = XST_SUCCESS;
-	    goto RETURN_PATH;
-	}
+            (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+        Status = XST_SUCCESS;
+        goto RETURN_PATH;
+    }
 
     if (InstancePtr->CardType == XSDPS_CARD_SD) {
 
-	    Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
-			    0U);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-
-	    Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	} else {
-	    if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-		    if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-			    Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
-			} else {
-			    Arg = XSDPS_MMC_8_BIT_BUS_ARG;
-			}
-		} else {
-		    if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-			    Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
-			} else {
-			    Arg = XSDPS_MMC_4_BIT_BUS_ARG;
-			}
-		}
-
-	    Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	}
+        Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+                0U);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+
+        Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    } else {
+        if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+            if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+                Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+            } else {
+                Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+            }
+        } else {
+            if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+                Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+            } else {
+                Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+            }
+        }
+
+        Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    }
 
     usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
     StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-				    XSDPS_HOST_CTRL1_OFFSET);
+                    XSDPS_HOST_CTRL1_OFFSET);
 
-	/* Width setting in controller */
+    /* Width setting in controller */
     if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
-	    StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
-	} else {
-	    StatusReg |= XSDPS_HC_WIDTH_MASK;
-	}
+        StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+    } else {
+        StatusReg |= XSDPS_HC_WIDTH_MASK;
+    }
 
     XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-		    XSDPS_HOST_CTRL1_OFFSET,
-			(u8)StatusReg);
+            XSDPS_HOST_CTRL1_OFFSET,
+            (u8)StatusReg);
 
     if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
-	    StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				    XSDPS_HOST_CTRL2_OFFSET);
-	    StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
-	    StatusReg |= InstancePtr->Mode;
-	    XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
-				    XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
-	}
+        StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+                    XSDPS_HOST_CTRL2_OFFSET);
+        StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
+        StatusReg |= InstancePtr->Mode;
+        XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+                    XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -330,13 +330,13 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 *
 * @param    InstancePtr is a pointer to the XSdPs instance.
 * @param    ReadBuff - buffer to store function group support data
-*	    returned by card.
+*        returned by card.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
@@ -351,8 +351,8 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
-	    ReadBuff[LoopCnt] = 0U;
-	}
+        ReadBuff[LoopCnt] = 0U;
+    }
 
     BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
     BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
@@ -363,25 +363,25 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 
     Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Check for transfer done */
+    /* Check for transfer done */
     Status = XSdps_CheckTransferDone(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     if (InstancePtr->Config.IsCacheCoherent == 0U) {
-	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
-				(INTPTR)BlkCnt * BlkSize);
-	}
+        Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+                (INTPTR)BlkCnt * BlkSize);
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -396,10 +396,10 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 * @param    SdStatReg - buffer to store status data returned by card.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
@@ -411,13 +411,13 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/* Send block write command */
+    /* Send block write command */
     Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-		    InstancePtr->RelCardAddr, 0U);
+            InstancePtr->RelCardAddr, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
     BlkCnt = XSDPS_SD_STATUS_BLKCNT;
     BlkSize = XSDPS_SD_STATUS_BLKSIZE;
@@ -426,25 +426,25 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
 
     Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Check for transfer done */
+    /* Check for transfer done */
     Status = XSdps_CheckTransferDone(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     if (InstancePtr->Config.IsCacheCoherent == 0U) {
-	    Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
-				(INTPTR)BlkCnt * BlkSize);
-	}
+        Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
+                (INTPTR)BlkCnt * BlkSize);
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 }
 
 /*****************************************************************************/
@@ -457,10 +457,10 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
 * @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
@@ -472,47 +472,47 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     if (InstancePtr->CardType == XSDPS_CARD_SD) {
-	    Status = XSdPs_Change_SdBusSpeed(InstancePtr);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	} else {
-	    Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	}
+        Status = XSdPs_Change_SdBusSpeed(InstancePtr);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    } else {
+        Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    }
 
     Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
     if ((InstancePtr->Mode == XSDPS_HS200_MODE) ||
-		(InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
-		(InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
-	    Status = XSdPs_Execute_Tuning(InstancePtr);
-	    if (Status != XST_SUCCESS) {
-		    Status = XST_FAILURE;
-		    goto RETURN_PATH;
-		}
-	}
+        (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+        (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+        Status = XSdPs_Execute_Tuning(InstancePtr);
+        if (Status != XST_SUCCESS) {
+            Status = XST_FAILURE;
+            goto RETURN_PATH;
+        }
+    }
 
     usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
     StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
-				    XSDPS_HOST_CTRL1_OFFSET);
+                    XSDPS_HOST_CTRL1_OFFSET);
     StatusReg |= XSDPS_HC_SPEED_MASK;
     XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-		    XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+            XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -527,10 +527,10 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 * @param    ReadBuff - buffer to store EXT_CSD
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
@@ -545,36 +545,36 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
-	    ReadBuff[LoopCnt] = 0U;
-	}
+        ReadBuff[LoopCnt] = 0U;
+    }
 
     BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
     BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
 
     XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
 
-	/* Send SEND_EXT_CSD command */
+    /* Send SEND_EXT_CSD command */
     Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Check for transfer done */
+    /* Check for transfer done */
     Status = XSdps_CheckTransferDone(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     if (InstancePtr->Config.IsCacheCoherent == 0U) {
-	    Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
-				(INTPTR)BlkCnt * BlkSize);
-	}
+        Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
+                (INTPTR)BlkCnt * BlkSize);
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -589,10 +589,10 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 * @param    Arg is the argument to be sent along with the command
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
@@ -604,20 +604,20 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
 
     Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
-	/* Check for transfer done */
+    /* Check for transfer done */
     Status = XSdps_CheckTransferDone(InstancePtr);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	}
+        Status = XST_FAILURE;
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -631,10 +631,10 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
 * @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Pullup(XSdPs *InstancePtr)
@@ -645,22 +645,22 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
     Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
-		    InstancePtr->RelCardAddr, 0U);
+            InstancePtr->RelCardAddr, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
     Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
     if (Status != XST_SUCCESS) {
-	    Status = XST_FAILURE;
-	    goto RETURN_PATH;
-	}
+        Status = XST_FAILURE;
+        goto RETURN_PATH;
+    }
 
     Status = XST_SUCCESS;
 
     RETURN_PATH:
-	    return Status;
+        return Status;
 
 }
 
@@ -674,11 +674,11 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr)
 * @param    InstancePtr is a pointer to the XSdPs instance.
 *
 * @return
-*		- XST_SUCCESS if successful.
-*		- XST_FAILURE if fail.
-*		- XSDPS_CT_ERROR if Command Transfer fail.
+*        - XST_SUCCESS if successful.
+*        - XST_FAILURE if fail.
+*        - XSDPS_CT_ERROR if Command Transfer fail.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 s32 XSdPs_Select_Card (XSdPs *InstancePtr)
@@ -688,9 +688,9 @@ s32 XSdPs_Select_Card (XSdPs *InstancePtr)
     Xil_AssertNonvoid(InstancePtr != NULL);
     Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/* Send CMD7 - Select card */
+    /* Send CMD7 - Select card */
     Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
-		    InstancePtr->RelCardAddr, 0U);
+            InstancePtr->RelCardAddr, 0U);
 
     return Status;
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c

@@ -49,14 +49,14 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
 * contains the configuration info for each device in the system.
 *
 * @param    DeviceId contains the ID of the device to look up the
-*	    configuration for.
+*        configuration for.
 *
 * @return
 *
 * A pointer to the configuration found or NULL if the specified device ID was
 * not found. See xsdps.h for the definition of XSdPs_Config.
 *
-* @note	    None.
+* @note        None.
 *
 ******************************************************************************/
 XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
@@ -65,11 +65,11 @@ XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
     u32 Index;
 
     for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
-	    if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
-		    CfgPtr = &XSdPs_ConfigTable[Index];
-		    break;
-		}
-	}
+        if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+            CfgPtr = &XSdPs_ConfigTable[Index];
+            break;
+        }
+    }
     return (XSdPs_Config *)CfgPtr;
 }
 /** @} */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h

@@ -73,9 +73,9 @@ enum ethernet_link_status {
 };
 
 void eth_link_detect(struct netif *netif);
-void 	    lwip_raw_init();
-int 	    xemacif_input(struct netif *netif);
-void 	    xemacif_input_thread(struct netif *netif);
+void         lwip_raw_init();
+int         xemacif_input(struct netif *netif);
+void         xemacif_input_thread(struct netif *netif);
 struct netif *    xemac_add(struct netif *netif,
     ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
     unsigned char *mac_ethernet_address,

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h

@@ -45,7 +45,7 @@ extern "C" {
 #include "xstatus.h"
 #include "sleep.h"
 #include "xparameters.h"
-#include "xparameters_ps.h"	/* defines XPAR values */
+#include "xparameters_ps.h"    /* defines XPAR values */
 #include "xil_types.h"
 #include "xil_assert.h"
 #include "xil_io.h"
@@ -55,7 +55,7 @@ extern "C" {
 #include "xil_cache.h"
 #include "xil_printf.h"
 // #include "xscugic.h"
-#include "xemacps.h"		/* defines XEmacPs API */
+#include "xemacps.h"        /* defines XEmacPs API */
 
 #include "netif/xpqueue.h"
 #include "xlwipconfig.h"
@@ -88,7 +88,7 @@ extern "C" {
 #define VERSAL_CRL_GEM0_REF_CTRL    0xFF5E0118
 #define VERSAL_CRL_GEM1_REF_CTRL    0xFF5E011C
 
-#define VERSAL_CRL_GEM_DIV_MASK	    0x0003FF00
+#define VERSAL_CRL_GEM_DIV_MASK        0x0003FF00
 #define VERSAL_CRL_APB_GEM_DIV_SHIFT    8
 
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
@@ -116,11 +116,11 @@ void     xemacps_error_handler(XEmacPs * Temac);
 typedef struct {
     XEmacPs emacps;
 
-	/* queue to store overflow packets */
+    /* queue to store overflow packets */
     pq_queue_t *recv_q;
     pq_queue_t *send_q;
 
-	/* pointers to memory holding buffer descriptors (used only with SDMA) */
+    /* pointers to memory holding buffer descriptors (used only with SDMA) */
     void *rx_bdspace;
     void *tx_bdspace;
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h

@@ -43,9 +43,9 @@ typedef struct {
 } pq_queue_t;
 
 pq_queue_t*    pq_create_queue();
-int 	    pq_enqueue(pq_queue_t *q, void *p);
-void*	    pq_dequeue(pq_queue_t *q);
-int	    pq_qlength(pq_queue_t *q);
+int         pq_enqueue(pq_queue_t *q, void *p);
+void*        pq_dequeue(pq_queue_t *q);
+int        pq_qlength(pq_queue_t *q);
 
 #ifdef __cplusplus
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h

@@ -41,7 +41,7 @@ struct xtopology_t {
     unsigned emac_baseaddr;
     enum xemac_types emac_type;
     unsigned intc_baseaddr;
-    unsigned intc_emac_intr;	/* valid only for xemac_type_xps_emaclite */
+    unsigned intc_emac_intr;    /* valid only for xemac_type_xps_emaclite */
     unsigned scugic_baseaddr; /* valid only for Zynq */
     unsigned scugic_emac_intr; /* valid only for GEM */
 };

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c

@@ -83,14 +83,14 @@ u32_t phyaddrforemac;
 void
 lwip_raw_init()
 {
-    ip_init();	/* Doesn't do much, it should be called to handle future changes. */
+    ip_init();    /* Doesn't do much, it should be called to handle future changes. */
 #if LWIP_UDP
-    udp_init();	/* Clears the UDP PCB list. */
+    udp_init();    /* Clears the UDP PCB list. */
 #endif
 #if LWIP_TCP
-    tcp_init();	/* Clears the TCP PCB list and clears some internal TCP timers. */
-			/* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
-			/* predefined regular intervals after this initialization. */
+    tcp_init();    /* Clears the TCP PCB list and clears some internal TCP timers. */
+            /* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
+            /* predefined regular intervals after this initialization. */
 #endif
 }
 
@@ -100,9 +100,9 @@ find_mac_type(unsigned base)
     int i;
 
     for (i = 0; i < xtopology_n_emacs; i++) {
-	    if (xtopology[i].emac_baseaddr == base)
-		    return xtopology[i].emac_type;
-	}
+        if (xtopology[i].emac_baseaddr == base)
+            return xtopology[i].emac_type;
+    }
 
     return xemac_type_unknown;
 }
@@ -113,9 +113,9 @@ xtopology_find_index(unsigned base)
     int i;
 
     for (i = 0; i < xtopology_n_emacs; i++) {
-	    if (xtopology[i].emac_baseaddr == base)
-		    return i;
-	}
+        if (xtopology[i].emac_baseaddr == base)
+            return i;
+    }
 
     return -1;
 }
@@ -135,66 +135,66 @@ xemac_add(struct netif *netif,
     int i;
 
 #ifdef OS_IS_FREERTOS
-	/* Start thread to detect link periodically for Hot Plug autodetect */
+    /* Start thread to detect link periodically for Hot Plug autodetect */
     sys_thread_new("link_detect_thread", link_detect_thread, netif,
-		    THREAD_STACKSIZE, tskIDLE_PRIORITY);
+            THREAD_STACKSIZE, tskIDLE_PRIORITY);
 #endif
 
-	/* set mac address */
+    /* set mac address */
     netif->hwaddr_len = 6;
     for (i = 0; i < 6; i++)
-	    netif->hwaddr[i] = mac_ethernet_address[i];
+        netif->hwaddr[i] = mac_ethernet_address[i];
 
-	/* initialize based on MAC type */
-	    switch (find_mac_type(mac_baseaddr)) {
-		    case xemac_type_xps_emaclite:
+    /* initialize based on MAC type */
+        switch (find_mac_type(mac_baseaddr)) {
+            case xemac_type_xps_emaclite:
 #ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
-			    return netif_add(netif, ipaddr, netmask, gw,
-					(void*)(UINTPTR)mac_baseaddr,
-				    xemacliteif_init,
+                return netif_add(netif, ipaddr, netmask, gw,
+                    (void*)(UINTPTR)mac_baseaddr,
+                    xemacliteif_init,
 #if NO_SYS
-				    ethernet_input
+                    ethernet_input
 #else
-				    tcpip_input
+                    tcpip_input
 #endif
-					);
+                    );
 #else
-			    return NULL;
+                return NULL;
 #endif
-		    case xemac_type_axi_ethernet:
+            case xemac_type_axi_ethernet:
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
-			    return netif_add(netif, ipaddr, netmask, gw,
-					(void*)(UINTPTR)mac_baseaddr,
-				    xaxiemacif_init,
+                return netif_add(netif, ipaddr, netmask, gw,
+                    (void*)(UINTPTR)mac_baseaddr,
+                    xaxiemacif_init,
 #if NO_SYS
-				    ethernet_input
+                    ethernet_input
 #else
-				    tcpip_input
+                    tcpip_input
 #endif
-					);
+                    );
 #else
-			    return NULL;
+                return NULL;
 #endif
 #if defined (__arm__) || defined (__aarch64__)
-		    case xemac_type_emacps:
+            case xemac_type_emacps:
 #ifdef XLWIP_CONFIG_INCLUDE_GEM
-			    return netif_add(netif, ipaddr, netmask, gw,
-						(void*)(UINTPTR)mac_baseaddr,
-					    xemacpsif_init,
+                return netif_add(netif, ipaddr, netmask, gw,
+                        (void*)(UINTPTR)mac_baseaddr,
+                        xemacpsif_init,
 #if NO_SYS
-					    ethernet_input
+                        ethernet_input
 #else
-					    tcpip_input
+                        tcpip_input
 #endif
 
-						);
+                        );
 #endif
 #endif
-		    default:
-			    xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
-					    mac_baseaddr);
-			    return NULL;
-	}
+            default:
+                xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
+                        mac_baseaddr);
+                return NULL;
+    }
 }
 
 #if 0
@@ -208,15 +208,15 @@ xemacif_input_thread(struct netif *netif)
 {
     struct xemac_s *emac = (struct xemac_s *)netif->state;
     while (1) {
-		/* sleep until there are packets to process
-		 * This semaphore is set by the packet receive interrupt
-		 * routine.
-		 */
-	    sys_sem_wait(&emac->sem_rx_data_available);
-
-		/* move all received packets to lwIP */
-	    xemacif_input(netif);
-	}
+        /* sleep until there are packets to process
+         * This semaphore is set by the packet receive interrupt
+         * routine.
+         */
+        sys_sem_wait(&emac->sem_rx_data_available);
+
+        /* move all received packets to lwIP */
+        xemacif_input(netif);
+    }
 }
 #endif
 
@@ -228,40 +228,40 @@ xemacif_input(struct netif *netif)
     int n_packets = 0;
 
     switch (emac->type) {
-	    case xemac_type_xps_emaclite:
+        case xemac_type_xps_emaclite:
 #ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
-		    n_packets = xemacliteif_input(netif);
-		    break;
+            n_packets = xemacliteif_input(netif);
+            break;
 #else
-			// print("incorrect configuration: xps_ethernetlite drivers not present?");
-		    while(1);
-		    return 0;
+            // print("incorrect configuration: xps_ethernetlite drivers not present?");
+            while(1);
+            return 0;
 #endif
-	    case xemac_type_axi_ethernet:
+        case xemac_type_axi_ethernet:
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
-		    n_packets = xaxiemacif_input(netif);
-		    break;
+            n_packets = xaxiemacif_input(netif);
+            break;
 #else
-			// print("incorrect configuration: axi_ethernet drivers not present?");
-		    while(1);
-		    return 0;
+            // print("incorrect configuration: axi_ethernet drivers not present?");
+            while(1);
+            return 0;
 #endif
 #if defined (__arm__) || defined (__aarch64__)
-	    case xemac_type_emacps:
+        case xemac_type_emacps:
 #ifdef XLWIP_CONFIG_INCLUDE_GEM
-		    n_packets = xemacpsif_input(netif);
-		    break;
+            n_packets = xemacpsif_input(netif);
+            break;
 #else
-		    xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
-		    while(1);
-		    return 0;
+            xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
+            while(1);
+            return 0;
 #endif
 #endif
-	    default:
-			// print("incorrect configuration: unknown temac type");
-		    while(1);
-		    return 0;
-	}
+        default:
+            // print("incorrect configuration: unknown temac type");
+            while(1);
+            return 0;
+    }
 
     return n_packets;
 }
@@ -271,14 +271,14 @@ u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_LINK_STATUS)
-	    return 1;
+        return 1;
     return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
@@ -286,14 +286,14 @@ static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_LINK_STATUS)
-	    return 1;
+        return 1;
     return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
@@ -301,14 +301,14 @@ static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_LINK_STATUS)
-	    return 1;
+        return 1;
     return 0;
 }
 #endif
@@ -318,14 +318,14 @@ u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-	    return 1;
+        return 1;
     return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
@@ -333,14 +333,14 @@ static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-	    return 1;
+        return 1;
     return 0;
 }
 #elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
@@ -348,14 +348,14 @@ static u32_t phy_autoneg_status(XEmacLite *xemacp, u32_t phy_addr)
 {
     u16_t status;
 
-	/* Read Phy Status register twice to get the confirmation of the current
-	 * link status.
-	 */
+    /* Read Phy Status register twice to get the confirmation of the current
+     * link status.
+     */
     XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
-	    return 1;
+        return 1;
     return 0;
 }
 #endif
@@ -377,43 +377,43 @@ void eth_link_detect(struct netif *netif)
 #endif
 
     if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
-			(eth_link_status == ETH_LINK_UNDEFINED))
-	    return;
+            (eth_link_status == ETH_LINK_UNDEFINED))
+        return;
 
     phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
 
     if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
-	    eth_link_status = ETH_LINK_DOWN;
+        eth_link_status = ETH_LINK_DOWN;
 
     switch (eth_link_status) {
-	    case ETH_LINK_UNDEFINED:
-	    case ETH_LINK_UP:
-		    return;
-	    case ETH_LINK_DOWN:
-		    netif_set_link_down(netif);
-		    eth_link_status = ETH_LINK_NEGOTIATING;
-		    xil_printf("Ethernet Link down\r\n");
-		    break;
-	    case ETH_LINK_NEGOTIATING:
-		    if (phy_link_status &&
-			    phy_autoneg_status(xemacp, phyaddrforemac)) {
-
-				/* Initiate Phy setup to get link speed */
+        case ETH_LINK_UNDEFINED:
+        case ETH_LINK_UP:
+            return;
+        case ETH_LINK_DOWN:
+            netif_set_link_down(netif);
+            eth_link_status = ETH_LINK_NEGOTIATING;
+            xil_printf("Ethernet Link down\r\n");
+            break;
+        case ETH_LINK_NEGOTIATING:
+            if (phy_link_status &&
+                phy_autoneg_status(xemacp, phyaddrforemac)) {
+
+                /* Initiate Phy setup to get link speed */
 #if defined(XLWIP_CONFIG_INCLUDE_GEM)
-			    link_speed = phy_setup_emacps(xemacp,
-							    phyaddrforemac);
-			    XEmacPs_SetOperatingSpeed(xemacp, link_speed);
+                link_speed = phy_setup_emacps(xemacp,
+                                phyaddrforemac);
+                XEmacPs_SetOperatingSpeed(xemacp, link_speed);
 #elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
-			    link_speed = phy_setup_axiemac(xemacp);
-			    XAxiEthernet_SetOperatingSpeed(xemacp,
-							       link_speed);
+                link_speed = phy_setup_axiemac(xemacp);
+                XAxiEthernet_SetOperatingSpeed(xemacp,
+                                   link_speed);
 #endif
-			    netif_set_link_up(netif);
-			    eth_link_status = ETH_LINK_UP;
-			    xil_printf("Ethernet Link up\r\n");
-			}
-		    break;
-	}
+                netif_set_link_up(netif);
+                eth_link_status = ETH_LINK_UP;
+                xil_printf("Ethernet Link up\r\n");
+            }
+            break;
+    }
 }
 
 #ifdef OS_IS_FREERTOS
@@ -422,11 +422,11 @@ void link_detect_thread(void *p)
     struct netif *netif = (struct netif *) p;
 
     while (1) {
-		/* Call eth_link_detect() every second to detect Ethernet link
-		 * change.
-		 */
-	    eth_link_detect(netif);
-	    vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
-	}
+        /* Call eth_link_detect() every second to detect Ethernet link
+         * change.
+         */
+        eth_link_detect(netif);
+        vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
+    }
 }
 #endif

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h

@@ -44,7 +44,7 @@
 
 
 #define ADVERTISE_100_AND_10        (ADVERTISE_10FULL | ADVERTISE_100FULL | \
-				    ADVERTISE_10HALF | ADVERTISE_100HALF)
+                    ADVERTISE_10HALF | ADVERTISE_100HALF)
 #define ADVERTISE_100               (ADVERTISE_100FULL | ADVERTISE_100HALF)
 #define ADVERTISE_10                (ADVERTISE_10FULL | ADVERTISE_10HALF)
 

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c

@@ -76,14 +76,14 @@
 
 #if LWIP_IGMP
 static err_t xemacpsif_mac_filter_update (struct netif *netif,
-						    ip_addr_t *group, u8_t action);
+                            ip_addr_t *group, u8_t action);
 
 static u8_t xemacps_mcast_entry_mask = 0;
 #endif
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
 static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif,
-						    ip_addr_t *group, u8_t action);
+                            ip_addr_t *group, u8_t action);
 
 static u8_t xemacps_mld6_mcast_entry_mask;
 #endif
@@ -101,22 +101,22 @@ int32_t lExpireCounter = 0;
  * this function also assumes that there are available BD's
  */
 err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif,
-												    struct pbuf *p)
+                                                    struct pbuf *p)
 {
     XStatus status = 0;
 
 #if ETH_PAD_SIZE
-    pbuf_header(p, -ETH_PAD_SIZE);	/* drop the padding word */
+    pbuf_header(p, -ETH_PAD_SIZE);    /* drop the padding word */
 #endif
     status = emacps_sgsend(xemacpsif, p);
     if (status != XST_SUCCESS) {
 #if LINK_STATS
     lwip_stats.link.drop++;
 #endif
-	}
+    }
 
 #if ETH_PAD_SIZE
-    pbuf_header(p, ETH_PAD_SIZE);	/* reclaim the padding word */
+    pbuf_header(p, ETH_PAD_SIZE);    /* reclaim the padding word */
 #endif
 
 #if LINK_STATS
@@ -148,23 +148,23 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
 
     SYS_ARCH_PROTECT(lev);
 
-	/* check if space is available to send */
+    /* check if space is available to send */
     freecnt = is_tx_space_available(xemacpsif);
     if (freecnt <= 5) {
     txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
-	    process_sent_bds(xemacpsif, txring);
-	}
+        process_sent_bds(xemacpsif, txring);
+    }
 
     if (is_tx_space_available(xemacpsif)) {
-	    _unbuffered_low_level_output(xemacpsif, p);
-	    err = ERR_OK;
-	} else {
+        _unbuffered_low_level_output(xemacpsif, p);
+        err = ERR_OK;
+    } else {
 #if LINK_STATS
-	    lwip_stats.link.drop++;
+        lwip_stats.link.drop++;
 #endif
-	    rt_kprintf("pack dropped, no space\r\n");
-	    err = ERR_MEM;
-	}
+        rt_kprintf("pack dropped, no space\r\n");
+        err = ERR_MEM;
+    }
 
     SYS_ARCH_UNPROTECT(lev);
     return err;
@@ -183,11 +183,11 @@ static struct pbuf * low_level_input(struct netif *netif)
     xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
     struct pbuf *p;
 
-	/* see if there is data to process */
+    /* see if there is data to process */
     if (pq_qlength(xemacpsif->recv_q) == 0)
-	    return NULL;
+        return NULL;
 
-	/* return one packet from receive q */
+    /* return one packet from receive q */
     p = (struct pbuf *)pq_dequeue(xemacpsif->recv_q);
     return p;
 }
@@ -202,9 +202,9 @@ static struct pbuf * low_level_input(struct netif *netif)
  */
 
 static err_t xemacpsif_output(struct netif *netif, struct pbuf *p,
-	    const ip_addr_t *ipaddr)
+        const ip_addr_t *ipaddr)
 {
-	/* resolve hardware address, then send (or queue) packet */
+    /* resolve hardware address, then send (or queue) packet */
     return etharp_output(netif, p, ipaddr);
 }
 
@@ -230,51 +230,51 @@ s32_t xemacpsif_input(struct netif *netif)
 #ifdef OS_IS_FREERTOS
     while (1)
 #endif
-	{
-		/* move received packet into a new pbuf */
-	    SYS_ARCH_PROTECT(lev);
-	    p = low_level_input(netif);
-	    SYS_ARCH_UNPROTECT(lev);
-
-		/* no packet could be read, silently ignore this */
-	    if (p == NULL) {
-		    return 0;
-		}
-
-		/* points to packet payload, which starts with an Ethernet header */
-	    ethhdr = p->payload;
-
-	#if LINK_STATS
-	    lwip_stats.link.recv++;
-	#endif /* LINK_STATS */
-
-	    switch (htons(ethhdr->type)) {
-			/* IP or ARP packet? */
-		    case ETHTYPE_IP:
-		    case ETHTYPE_ARP:
-	#if LWIP_IPV6
-			/*IPv6 Packet?*/
-		    case ETHTYPE_IPV6:
-	#endif
-	#if PPPOE_SUPPORT
-				/* PPPoE packet? */
-		    case ETHTYPE_PPPOEDISC:
-		    case ETHTYPE_PPPOE:
-	#endif /* PPPOE_SUPPORT */
-				/* full packet send to tcpip_thread to process */
-			    if (netif->input(p, netif) != ERR_OK) {
-				    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n"));
-				    pbuf_free(p);
-				    p = NULL;
-				}
-			    break;
-
-		    default:
-			    pbuf_free(p);
-			    p = NULL;
-			    break;
-		}
-	}
+    {
+        /* move received packet into a new pbuf */
+        SYS_ARCH_PROTECT(lev);
+        p = low_level_input(netif);
+        SYS_ARCH_UNPROTECT(lev);
+
+        /* no packet could be read, silently ignore this */
+        if (p == NULL) {
+            return 0;
+        }
+
+        /* points to packet payload, which starts with an Ethernet header */
+        ethhdr = p->payload;
+
+    #if LINK_STATS
+        lwip_stats.link.recv++;
+    #endif /* LINK_STATS */
+
+        switch (htons(ethhdr->type)) {
+            /* IP or ARP packet? */
+            case ETHTYPE_IP:
+            case ETHTYPE_ARP:
+    #if LWIP_IPV6
+            /*IPv6 Packet?*/
+            case ETHTYPE_IPV6:
+    #endif
+    #if PPPOE_SUPPORT
+                /* PPPoE packet? */
+            case ETHTYPE_PPPOEDISC:
+            case ETHTYPE_PPPOE:
+    #endif /* PPPOE_SUPPORT */
+                /* full packet send to tcpip_thread to process */
+                if (netif->input(p, netif) != ERR_OK) {
+                    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n"));
+                    pbuf_free(p);
+                    p = NULL;
+                }
+                break;
+
+            default:
+                pbuf_free(p);
+                p = NULL;
+                break;
+        }
+    }
 
     return 1;
 }
@@ -283,15 +283,15 @@ s32_t xemacpsif_input(struct netif *netif)
 #if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
 void vTimerCallback( TimerHandle_t pxTimer )
 {
-	/* Do something if the pxTimer parameter is NULL */
+    /* Do something if the pxTimer parameter is NULL */
     configASSERT(pxTimer);
 
     lExpireCounter++;
-	/* If the timer has expired 100 times then reset RX */
+    /* If the timer has expired 100 times then reset RX */
     if(lExpireCounter >= RESETRXTIMEOUT) {
-	    lExpireCounter = 0;
-	    xemacpsif_resetrx_on_no_rxdata(NetIf);
-	}
+        lExpireCounter = 0;
+        xemacpsif_resetrx_on_no_rxdata(NetIf);
+    }
 }
  #endif
 
@@ -308,15 +308,15 @@ static err_t low_level_init(struct netif *netif)
 
     xemacpsif = mem_malloc(sizeof *xemacpsif);
     if (xemacpsif == NULL) {
-	    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
-	    return ERR_MEM;
-	}
+        LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+        return ERR_MEM;
+    }
 
     xemac = mem_malloc(sizeof *xemac);
     if (xemac == NULL) {
-	    LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
-	    return ERR_MEM;
-	}
+        LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+        return ERR_MEM;
+    }
 
     xemac->state = (void *)xemacpsif;
     xemac->topology_index = xtopology_find_index(mac_address);
@@ -325,9 +325,9 @@ static err_t low_level_init(struct netif *netif)
     xemacpsif->send_q = NULL;
     xemacpsif->recv_q = pq_create_queue();
     if (!xemacpsif->recv_q)
-	    return ERR_MEM;
+        return ERR_MEM;
 
-	/* maximum transfer unit */
+    /* maximum transfer unit */
 #ifdef ZYNQMP_USE_JUMBO
     netif->mtu = XEMACPS_MTU_JUMBO - XEMACPS_HDR_SIZE;
 #else
@@ -343,7 +343,7 @@ static err_t low_level_init(struct netif *netif)
 #endif
 
     netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
-										    NETIF_FLAG_LINK_UP;
+                                            NETIF_FLAG_LINK_UP;
 
 #if LWIP_IPV6 && LWIP_IPV6_MLD
     netif->flags |= NETIF_FLAG_MLD6;
@@ -356,52 +356,52 @@ static err_t low_level_init(struct netif *netif)
 #if 0
     sys_sem_new(&xemac->sem_rx_data_available, 0);
 #endif
-	/* obtain config of this emac */
+    /* obtain config of this emac */
     mac_config = (XEmacPs_Config *)xemacps_lookup_config((unsigned)(UINTPTR)netif->state);
 
 #if EL1_NONSECURE
-	/* Request device to indicate that this library is using it */
+    /* Request device to indicate that this library is using it */
     if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
-	    Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_0, 1, 0, 100, 1, 0, 0);
-	}
+        Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_0, 1, 0, 100, 1, 0, 0);
+    }
     if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
-	    Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_1, 1, 0, 100, 1, 0, 0);
-	}
+        Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_1, 1, 0, 100, 1, 0, 0);
+    }
 #endif
 
     status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
-					    mac_config->BaseAddress);
+                        mac_config->BaseAddress);
     if (status != XST_SUCCESS) {
-	    xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
-	}
+        xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+    }
 
-	/* initialize the mac */
+    /* initialize the mac */
     init_emacps(xemacpsif, netif);
 
     dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-													    XEMACPS_DMACR_OFFSET);
+                                                        XEMACPS_DMACR_OFFSET);
     dmacrreg = dmacrreg | (0x00000010);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-										    XEMACPS_DMACR_OFFSET, dmacrreg);
+                                            XEMACPS_DMACR_OFFSET, dmacrreg);
 
 #if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
-	/* Freertos tick is 10ms by default; set period to the same */
+    /* Freertos tick is 10ms by default; set period to the same */
     xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);
     if (xemac->xTimer == NULL) {
-	    xil_printf("In %s:Timer creation failed....\r\n", __func__);
-	} else {
-	    if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
-		    xil_printf("In %s:Timer start failed....\r\n", __func__);
-		}
-	}
+        xil_printf("In %s:Timer creation failed....\r\n", __func__);
+    } else {
+        if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
+            xil_printf("In %s:Timer start failed....\r\n", __func__);
+        }
+    }
 #endif
     setup_isr(xemac);
     init_dma(xemac);
     start_emacps(xemacpsif);
 
-	/* replace the state in netif (currently the emac baseaddress)
-	 * with the mac instance pointer.
-	 */
+    /* replace the state in netif (currently the emac baseaddress)
+     * with the mac instance pointer.
+     */
     netif->state = (void *)xemac;
 
     return ERR_OK;
@@ -419,17 +419,17 @@ void HandleEmacPsError(struct xemac_s *xemac)
     xemacpsif = (xemacpsif_s *)(xemac->state);
     free_txrx_pbufs(xemacpsif);
     status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
-					    mac_config->BaseAddress);
+                        mac_config->BaseAddress);
     if (status != XST_SUCCESS) {
-	    xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
-	}
-	/* initialize the mac */
+        xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+    }
+    /* initialize the mac */
     init_emacps_on_error(xemacpsif, NetIf);
     dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-													    XEMACPS_DMACR_OFFSET);
+                                                        XEMACPS_DMACR_OFFSET);
     dmacrreg = dmacrreg | (0x01000000);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-										    XEMACPS_DMACR_OFFSET, dmacrreg);
+                                            XEMACPS_DMACR_OFFSET, dmacrreg);
     setup_isr(xemac);
     init_dma(xemac);
     start_emacps(xemacpsif);
@@ -446,18 +446,18 @@ void HandleTxErrors(struct xemac_s *xemac)
     SYS_ARCH_PROTECT(lev);
     xemacpsif = (xemacpsif_s *)(xemac->state);
     netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-											    XEMACPS_NWCTRL_OFFSET);
+                                                XEMACPS_NWCTRL_OFFSET);
     netctrlreg = netctrlreg & (~XEMACPS_NWCTRL_TXEN_MASK);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-								    XEMACPS_NWCTRL_OFFSET, netctrlreg);
+                                    XEMACPS_NWCTRL_OFFSET, netctrlreg);
     free_onlytx_pbufs(xemacpsif);
 
     clean_dma_txdescs(xemac);
     netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-												    XEMACPS_NWCTRL_OFFSET);
+                                                    XEMACPS_NWCTRL_OFFSET);
     netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-									    XEMACPS_NWCTRL_OFFSET, netctrlreg);
+                                        XEMACPS_NWCTRL_OFFSET, netctrlreg);
     SYS_ARCH_UNPROTECT(lev);
 }
 
@@ -470,15 +470,15 @@ static u8_t xemacpsif_ip6_addr_ismulticast(ip6_addr_t* ip_addr)
            ip6_addr_ismulticast_sitelocal(ip_addr) ||
            ip6_addr_ismulticast_orglocal(ip_addr)  ||
            ip6_addr_ismulticast_global(ip_addr)) {
-	/*Return TRUE if IPv6 is Multicast type*/
+    /*Return TRUE if IPv6 is Multicast type*/
     return TRUE;
-	} else {
+    } else {
     return FALSE;
-	}
+    }
 }
 
 static void xemacpsif_mld6_mac_hash_update (struct netif *netif, u8_t *ip_addr,
-	    u8_t action)
+        u8_t action)
 {
     u8_t multicast_mac_addr[6];
     struct xemac_s *xemac = (struct xemac_s *) (netif->state);
@@ -493,99 +493,99 @@ static void xemacpsif_mld6_mac_hash_update (struct netif *netif, u8_t *ip_addr,
     multicast_mac_addr[4] = ip_addr[14];
     multicast_mac_addr[5] = ip_addr[15];
 
-	/* Wait till all sent packets are acknowledged from HW */
+    /* Wait till all sent packets are acknowledged from HW */
     while(txring->HwCnt);
 
     SYS_ARCH_DECL_PROTECT(lev);
 
     SYS_ARCH_PROTECT(lev);
 
-	/* Stop Ethernet */
+    /* Stop Ethernet */
     XEmacPs_Stop(&xemacpsif->emacps);
 
     if (action == NETIF_ADD_MAC_FILTER) {
-		/* Set Mulitcast mac address in hash table */
-	    XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+        /* Set Mulitcast mac address in hash table */
+        XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
 
-	} else if (action == NETIF_DEL_MAC_FILTER) {
-		/* Remove Mulitcast mac address in hash table */
-	    XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
-	}
+    } else if (action == NETIF_DEL_MAC_FILTER) {
+        /* Remove Mulitcast mac address in hash table */
+        XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+    }
 
-	/* Reset DMA */
+    /* Reset DMA */
     reset_dma(xemac);
 
-	/* Start Ethernet */
+    /* Start Ethernet */
     XEmacPs_Start(&xemacpsif->emacps);
 
     SYS_ARCH_UNPROTECT(lev);
 }
 
 static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif, ip_addr_t *group,
-	    u8_t action)
+        u8_t action)
 {
     u8_t temp_mask;
     unsigned int i;
     u8_t * ip_addr = (u8_t *) group;
 
     if(!(xemacpsif_ip6_addr_ismulticast((ip6_addr_t*) ip_addr))) {
-	    LWIP_DEBUGF(NETIF_DEBUG,
-                                ("%s: The requested MAC address is not a multicast address.\r\n", __func__));								 LWIP_DEBUGF(NETIF_DEBUG,
-		                ("Multicast address add operation failure !!\r\n"));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                                ("%s: The requested MAC address is not a multicast address.\r\n", __func__));                                 LWIP_DEBUGF(NETIF_DEBUG,
+                        ("Multicast address add operation failure !!\r\n"));
                         return ERR_ARG;
-	}
+    }
     if (action == NETIF_ADD_MAC_FILTER) {
-	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-		    temp_mask = (0x01) << i;
-		    if ((xemacps_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
-			    continue;
-			}
-		    xemacps_mld6_mcast_entry_mask |= temp_mask;
-
-			/* Update mac address in hash table */
-		    xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
-
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: Multicast MAC address successfully added.\r\n", __func__));
-
-		    return ERR_OK;
-		}
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("%s: No multicast address registers left.\r\n", __func__));
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("Multicast MAC address add operation failure !!\r\n"));
-	    return ERR_MEM;
-	} else if (action == NETIF_DEL_MAC_FILTER) {
-	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-		    temp_mask = (0x01) << i;
-		    if ((xemacps_mld6_mcast_entry_mask & temp_mask) != temp_mask) {
-			    continue;
-			}
-		    xemacps_mld6_mcast_entry_mask &= (~temp_mask);
-
-			/* Update mac address in hash table */
-		    xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
-
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: Multicast MAC address successfully removed.\r\n", __func__));
-
-		    return ERR_OK;
-		}
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("%s: No multicast address registers present with\r\n", __func__));
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("the requested Multicast MAC address.\r\n"));
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("Multicast MAC address removal failure!!.\r\n"));
-	    return ERR_MEM;
-	}
+        for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+            temp_mask = (0x01) << i;
+            if ((xemacps_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
+                continue;
+            }
+            xemacps_mld6_mcast_entry_mask |= temp_mask;
+
+            /* Update mac address in hash table */
+            xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: Multicast MAC address successfully added.\r\n", __func__));
+
+            return ERR_OK;
+        }
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("%s: No multicast address registers left.\r\n", __func__));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("Multicast MAC address add operation failure !!\r\n"));
+        return ERR_MEM;
+    } else if (action == NETIF_DEL_MAC_FILTER) {
+        for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+            temp_mask = (0x01) << i;
+            if ((xemacps_mld6_mcast_entry_mask & temp_mask) != temp_mask) {
+                continue;
+            }
+            xemacps_mld6_mcast_entry_mask &= (~temp_mask);
+
+            /* Update mac address in hash table */
+            xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: Multicast MAC address successfully removed.\r\n", __func__));
+
+            return ERR_OK;
+        }
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("%s: No multicast address registers present with\r\n", __func__));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("the requested Multicast MAC address.\r\n"));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("Multicast MAC address removal failure!!.\r\n"));
+        return ERR_MEM;
+    }
     return ERR_ARG;
 }
 #endif
 
 #if LWIP_IGMP
 static void xemacpsif_mac_hash_update (struct netif *netif, u8_t *ip_addr,
-	    u8_t action)
+        u8_t action)
 {
     u8_t multicast_mac_addr[6];
     struct xemac_s *xemac = (struct xemac_s *) (netif->state);
@@ -600,102 +600,102 @@ static void xemacpsif_mac_hash_update (struct netif *netif, u8_t *ip_addr,
     multicast_mac_addr[4] = ip_addr[2];
     multicast_mac_addr[5] = ip_addr[3];
 
-	/* Wait till all sent packets are acknowledged from HW */
+    /* Wait till all sent packets are acknowledged from HW */
     while(txring->HwCnt);
 
     SYS_ARCH_DECL_PROTECT(lev);
 
     SYS_ARCH_PROTECT(lev);
 
-	/* Stop Ethernet */
+    /* Stop Ethernet */
     XEmacPs_Stop(&xemacpsif->emacps);
 
     if (action == IGMP_ADD_MAC_FILTER) {
-		/* Set Mulitcast mac address in hash table */
-	    XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+        /* Set Mulitcast mac address in hash table */
+        XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
 
-	} else if (action == IGMP_DEL_MAC_FILTER) {
-		/* Remove Mulitcast mac address in hash table */
-	    XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
-	}
+    } else if (action == IGMP_DEL_MAC_FILTER) {
+        /* Remove Mulitcast mac address in hash table */
+        XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+    }
 
-	/* Reset DMA */
+    /* Reset DMA */
     reset_dma(xemac);
 
-	/* Start Ethernet */
+    /* Start Ethernet */
     XEmacPs_Start(&xemacpsif->emacps);
 
     SYS_ARCH_UNPROTECT(lev);
 }
 
 static err_t xemacpsif_mac_filter_update (struct netif *netif, ip_addr_t *group,
-	    u8_t action)
+        u8_t action)
 {
     u8_t temp_mask;
     unsigned int i;
     u8_t * ip_addr = (u8_t *) group;
 
     if ((ip_addr[0] < 224) && (ip_addr[0] > 239)) {
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("%s: The requested MAC address is not a multicast address.\r\n", __func__));
-	    LWIP_DEBUGF(NETIF_DEBUG,
-				("Multicast address add operation failure !!\r\n"));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("%s: The requested MAC address is not a multicast address.\r\n", __func__));
+        LWIP_DEBUGF(NETIF_DEBUG,
+                ("Multicast address add operation failure !!\r\n"));
 
-	    return ERR_ARG;
-	}
+        return ERR_ARG;
+    }
 
     if (action == IGMP_ADD_MAC_FILTER) {
 
-	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-		    temp_mask = (0x01) << i;
-		    if ((xemacps_mcast_entry_mask & temp_mask) == temp_mask) {
-			    continue;
-			}
-		    xemacps_mcast_entry_mask |= temp_mask;
-
-			/* Update mac address in hash table */
-		    xemacpsif_mac_hash_update(netif, ip_addr, action);
-
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: Multicast MAC address successfully added.\r\n", __func__));
-
-		    return ERR_OK;
-		}
-	    if (i == XEMACPS_MAX_MAC_ADDR) {
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: No multicast address registers left.\r\n", __func__));
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("Multicast MAC address add operation failure !!\r\n"));
-
-		    return ERR_MEM;
-		}
-	} else if (action == IGMP_DEL_MAC_FILTER) {
-	    for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
-		    temp_mask = (0x01) << i;
-		    if ((xemacps_mcast_entry_mask & temp_mask) != temp_mask) {
-			    continue;
-			}
-		    xemacps_mcast_entry_mask &= (~temp_mask);
-
-			/* Update mac address in hash table */
-		    xemacpsif_mac_hash_update(netif, ip_addr, action);
-
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: Multicast MAC address successfully removed.\r\n", __func__));
-
-		    return ERR_OK;
-		}
-	    if (i == XEMACPS_MAX_MAC_ADDR) {
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("%s: No multicast address registers present with\r\n", __func__));
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("the requested Multicast MAC address.\r\n"));
-		    LWIP_DEBUGF(NETIF_DEBUG,
-					("Multicast MAC address removal failure!!.\r\n"));
-
-		    return ERR_MEM;
-		}
-	}
+        for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+            temp_mask = (0x01) << i;
+            if ((xemacps_mcast_entry_mask & temp_mask) == temp_mask) {
+                continue;
+            }
+            xemacps_mcast_entry_mask |= temp_mask;
+
+            /* Update mac address in hash table */
+            xemacpsif_mac_hash_update(netif, ip_addr, action);
+
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: Multicast MAC address successfully added.\r\n", __func__));
+
+            return ERR_OK;
+        }
+        if (i == XEMACPS_MAX_MAC_ADDR) {
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: No multicast address registers left.\r\n", __func__));
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("Multicast MAC address add operation failure !!\r\n"));
+
+            return ERR_MEM;
+        }
+    } else if (action == IGMP_DEL_MAC_FILTER) {
+        for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+            temp_mask = (0x01) << i;
+            if ((xemacps_mcast_entry_mask & temp_mask) != temp_mask) {
+                continue;
+            }
+            xemacps_mcast_entry_mask &= (~temp_mask);
+
+            /* Update mac address in hash table */
+            xemacpsif_mac_hash_update(netif, ip_addr, action);
+
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: Multicast MAC address successfully removed.\r\n", __func__));
+
+            return ERR_OK;
+        }
+        if (i == XEMACPS_MAX_MAC_ADDR) {
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("%s: No multicast address registers present with\r\n", __func__));
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("the requested Multicast MAC address.\r\n"));
+            LWIP_DEBUGF(NETIF_DEBUG,
+                    ("Multicast MAC address removal failure!!.\r\n"));
+
+            return ERR_MEM;
+        }
+    }
     return ERR_OK;
 }
 #endif
@@ -712,9 +712,9 @@ static err_t xemacpsif_mac_filter_update (struct netif *netif, ip_addr_t *group,
 err_t xemacpsif_init(struct netif *netif)
 {
 #if LWIP_SNMP
-	/* ifType ethernetCsmacd(6) @see RFC1213 */
+    /* ifType ethernetCsmacd(6) @see RFC1213 */
     netif->link_type = 6;
-	/* your link speed here */
+    /* your link speed here */
     netif->link_speed = ;
     netif->ts = 0;
     netif->ifinoctets = 0;

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_dma.c

@@ -57,7 +57,7 @@
 
 #include <stdio.h>
 
-#define INTC_BASE_ADDR	    XPAR_SCUGIC_0_CPU_BASEADDR
+#define INTC_BASE_ADDR        XPAR_SCUGIC_0_CPU_BASEADDR
 #define INTC_DIST_BASE_ADDR    XPAR_SCUGIC_0_DIST_BASEADDR
 
 /* Byte alignment of BDs */
@@ -122,8 +122,8 @@ static volatile u32_t bd_space_attr_set = 0;
 long xInsideISR = 0;
 #endif
 
-#define XEMACPS_BD_TO_INDEX(ringptr, bdptr)				\
-	(((UINTPTR)bdptr - (UINTPTR)(ringptr)->BaseBdAddr) / (ringptr)->Separation)
+#define XEMACPS_BD_TO_INDEX(ringptr, bdptr)                \
+    (((UINTPTR)bdptr - (UINTPTR)(ringptr)->BaseBdAddr) / (ringptr)->Separation)
 
 
 s32_t is_tx_space_available(xemacpsif_s *emac)
@@ -133,7 +133,7 @@ s32_t is_tx_space_available(xemacpsif_s *emac)
 
     txring = &(XEmacPs_GetTxRing(&emac->emacps));
 
-	/* tx space is available as long as there are valid BD's */
+    /* tx space is available as long as there are valid BD's */
     freecnt = XEmacPs_BdRingGetFreeCnt(txring);
     return freecnt;
 }
@@ -145,23 +145,23 @@ u32_t get_base_index_txpbufsstorage (xemacpsif_s *xemacpsif)
     u32_t index;
 #ifdef XPAR_XEMACPS_0_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-	    index = 0;
-	}
+        index = 0;
+    }
 #endif
 #ifdef XPAR_XEMACPS_1_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) {
-	    index = XLWIP_CONFIG_N_TX_DESC;
-	}
+        index = XLWIP_CONFIG_N_TX_DESC;
+    }
 #endif
 #ifdef XPAR_XEMACPS_2_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) {
-	    index = 2 * XLWIP_CONFIG_N_TX_DESC;
-	}
+        index = 2 * XLWIP_CONFIG_N_TX_DESC;
+    }
 #endif
 #ifdef XPAR_XEMACPS_3_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) {
-	    index = 3 * XLWIP_CONFIG_N_TX_DESC;
-	}
+        index = 3 * XLWIP_CONFIG_N_TX_DESC;
+    }
 #endif
     return index;
 }
@@ -172,23 +172,23 @@ u32_t get_base_index_rxpbufsstorage (xemacpsif_s *xemacpsif)
     u32_t index;
 #ifdef XPAR_XEMACPS_0_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-	    index = 0;
-	}
+        index = 0;
+    }
 #endif
 #ifdef XPAR_XEMACPS_1_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) {
-	    index = XLWIP_CONFIG_N_RX_DESC;
-	}
+        index = XLWIP_CONFIG_N_RX_DESC;
+    }
 #endif
 #ifdef XPAR_XEMACPS_2_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) {
-	    index = 2 * XLWIP_CONFIG_N_RX_DESC;
-	}
+        index = 2 * XLWIP_CONFIG_N_RX_DESC;
+    }
 #endif
 #ifdef XPAR_XEMACPS_3_BASEADDR
     if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) {
-	    index = 3 * XLWIP_CONFIG_N_RX_DESC;
-	}
+        index = 3 * XLWIP_CONFIG_N_RX_DESC;
+    }
 #endif
     return index;
 }
@@ -208,41 +208,41 @@ void process_sent_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *txring)
     index = get_base_index_txpbufsstorage (xemacpsif);
 
     while (1) {
-		/* obtain processed BD's */
-	    n_bds = XEmacPs_BdRingFromHwTx(txring,
-							    XLWIP_CONFIG_N_TX_DESC, &txbdset);
-	    if (n_bds == 0)  {
-		    return;
-		}
-		/* free the processed BD's */
-	    n_pbufs_freed = n_bds;
-	    curbdpntr = txbdset;
-	    while (n_pbufs_freed > 0) {
-		    bdindex = XEMACPS_BD_TO_INDEX(txring, curbdpntr);
-		    temp = (u32 *)curbdpntr;
-			*temp = 0;
-		    temp++;
-		    if (bdindex == (XLWIP_CONFIG_N_TX_DESC - 1)) {
-				*temp = 0xC0000000;
-			} else {
-				*temp = 0x80000000;
-			}
-		    dsb();
-		    p = (struct pbuf *)tx_pbufs_storage[index + bdindex];
-		    if (p != NULL) {
-			    pbuf_free(p);
-			}
-		    tx_pbufs_storage[index + bdindex] = 0;
-		    curbdpntr = XEmacPs_BdRingNext(txring, curbdpntr);
-		    n_pbufs_freed--;
-		    dsb();
-		}
-
-	    status = XEmacPs_BdRingFree(txring, n_bds, txbdset);
-	    if (status != XST_SUCCESS) {
-		    LWIP_DEBUGF(NETIF_DEBUG, ("Failure while freeing in Tx Done ISR\r\n"));
-		}
-	}
+        /* obtain processed BD's */
+        n_bds = XEmacPs_BdRingFromHwTx(txring,
+                                XLWIP_CONFIG_N_TX_DESC, &txbdset);
+        if (n_bds == 0)  {
+            return;
+        }
+        /* free the processed BD's */
+        n_pbufs_freed = n_bds;
+        curbdpntr = txbdset;
+        while (n_pbufs_freed > 0) {
+            bdindex = XEMACPS_BD_TO_INDEX(txring, curbdpntr);
+            temp = (u32 *)curbdpntr;
+            *temp = 0;
+            temp++;
+            if (bdindex == (XLWIP_CONFIG_N_TX_DESC - 1)) {
+                *temp = 0xC0000000;
+            } else {
+                *temp = 0x80000000;
+            }
+            dsb();
+            p = (struct pbuf *)tx_pbufs_storage[index + bdindex];
+            if (p != NULL) {
+                pbuf_free(p);
+            }
+            tx_pbufs_storage[index + bdindex] = 0;
+            curbdpntr = XEmacPs_BdRingNext(txring, curbdpntr);
+            n_pbufs_freed--;
+            dsb();
+        }
+
+        status = XEmacPs_BdRingFree(txring, n_bds, txbdset);
+        if (status != XST_SUCCESS) {
+            LWIP_DEBUGF(NETIF_DEBUG, ("Failure while freeing in Tx Done ISR\r\n"));
+        }
+    }
     return;
 }
 
@@ -261,9 +261,9 @@ void emacps_send_handler(void *arg)
     regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_TXSR_OFFSET);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,XEMACPS_TXSR_OFFSET, regval);
 
-	/* If Transmit done interrupt is asserted, process completed BD's */
-	/* Since RT-Thread does not support freeing memory in interrupts, comment it out */
-	// process_sent_bds(xemacpsif, txringptr);
+    /* If Transmit done interrupt is asserted, process completed BD's */
+    /* Since RT-Thread does not support freeing memory in interrupts, comment it out */
+    // process_sent_bds(xemacpsif, txringptr);
 #ifdef OS_IS_FREERTOS
     xInsideISR--;
 #endif
@@ -289,79 +289,79 @@ XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
 
     index = get_base_index_txpbufsstorage (xemacpsif);
 
-	/* first count the number of pbufs */
+    /* first count the number of pbufs */
     for (q = p, n_pbufs = 0; q != NULL; q = q->next)
-	    n_pbufs++;
+        n_pbufs++;
 
-	/* obtain as many BD's */
+    /* obtain as many BD's */
     status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
     if (status != XST_SUCCESS) {
-	    mtcpsr(lev);
-	    LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
-	    return XST_FAILURE;
-	}
+        mtcpsr(lev);
+        LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
+        return XST_FAILURE;
+    }
 
     for(q = p, txbd = txbdset; q != NULL; q = q->next) {
-	    bdindex = XEMACPS_BD_TO_INDEX(txring, txbd);
-	    if (tx_pbufs_storage[index + bdindex] != 0) {
-		    mtcpsr(lev);
-		    LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
-		    return XST_FAILURE;
-		}
-
-		/* Send the data from the pbuf to the interface, one pbuf at a
-		   time. The size of the data in each pbuf is kept in the ->len
-		   variable. */
-	    if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
-		    Xil_DCacheFlushRange((UINTPTR)q->payload, (UINTPTR)q->len);
-		}
-
-	    XEmacPs_BdSetAddressTx(txbd, (UINTPTR)q->payload);
+        bdindex = XEMACPS_BD_TO_INDEX(txring, txbd);
+        if (tx_pbufs_storage[index + bdindex] != 0) {
+            mtcpsr(lev);
+            LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
+            return XST_FAILURE;
+        }
+
+        /* Send the data from the pbuf to the interface, one pbuf at a
+           time. The size of the data in each pbuf is kept in the ->len
+           variable. */
+        if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+            Xil_DCacheFlushRange((UINTPTR)q->payload, (UINTPTR)q->len);
+        }
+
+        XEmacPs_BdSetAddressTx(txbd, (UINTPTR)q->payload);
 
 #ifdef ZYNQMP_USE_JUMBO
-	    max_fr_size = MAX_FRAME_SIZE_JUMBO - 18;
+        max_fr_size = MAX_FRAME_SIZE_JUMBO - 18;
 #else
-	    max_fr_size = XEMACPS_MAX_FRAME_SIZE - 18;
+        max_fr_size = XEMACPS_MAX_FRAME_SIZE - 18;
 #endif
-	    if (q->len > max_fr_size)
-		    XEmacPs_BdSetLength(txbd, max_fr_size & 0x3FFF);
-	    else
-		    XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
-
-	    tx_pbufs_storage[index + bdindex] = (UINTPTR)q;
-
-	    pbuf_ref(q);
-	    last_txbd = txbd;
-	    XEmacPs_BdClearLast(txbd);
-	    txbd = XEmacPs_BdRingNext(txring, txbd);
-	}
+        if (q->len > max_fr_size)
+            XEmacPs_BdSetLength(txbd, max_fr_size & 0x3FFF);
+        else
+            XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
+
+        tx_pbufs_storage[index + bdindex] = (UINTPTR)q;
+
+        pbuf_ref(q);
+        last_txbd = txbd;
+        XEmacPs_BdClearLast(txbd);
+        txbd = XEmacPs_BdRingNext(txring, txbd);
+    }
     XEmacPs_BdSetLast(last_txbd);
-	/* For fragmented packets, remember the 1st BD allocated for the 1st
-	   packet fragment. The used bit for this BD should be cleared at the end
-	   after clearing out used bits for other fragments. For packets without
-	   just remember the allocated BD. */
+    /* For fragmented packets, remember the 1st BD allocated for the 1st
+       packet fragment. The used bit for this BD should be cleared at the end
+       after clearing out used bits for other fragments. For packets without
+       just remember the allocated BD. */
     temp_txbd = txbdset;
     txbd = txbdset;
     txbd = XEmacPs_BdRingNext(txring, txbd);
     q = p->next;
     for(; q != NULL; q = q->next) {
-	    XEmacPs_BdClearTxUsed(txbd);
-	    dsb();
-	    txbd = XEmacPs_BdRingNext(txring, txbd);
-	}
+        XEmacPs_BdClearTxUsed(txbd);
+        dsb();
+        txbd = XEmacPs_BdRingNext(txring, txbd);
+    }
     XEmacPs_BdClearTxUsed(temp_txbd);
     dsb();
 
     status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
     if (status != XST_SUCCESS) {
-	    mtcpsr(lev);
-	    LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
-	    return XST_FAILURE;
-	}
-	/* Start transmit */
+        mtcpsr(lev);
+        LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
+        return XST_FAILURE;
+    }
+    /* Start transmit */
     XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
     XEMACPS_NWCTRL_OFFSET,
-	(XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
+    (XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
     XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
 
     mtcpsr(lev);
@@ -382,63 +382,63 @@ void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring)
 
     freebds = XEmacPs_BdRingGetFreeCnt (rxring);
     while (freebds > 0) {
-	    freebds--;
+        freebds--;
 #ifdef ZYNQMP_USE_JUMBO
-	    p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
+        p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
 #else
-	    p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
+        p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
 #endif
-	    if (!p) {
+        if (!p) {
 #if LINK_STATS
-		    lwip_stats.link.memerr++;
-		    lwip_stats.link.drop++;
+            lwip_stats.link.memerr++;
+            lwip_stats.link.drop++;
 #endif
-		    rt_kprintf("unable to alloc pbuf in recv_handler\r\n");
-		    return;
-		}
-	    status = XEmacPs_BdRingAlloc(rxring, 1, &rxbd);
-	    if (status != XST_SUCCESS) {
-		    LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n"));
-		    pbuf_free(p);
-		    return;
-		}
-	    status = XEmacPs_BdRingToHw(rxring, 1, rxbd);
-	    if (status != XST_SUCCESS) {
-		    LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware: "));
-		    if (status == XST_DMA_SG_LIST_ERROR) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with XEmacPs_BdRingAlloc()\r\n"));
-			}
-		    else {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"));
-			}
-
-		    pbuf_free(p);
-		    XEmacPs_BdRingUnAlloc(rxring, 1, rxbd);
-		    return;
-		}
+            rt_kprintf("unable to alloc pbuf in recv_handler\r\n");
+            return;
+        }
+        status = XEmacPs_BdRingAlloc(rxring, 1, &rxbd);
+        if (status != XST_SUCCESS) {
+            LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n"));
+            pbuf_free(p);
+            return;
+        }
+        status = XEmacPs_BdRingToHw(rxring, 1, rxbd);
+        if (status != XST_SUCCESS) {
+            LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware: "));
+            if (status == XST_DMA_SG_LIST_ERROR) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with XEmacPs_BdRingAlloc()\r\n"));
+            }
+            else {
+                LWIP_DEBUGF(NETIF_DEBUG, ("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"));
+            }
+
+            pbuf_free(p);
+            XEmacPs_BdRingUnAlloc(rxring, 1, rxbd);
+            return;
+        }
 #ifdef ZYNQMP_USE_JUMBO
-	    if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
-		    Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
-		}
+        if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+            Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+        }
 #else
-	    if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
-		    Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
-		}
+        if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+            Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+        }
 #endif
-	    bdindex = XEMACPS_BD_TO_INDEX(rxring, rxbd);
-	    temp = (u32 *)rxbd;
-	    if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
-			*temp = 0x00000002;
-		} else {
-			*temp = 0;
-		}
-	    temp++;
-		*temp = 0;
-	    dsb();
-
-	    XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
-	    rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
-	}
+        bdindex = XEMACPS_BD_TO_INDEX(rxring, rxbd);
+        temp = (u32 *)rxbd;
+        if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
+            *temp = 0x00000002;
+        } else {
+            *temp = 0;
+        }
+        temp++;
+        *temp = 0;
+        dsb();
+
+        XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
+        rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
+    }
 }
 
 void emacps_recv_handler(void *arg)
@@ -465,60 +465,60 @@ void emacps_recv_handler(void *arg)
 
     gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
     index = get_base_index_rxpbufsstorage (xemacpsif);
-	/*
-	 * If Reception done interrupt is asserted, call RX call back function
-	 * to handle the processed BDs and then raise the according flag.
-	 */
+    /*
+     * If Reception done interrupt is asserted, call RX call back function
+     * to handle the processed BDs and then raise the according flag.
+     */
     regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET);
     XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET, regval);
     if (gigeversion <= 2) {
-		    resetrx_on_no_rxdata(xemacpsif);
-	}
+            resetrx_on_no_rxdata(xemacpsif);
+    }
 
     while(1) {
 
-	    bd_processed = XEmacPs_BdRingFromHwRx(rxring, XLWIP_CONFIG_N_RX_DESC, &rxbdset);
-	    if (bd_processed <= 0) {
-		    break;
-		}
-	    for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
-
-		    bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
-		    p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
-			/*
-			 * Adjust the buffer size to the actual number of bytes received.
-			 */
+        bd_processed = XEmacPs_BdRingFromHwRx(rxring, XLWIP_CONFIG_N_RX_DESC, &rxbdset);
+        if (bd_processed <= 0) {
+            break;
+        }
+        for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
+
+            bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
+            p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
+            /*
+             * Adjust the buffer size to the actual number of bytes received.
+             */
 #ifdef ZYNQMP_USE_JUMBO
-		    rx_bytes = XEmacPs_GetRxFrameSize(&xemacpsif->emacps, curbdptr);
+            rx_bytes = XEmacPs_GetRxFrameSize(&xemacpsif->emacps, curbdptr);
 #else
-		    rx_bytes = XEmacPs_BdGetLength(curbdptr);
+            rx_bytes = XEmacPs_BdGetLength(curbdptr);
 #endif
-		    pbuf_realloc(p, rx_bytes);
-			/* Invalidate RX frame before queuing to handle
-			 * L1 cache prefetch conditions on any architecture.
-			 */
-		    Xil_DCacheInvalidateRange((UINTPTR)p->payload, rx_bytes);
-			/* store it in the receive queue,
-			 * where it'll be processed by a different handler
-			 */
-		    if (pq_enqueue(xemacpsif->recv_q, (void*)p) < 0) {
+            pbuf_realloc(p, rx_bytes);
+            /* Invalidate RX frame before queuing to handle
+             * L1 cache prefetch conditions on any architecture.
+             */
+            Xil_DCacheInvalidateRange((UINTPTR)p->payload, rx_bytes);
+            /* store it in the receive queue,
+             * where it'll be processed by a different handler
+             */
+            if (pq_enqueue(xemacpsif->recv_q, (void*)p) < 0) {
 #if LINK_STATS
-			    lwip_stats.link.memerr++;
-			    lwip_stats.link.drop++;
+                lwip_stats.link.memerr++;
+                lwip_stats.link.drop++;
 #endif
-			    pbuf_free(p);
-			}
-		    curbdptr = XEmacPs_BdRingNext( rxring, curbdptr);
-		}
-		/* free up the BD's */
-	    XEmacPs_BdRingFree(rxring, bd_processed, rxbdset);
-	    setup_rx_bds(xemacpsif, rxring);
+                pbuf_free(p);
+            }
+            curbdptr = XEmacPs_BdRingNext( rxring, curbdptr);
+        }
+        /* free up the BD's */
+        XEmacPs_BdRingFree(rxring, bd_processed, rxbdset);
+        setup_rx_bds(xemacpsif, rxring);
 #if 0
-	    sys_sem_signal(&xemac->sem_rx_data_available);
+        sys_sem_signal(&xemac->sem_rx_data_available);
 #else
-	    eth_device_ready(xemac->rt_eth_device);
+        eth_device_ready(xemac->rt_eth_device);
 #endif
-	}
+    }
 
 #ifdef OS_IS_FREERTOS
     xInsideISR--;
@@ -537,12 +537,12 @@ void clean_dma_txdescs(struct xemac_s *xemac)
     XEmacPs_BdClear(&bdtemplate);
     XEmacPs_BdSetStatus(&bdtemplate, XEMACPS_TXBUF_USED_MASK);
 
-	/*
-	 * Create the TxBD ring
-	 */
+    /*
+     * Create the TxBD ring
+     */
     XEmacPs_BdRingCreate(txringptr, (UINTPTR) xemacpsif->tx_bdspace,
-			(UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
-				 XLWIP_CONFIG_N_TX_DESC);
+            (UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
+                 XLWIP_CONFIG_N_TX_DESC);
     XEmacPs_BdRingClone(txringptr, &bdtemplate, XEMACPS_SEND);
 }
 
@@ -567,13 +567,13 @@ XStatus init_dma(struct xemac_s *xemac)
 
     index = get_base_index_rxpbufsstorage (xemacpsif);
     gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
-	/*
-	 * The BDs need to be allocated in uncached memory. Hence the 1 MB
-	 * address range allocated for Bd_Space is made uncached
-	 * by setting appropriate attributes in the translation table.
-	 * The Bd_Space is aligned to 1MB and has a size of 1 MB. This ensures
-	 * a reserved uncached area used only for BDs.
-	 */
+    /*
+     * The BDs need to be allocated in uncached memory. Hence the 1 MB
+     * address range allocated for Bd_Space is made uncached
+     * by setting appropriate attributes in the translation table.
+     * The Bd_Space is aligned to 1MB and has a size of 1 MB. This ensures
+     * a reserved uncached area used only for BDs.
+     */
     if (bd_space_attr_set == 0) {
 #if defined (ARMR5)
     Xil_SetTlbAttributes((s32_t)bd_space, STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); // addr, attr
@@ -584,15 +584,15 @@ XStatus init_dma(struct xemac_s *xemac)
     Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr
 #endif
 #endif
-	    bd_space_attr_set = 1;
-	}
+        bd_space_attr_set = 1;
+    }
 
     rxringptr = &XEmacPs_GetRxRing(&xemacpsif->emacps);
     txringptr = &XEmacPs_GetTxRing(&xemacpsif->emacps);
     LWIP_DEBUGF(NETIF_DEBUG, ("rxringptr: 0x%08x\r\n", rxringptr));
     LWIP_DEBUGF(NETIF_DEBUG, ("txringptr: 0x%08x\r\n", txringptr));
 
-	/* Allocate 64k for Rx and Tx bds each to take care of extreme cases */
+    /* Allocate 64k for Rx and Tx bds each to take care of extreme cases */
     tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
     xemacpsif->rx_bdspace = (void *)tempaddress;
     bd_space_index += 0x10000;
@@ -600,163 +600,163 @@ XStatus init_dma(struct xemac_s *xemac)
     xemacpsif->tx_bdspace = (void *)tempaddress;
     bd_space_index += 0x10000;
     if (gigeversion > 2) {
-	    tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
-	    bdrxterminate = (XEmacPs_Bd *)tempaddress;
-	    bd_space_index += 0x10000;
-	    tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
-	    bdtxterminate = (XEmacPs_Bd *)tempaddress;
-	    bd_space_index += 0x10000;
-	}
+        tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+        bdrxterminate = (XEmacPs_Bd *)tempaddress;
+        bd_space_index += 0x10000;
+        tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+        bdtxterminate = (XEmacPs_Bd *)tempaddress;
+        bd_space_index += 0x10000;
+    }
 
     LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: %p \r\n", xemacpsif->rx_bdspace));
     LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: %p \r\n", xemacpsif->tx_bdspace));
 
     if (!xemacpsif->rx_bdspace || !xemacpsif->tx_bdspace) {
-	    xil_printf("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors",
-			    __FILE__, __LINE__);
-	    return ERR_IF;
-	}
-
-	/*
-	 * Setup RxBD space.
-	 *
-	 * Setup a BD template for the Rx channel. This template will be copied to
-	 * every RxBD. We will not have to explicitly set these again.
-	 */
+        xil_printf("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors",
+                __FILE__, __LINE__);
+        return ERR_IF;
+    }
+
+    /*
+     * Setup RxBD space.
+     *
+     * Setup a BD template for the Rx channel. This template will be copied to
+     * every RxBD. We will not have to explicitly set these again.
+     */
     XEmacPs_BdClear(&bdtemplate);
 
-	/*
-	 * Create the RxBD ring
-	 */
+    /*
+     * Create the RxBD ring
+     */
 
     status = XEmacPs_BdRingCreate(rxringptr, (UINTPTR) xemacpsif->rx_bdspace,
-				(UINTPTR) xemacpsif->rx_bdspace, BD_ALIGNMENT,
-				     XLWIP_CONFIG_N_RX_DESC);
+                (UINTPTR) xemacpsif->rx_bdspace, BD_ALIGNMENT,
+                     XLWIP_CONFIG_N_RX_DESC);
 
     if (status != XST_SUCCESS) {
-	    LWIP_DEBUGF(NETIF_DEBUG, ("Error setting up RxBD space\r\n"));
-	    return ERR_IF;
-	}
+        LWIP_DEBUGF(NETIF_DEBUG, ("Error setting up RxBD space\r\n"));
+        return ERR_IF;
+    }
 
     status = XEmacPs_BdRingClone(rxringptr, &bdtemplate, XEMACPS_RECV);
     if (status != XST_SUCCESS) {
-	    LWIP_DEBUGF(NETIF_DEBUG, ("Error initializing RxBD space\r\n"));
-	    return ERR_IF;
-	}
+        LWIP_DEBUGF(NETIF_DEBUG, ("Error initializing RxBD space\r\n"));
+        return ERR_IF;
+    }
 
     XEmacPs_BdClear(&bdtemplate);
     XEmacPs_BdSetStatus(&bdtemplate, XEMACPS_TXBUF_USED_MASK);
-	/*
-	 * Create the TxBD ring
-	 */
+    /*
+     * Create the TxBD ring
+     */
     status = XEmacPs_BdRingCreate(txringptr, (UINTPTR) xemacpsif->tx_bdspace,
-				(UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
-				     XLWIP_CONFIG_N_TX_DESC);
+                (UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
+                     XLWIP_CONFIG_N_TX_DESC);
 
     if (status != XST_SUCCESS) {
-	    return ERR_IF;
-	}
+        return ERR_IF;
+    }
 
-	/* We reuse the bd template, as the same one will work for both rx and tx. */
+    /* We reuse the bd template, as the same one will work for both rx and tx. */
     status = XEmacPs_BdRingClone(txringptr, &bdtemplate, XEMACPS_SEND);
     if (status != XST_SUCCESS) {
-	    return ERR_IF;
-	}
+        return ERR_IF;
+    }
 
-	/*
-	 * Allocate RX descriptors, 1 RxBD at a time.
-	 */
+    /*
+     * Allocate RX descriptors, 1 RxBD at a time.
+     */
     for (i = 0; i < XLWIP_CONFIG_N_RX_DESC; i++) {
 #ifdef ZYNQMP_USE_JUMBO
-	    p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
+        p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
 #else
-	    p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
+        p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
 #endif
-	    if (!p) {
+        if (!p) {
 #if LINK_STATS
-		    lwip_stats.link.memerr++;
-		    lwip_stats.link.drop++;
+            lwip_stats.link.memerr++;
+            lwip_stats.link.drop++;
 #endif
-		    rt_kprintf("unable to alloc pbuf in init_dma\r\n");
-		    return ERR_IF;
-		}
-	    status = XEmacPs_BdRingAlloc(rxringptr, 1, &rxbd);
-	    if (status != XST_SUCCESS) {
-		    LWIP_DEBUGF(NETIF_DEBUG, ("init_dma: Error allocating RxBD\r\n"));
-		    pbuf_free(p);
-		    return ERR_IF;
-		}
-		/* Enqueue to HW */
-	    status = XEmacPs_BdRingToHw(rxringptr, 1, rxbd);
-	    if (status != XST_SUCCESS) {
-		    LWIP_DEBUGF(NETIF_DEBUG, ("Error: committing RxBD to HW\r\n"));
-		    pbuf_free(p);
-		    XEmacPs_BdRingUnAlloc(rxringptr, 1, rxbd);
-		    return ERR_IF;
-		}
-
-	    bdindex = XEMACPS_BD_TO_INDEX(rxringptr, rxbd);
-	    temp = (u32 *)rxbd;
-		*temp = 0;
-	    if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
-			*temp = 0x00000002;
-		}
-	    temp++;
-		*temp = 0;
-	    dsb();
+            rt_kprintf("unable to alloc pbuf in init_dma\r\n");
+            return ERR_IF;
+        }
+        status = XEmacPs_BdRingAlloc(rxringptr, 1, &rxbd);
+        if (status != XST_SUCCESS) {
+            LWIP_DEBUGF(NETIF_DEBUG, ("init_dma: Error allocating RxBD\r\n"));
+            pbuf_free(p);
+            return ERR_IF;
+        }
+        /* Enqueue to HW */
+        status = XEmacPs_BdRingToHw(rxringptr, 1, rxbd);
+        if (status != XST_SUCCESS) {
+            LWIP_DEBUGF(NETIF_DEBUG, ("Error: committing RxBD to HW\r\n"));
+            pbuf_free(p);
+            XEmacPs_BdRingUnAlloc(rxringptr, 1, rxbd);
+            return ERR_IF;
+        }
+
+        bdindex = XEMACPS_BD_TO_INDEX(rxringptr, rxbd);
+        temp = (u32 *)rxbd;
+        *temp = 0;
+        if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
+            *temp = 0x00000002;
+        }
+        temp++;
+        *temp = 0;
+        dsb();
 #ifdef ZYNQMP_USE_JUMBO
-	    if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
-		    Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
-		}
+        if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+            Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+        }
 #else
-	    if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
-		    Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
-		}
+        if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+            Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+        }
 #endif
-	    XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
+        XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
 
-	    rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
-	}
+        rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
+    }
     XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
     if (gigeversion > 2) {
-	    XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 1, XEMACPS_SEND);
-	}else {
-	    XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 0, XEMACPS_SEND);
-	}
+        XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 1, XEMACPS_SEND);
+    }else {
+        XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 0, XEMACPS_SEND);
+    }
     if (gigeversion > 2)
-	{
-		/*
-		 * This version of GEM supports priority queuing and the current
-		 * driver is using tx priority queue 1 and normal rx queue for
-		 * packet transmit and receive. The below code ensure that the
-		 * other queue pointers are parked to known state for avoiding
-		 * the controller to malfunction by fetching the descriptors
-		 * from these queues.
-		 */
-	    XEmacPs_BdClear(bdrxterminate);
-	    XEmacPs_BdSetAddressRx(bdrxterminate, (XEMACPS_RXBUF_NEW_MASK |
-					    XEMACPS_RXBUF_WRAP_MASK));
-	    XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_RXQ1BASE_OFFSET),
-				   (UINTPTR)bdrxterminate);
-	    XEmacPs_BdClear(bdtxterminate);
-	    XEmacPs_BdSetStatus(bdtxterminate, (XEMACPS_TXBUF_USED_MASK |
-					    XEMACPS_TXBUF_WRAP_MASK));
-	    XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
-				   (UINTPTR)bdtxterminate);
-	}
-
-	/*
-	 * Connect the device driver handler that will be called when an
-	 * interrupt for the device occurs, the handler defined above performs
-	 * the specific interrupt processing for the device.
-	 */
-	// XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr,
-	// 			(Xil_ExceptionHandler)XEmacPs_IntrHandler,
-	// 					(void *)&xemacpsif->emacps);
-	/*
-	 * Enable the interrupt for emacps.
-	 */
-	// XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, (u32) xtopologyp->scugic_emac_intr);
+    {
+        /*
+         * This version of GEM supports priority queuing and the current
+         * driver is using tx priority queue 1 and normal rx queue for
+         * packet transmit and receive. The below code ensure that the
+         * other queue pointers are parked to known state for avoiding
+         * the controller to malfunction by fetching the descriptors
+         * from these queues.
+         */
+        XEmacPs_BdClear(bdrxterminate);
+        XEmacPs_BdSetAddressRx(bdrxterminate, (XEMACPS_RXBUF_NEW_MASK |
+                        XEMACPS_RXBUF_WRAP_MASK));
+        XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_RXQ1BASE_OFFSET),
+                   (UINTPTR)bdrxterminate);
+        XEmacPs_BdClear(bdtxterminate);
+        XEmacPs_BdSetStatus(bdtxterminate, (XEMACPS_TXBUF_USED_MASK |
+                        XEMACPS_TXBUF_WRAP_MASK));
+        XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
+                   (UINTPTR)bdtxterminate);
+    }
+
+    /*
+     * Connect the device driver handler that will be called when an
+     * interrupt for the device occurs, the handler defined above performs
+     * the specific interrupt processing for the device.
+     */
+    // XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr,
+    //             (Xil_ExceptionHandler)XEmacPs_IntrHandler,
+    //                     (void *)&xemacpsif->emacps);
+    /*
+     * Enable the interrupt for emacps.
+     */
+    // XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, (u32) xtopologyp->scugic_emac_intr);
     emac_intr_num = (u32) xtopologyp->scugic_emac_intr;
     return 0;
 }
@@ -783,19 +783,19 @@ void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif)
 
     gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
     if (gigeversion == 2) {
-	    tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET);
-	    if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) {
-		    regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET);
-		    regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
-		    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET, regctrl);
-		    regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
-		    regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
-		    XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
-		}
-	    xemacpsif->last_rx_frms_cntr = tempcntr;
-	}
+        tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET);
+        if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) {
+            regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+                    XEMACPS_NWCTRL_OFFSET);
+            regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
+            XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+                    XEMACPS_NWCTRL_OFFSET, regctrl);
+            regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
+            regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
+            XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
+        }
+        xemacpsif->last_rx_frms_cntr = tempcntr;
+    }
 }
 
 void free_txrx_pbufs(xemacpsif_s *xemacpsif)
@@ -807,18 +807,18 @@ void free_txrx_pbufs(xemacpsif_s *xemacpsif)
     index1 = get_base_index_txpbufsstorage (xemacpsif);
 
     for (index = index1; index < (index1 + XLWIP_CONFIG_N_TX_DESC); index++) {
-	    if (tx_pbufs_storage[index] != 0) {
-		    p = (struct pbuf *)tx_pbufs_storage[index];
-		    pbuf_free(p);
-		    tx_pbufs_storage[index] = 0;
-		}
-	}
+        if (tx_pbufs_storage[index] != 0) {
+            p = (struct pbuf *)tx_pbufs_storage[index];
+            pbuf_free(p);
+            tx_pbufs_storage[index] = 0;
+        }
+    }
 
     for (index = index1; index < (index1 + XLWIP_CONFIG_N_TX_DESC); index++) {
-	    p = (struct pbuf *)rx_pbufs_storage[index];
-	    pbuf_free(p);
+        p = (struct pbuf *)rx_pbufs_storage[index];
+        pbuf_free(p);
 
-	}
+    }
 }
 
 void free_onlytx_pbufs(xemacpsif_s *xemacpsif)
@@ -829,12 +829,12 @@ void free_onlytx_pbufs(xemacpsif_s *xemacpsif)
 
     index1 = get_base_index_txpbufsstorage (xemacpsif);
     for (index = index1; index < (index1 + XLWIP_CONFIG_N_TX_DESC); index++) {
-	    if (tx_pbufs_storage[index] != 0) {
-		    p = (struct pbuf *)tx_pbufs_storage[index];
-		    pbuf_free(p);
-		    tx_pbufs_storage[index] = 0;
-		}
-	}
+        if (tx_pbufs_storage[index] != 0) {
+            p = (struct pbuf *)tx_pbufs_storage[index];
+            pbuf_free(p);
+            tx_pbufs_storage[index] = 0;
+        }
+    }
 }
 
 /* reset Tx and Rx DMA pointers after XEmacPs_Stop */
@@ -851,10 +851,10 @@ void reset_dma(struct xemac_s *xemac)
 
     gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
     if (gigeversion > 2) {
-	    txqueuenum = 1;
-	} else {
-	    txqueuenum = 0;
-	}
+        txqueuenum = 1;
+    } else {
+        txqueuenum = 0;
+    }
 
     XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
     XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, txqueuenum, XEMACPS_SEND);
@@ -862,12 +862,12 @@ void reset_dma(struct xemac_s *xemac)
 
 void emac_disable_intr(void)
 {
-	// XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
+    // XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
     rt_hw_interrupt_mask(emac_intr_num);
 }
 
 void emac_enable_intr(void)
 {
-	// XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
+    // XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
     rt_hw_interrupt_umask(emac_intr_num);
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c

@@ -55,11 +55,11 @@ XEmacPs_Config *xemacps_lookup_config(unsigned mac_base)
     s32_t i;
 
     for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
-	    if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
-		    cfgptr = &XEmacPs_ConfigTable[i];
-		    break;
-		}
-	}
+        if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
+            cfgptr = &XEmacPs_ConfigTable[i];
+            break;
+        }
+    }
 
     return (cfgptr);
 }
@@ -82,11 +82,11 @@ void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
     XEmacPs_SetOptions(xemacpsp, XEMACPS_MULTICAST_OPTION);
 #endif
 
-	/* set mac address */
+    /* set mac address */
     status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
     if (status != XST_SUCCESS) {
-	    xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
-	}
+        xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+    }
 
     XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
 
@@ -109,44 +109,44 @@ void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
 #else
     detect_phy(xemacpsp);
     for (i = 31; i > 0; i--) {
-	    if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-		    if (phymapemac0[i] == TRUE) {
-			    link_speed = phy_setup_emacps(xemacpsp, i);
-			    phyfoundforemac0 = TRUE;
-			    phyaddrforemac = i;
-			}
-		} else {
-		    if (phymapemac1[i] == TRUE) {
-			    link_speed = phy_setup_emacps(xemacpsp, i);
-			    phyfoundforemac1 = TRUE;
-			    phyaddrforemac = i;
-			}
-		}
-	}
-	/* If no PHY was detected, use broadcast PHY address of 0 */
+        if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+            if (phymapemac0[i] == TRUE) {
+                link_speed = phy_setup_emacps(xemacpsp, i);
+                phyfoundforemac0 = TRUE;
+                phyaddrforemac = i;
+            }
+        } else {
+            if (phymapemac1[i] == TRUE) {
+                link_speed = phy_setup_emacps(xemacpsp, i);
+                phyfoundforemac1 = TRUE;
+                phyaddrforemac = i;
+            }
+        }
+    }
+    /* If no PHY was detected, use broadcast PHY address of 0 */
     if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
-	    if (phyfoundforemac0 == FALSE)
-		    link_speed = phy_setup_emacps(xemacpsp, 0);
-	} else {
-	    if (phyfoundforemac1 == FALSE)
-		    link_speed = phy_setup_emacps(xemacpsp, 0);
-	}
+        if (phyfoundforemac0 == FALSE)
+            link_speed = phy_setup_emacps(xemacpsp, 0);
+    } else {
+        if (phyfoundforemac1 == FALSE)
+            link_speed = phy_setup_emacps(xemacpsp, 0);
+    }
 #endif
 
     if (link_speed == XST_FAILURE) {
-	    eth_link_status = ETH_LINK_DOWN;
-	    xil_printf("Phy setup failure %s \n\r",__func__);
-	    return;
-	} else {
-	    eth_link_status = ETH_LINK_UP;
-	}
+        eth_link_status = ETH_LINK_DOWN;
+        xil_printf("Phy setup failure %s \n\r",__func__);
+        return;
+    } else {
+        eth_link_status = ETH_LINK_UP;
+    }
 
     XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
-	/* Setting the operating speed of the MAC needs a delay. */
-	{
-	    volatile s32_t wait;
-	    for (wait=0; wait < 20000; wait++);
-	}
+    /* Setting the operating speed of the MAC needs a delay. */
+    {
+        volatile s32_t wait;
+        for (wait=0; wait < 20000; wait++);
+    }
 }
 
 void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
@@ -156,19 +156,19 @@ void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
 
     xemacpsp = &xemacps->emacps;
 
-	/* set mac address */
+    /* set mac address */
     status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
     if (status != XST_SUCCESS) {
-	    xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
-	}
+        xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+    }
 
     XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
 
-	/* Setting the operating speed of the MAC needs a delay. */
-	{
-	    volatile s32_t wait;
-	    for (wait=0; wait < 20000; wait++);
-	}
+    /* Setting the operating speed of the MAC needs a delay. */
+    {
+        volatile s32_t wait;
+        for (wait=0; wait < 20000; wait++);
+    }
 }
 
 void setup_isr (struct xemac_s *xemac)
@@ -176,41 +176,41 @@ void setup_isr (struct xemac_s *xemac)
     xemacpsif_s   *xemacpsif;
 
     xemacpsif = (xemacpsif_s *)(xemac->state);
-	/*
-	 * Setup callbacks
-	 */
+    /*
+     * Setup callbacks
+     */
     XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND,
-				     (void *) emacps_send_handler,
-				     (void *) xemac);
+                     (void *) emacps_send_handler,
+                     (void *) xemac);
 
     XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV,
-				    (void *) emacps_recv_handler,
-				    (void *) xemac);
+                    (void *) emacps_recv_handler,
+                    (void *) xemac);
 
     XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR,
-				    (void *) emacps_error_handler,
-				    (void *) xemac);
+                    (void *) emacps_error_handler,
+                    (void *) xemac);
 }
 
 void start_emacps (xemacpsif_s *xemacps)
 {
-	/* start the temac */
+    /* start the temac */
     XEmacPs_Start(&xemacps->emacps);
 }
 
 void restart_emacps_transmitter (xemacpsif_s *xemacps) {
     u32_t Reg;
     Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
-				    XEMACPS_NWCTRL_OFFSET);
+                    XEMACPS_NWCTRL_OFFSET);
     Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK);
     XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
-									    XEMACPS_NWCTRL_OFFSET, Reg);
+                                        XEMACPS_NWCTRL_OFFSET, Reg);
 
     Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
-					    XEMACPS_NWCTRL_OFFSET);
+                        XEMACPS_NWCTRL_OFFSET);
     Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK);
     XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
-									    XEMACPS_NWCTRL_OFFSET, Reg);
+                                        XEMACPS_NWCTRL_OFFSET, Reg);
 }
 
 void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
@@ -229,47 +229,47 @@ void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
     txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
 
     if (ErrorWord != 0) {
-	    switch (Direction) {
-		    case XEMACPS_RECV:
-		    if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
-			    HandleEmacPsError(xemac);
-			}
-		    if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
-			    emacps_recv_handler(arg);
-			    setup_rx_bds(xemacpsif, rxring);
-			}
-		    if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
-			    emacps_recv_handler(arg);
-			    setup_rx_bds(xemacpsif, rxring);
-			}
-		    break;
-		    case XEMACPS_SEND:
-		    if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
-			    HandleEmacPsError(xemac);
-			}
-		    if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
-			    HandleTxErrors(xemac);
-			}
-		    if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
-			    HandleTxErrors(xemac);
-			}
-		    if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
-			    HandleTxErrors(xemac);
-			}
-		    if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
-			    LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
-				// process_sent_bds(xemacpsif, txring);
-			}
-		    break;
-		}
-	}
+        switch (Direction) {
+            case XEMACPS_RECV:
+            if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
+                HandleEmacPsError(xemac);
+            }
+            if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
+                emacps_recv_handler(arg);
+                setup_rx_bds(xemacpsif, rxring);
+            }
+            if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
+                emacps_recv_handler(arg);
+                setup_rx_bds(xemacpsif, rxring);
+            }
+            break;
+            case XEMACPS_SEND:
+            if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
+                HandleEmacPsError(xemac);
+            }
+            if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
+                HandleTxErrors(xemac);
+            }
+            if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
+                HandleTxErrors(xemac);
+            }
+            if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
+                HandleTxErrors(xemac);
+            }
+            if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
+                LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
+                // process_sent_bds(xemacpsif, txring);
+            }
+            break;
+        }
+    }
 #ifdef OS_IS_FREERTOS
     xInsideISR--;
 #endif

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_physpeed.c

@@ -119,31 +119,31 @@
 
 #define CONFIG_LINKSPEED_AUTODETECT 1
 
-#define PHY_DETECT_REG  					    1
-#define PHY_IDENTIFIER_1_REG				    2
-#define PHY_IDENTIFIER_2_REG				    3
-#define PHY_DETECT_MASK 				    0x1808
-#define PHY_MARVELL_IDENTIFIER			    0x0141
-#define PHY_TI_IDENTIFIER				    0x2000
-#define PHY_REALTEK_IDENTIFIER			    0x001c
-#define PHY_XILINX_PCS_PMA_ID1		    0x0174
-#define PHY_XILINX_PCS_PMA_ID2		    0x0C00
-
-#define XEMACPS_GMII2RGMII_SPEED1000_FD	    0x140
-#define XEMACPS_GMII2RGMII_SPEED100_FD	    0x2100
-#define XEMACPS_GMII2RGMII_SPEED10_FD	    0x100
-#define XEMACPS_GMII2RGMII_REG_NUM		    0x10
-
-#define PHY_REGCR	    0x0D
-#define PHY_ADDAR	    0x0E
+#define PHY_DETECT_REG                          1
+#define PHY_IDENTIFIER_1_REG                    2
+#define PHY_IDENTIFIER_2_REG                    3
+#define PHY_DETECT_MASK                     0x1808
+#define PHY_MARVELL_IDENTIFIER                0x0141
+#define PHY_TI_IDENTIFIER                    0x2000
+#define PHY_REALTEK_IDENTIFIER                0x001c
+#define PHY_XILINX_PCS_PMA_ID1            0x0174
+#define PHY_XILINX_PCS_PMA_ID2            0x0C00
+
+#define XEMACPS_GMII2RGMII_SPEED1000_FD        0x140
+#define XEMACPS_GMII2RGMII_SPEED100_FD        0x2100
+#define XEMACPS_GMII2RGMII_SPEED10_FD        0x100
+#define XEMACPS_GMII2RGMII_REG_NUM            0x10
+
+#define PHY_REGCR        0x0D
+#define PHY_ADDAR        0x0E
 #define PHY_RGMIIDCTL    0x86
 #define PHY_RGMIICTL    0x32
-#define PHY_STS		    0x11
-#define PHY_TI_CR	    0x10
-#define PHY_TI_CFG4	    0x31
+#define PHY_STS            0x11
+#define PHY_TI_CR        0x10
+#define PHY_TI_CFG4        0x31
 
-#define MICREL_PHY_IDENTIFIER			    0x22
-#define MICREL_PHY_KSZ9031_MODEL		    0x220
+#define MICREL_PHY_IDENTIFIER                0x22
+#define MICREL_PHY_KSZ9031_MODEL            0x220
 
 #define PHY_REGCR_ADDR    0x001F
 #define PHY_REGCR_DATA    0x401F
@@ -151,14 +151,14 @@
 #define PHY_TI_CFG4RESVDBIT7    0x80
 
 /* Frequency setting */
-#define SLCR_LOCK_ADDR			(XPS_SYS_CTRL_BASEADDR + 0x4)
-#define SLCR_UNLOCK_ADDR		(XPS_SYS_CTRL_BASEADDR + 0x8)
-#define SLCR_GEM0_CLK_CTRL_ADDR	(XPS_SYS_CTRL_BASEADDR + 0x140)
-#define SLCR_GEM1_CLK_CTRL_ADDR	(XPS_SYS_CTRL_BASEADDR + 0x144)
+#define SLCR_LOCK_ADDR            (XPS_SYS_CTRL_BASEADDR + 0x4)
+#define SLCR_UNLOCK_ADDR        (XPS_SYS_CTRL_BASEADDR + 0x8)
+#define SLCR_GEM0_CLK_CTRL_ADDR    (XPS_SYS_CTRL_BASEADDR + 0x140)
+#define SLCR_GEM1_CLK_CTRL_ADDR    (XPS_SYS_CTRL_BASEADDR + 0x144)
 #define SLCR_GEM_SRCSEL_EMIO    0x40
 #define SLCR_LOCK_KEY_VALUE     0x767B
 #define SLCR_UNLOCK_KEY_VALUE    0xDF0D
-#define SLCR_ADDR_GEM_RST_CTRL	(XPS_SYS_CTRL_BASEADDR + 0x214)
+#define SLCR_ADDR_GEM_RST_CTRL    (XPS_SYS_CTRL_BASEADDR + 0x214)
 #define EMACPS_SLCR_DIV_MASK    0xFC0FC0FF
 
 #if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
@@ -181,7 +181,7 @@ static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr);
 #endif
 static void SetUpSLCRDivisors(u32_t mac_baseaddr, s32_t speed);
 #if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
-	|| defined (CONFIG_LINKSPEED10)
+    || defined (CONFIG_LINKSPEED10)
 static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed);
 #endif
 
@@ -193,30 +193,30 @@ u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
     u16_t phy_id;
 
     if(phy_addr == 0) {
-	    for (phy_addr = 31; phy_addr > 0; phy_addr--) {
-		    XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
-					&phy_id);
-
-		    if (phy_id == PHY_XILINX_PCS_PMA_ID1) {
-			    XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG,
-						&phy_id);
-			    if (phy_id == PHY_XILINX_PCS_PMA_ID2) {
-					/* Found a valid PHY address */
-				    LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
-						    phy_addr));
-				    break;
-				}
-			}
-		}
-	}
+        for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+            XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
+                    &phy_id);
+
+            if (phy_id == PHY_XILINX_PCS_PMA_ID1) {
+                XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG,
+                        &phy_id);
+                if (phy_id == PHY_XILINX_PCS_PMA_ID2) {
+                    /* Found a valid PHY address */
+                    LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
+                            phy_addr));
+                    break;
+                }
+            }
+        }
+    }
 
     link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
     if (link_speed == 1000)
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
     else if (link_speed == 100)
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
     else
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
 
     xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
     return link_speed;
@@ -241,44 +241,44 @@ static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
     while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
-	    sleep(1);
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
-																&status);
-	}
+        sleep(1);
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
+                                                                &status);
+    }
     xil_printf("autonegotiation complete \r\n");
 
 #if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 1);
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
     if ((temp & 0x0020) == 0x0020) {
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
-	    return 1000;
-	}
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+        return 1000;
+    }
     else {
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
-	    xil_printf("Link error, temp = %x\r\n", temp);
-	    return 0;
-	}
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+        xil_printf("Link error, temp = %x\r\n", temp);
+        return 0;
+    }
 #elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
     xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n");
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
     while(!(temp & 0x8000)) {
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
-	}
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+    }
     if((temp & 0x0C00) == 0x0800) {
-	    return 1000;
-	}
+        return 1000;
+    }
     else if((temp & 0x0C00) == 0x0400) {
-	    return 100;
-	}
+        return 100;
+    }
     else if((temp & 0x0C00) == 0x0000) {
-	    return 10;
-	} else {
-	    xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Defaulting to Speed = 10 Mbps\r\n");
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &temp);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, 0x0100);
-	    return 10;
-	}
+        return 10;
+    } else {
+        xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Defaulting to Speed = 10 Mbps\r\n");
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &temp);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, 0x0100);
+        return 10;
+    }
 #endif
 
 }
@@ -291,32 +291,32 @@ void detect_phy(XEmacPs *xemacpsp)
     u32_t emacnum;
 
     if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR)
-	    emacnum = 0;
+        emacnum = 0;
     else
-	    emacnum = 1;
+        emacnum = 1;
     for (phy_addr = 31; phy_addr > 0; phy_addr--) {
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG,
-							&phy_reg);
-
-	    if ((phy_reg != 0xFFFF) &&
-			((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-			/* Found a valid PHY address */
-		    LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
-																    phy_addr));
-		    if (emacnum == 0)
-			    phymapemac0[phy_addr] = TRUE;
-		    else
-			    phymapemac1[phy_addr] = TRUE;
-
-		    XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
-							&phy_reg);
-		    if ((phy_reg != PHY_MARVELL_IDENTIFIER) &&
-				(phy_reg != PHY_TI_IDENTIFIER) &&
-				(phy_reg != PHY_REALTEK_IDENTIFIER)) {
-			    xil_printf("WARNING: Not a Marvell or TI or Realtek Ethernet PHY. Please verify the initialization sequence\r\n");
-			}
-		}
-	}
+        XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG,
+                            &phy_reg);
+
+        if ((phy_reg != 0xFFFF) &&
+            ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+            /* Found a valid PHY address */
+            LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
+                                                                    phy_addr));
+            if (emacnum == 0)
+                phymapemac0[phy_addr] = TRUE;
+            else
+                phymapemac1[phy_addr] = TRUE;
+
+            XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
+                            &phy_reg);
+            if ((phy_reg != PHY_MARVELL_IDENTIFIER) &&
+                (phy_reg != PHY_TI_IDENTIFIER) &&
+                (phy_reg != PHY_REALTEK_IDENTIFIER)) {
+                xil_printf("WARNING: Not a Marvell or TI or Realtek Ethernet PHY. Please verify the initialization sequence\r\n");
+            }
+        }
+    }
 }
 
 u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
@@ -338,18 +338,18 @@ u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
 #ifdef  CONFIG_LINKSPEED_AUTODETECT
     link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
     if (link_speed == 1000) {
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
-	    convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
-	} else if (link_speed == 100) {
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
-	    convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
-	} else if (link_speed != XST_FAILURE){
-	    SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
-	    convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
-	} else {
-	    xil_printf("Phy setup error \r\n");
-	    return XST_FAILURE;
-	}
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
+        convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
+    } else if (link_speed == 100) {
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
+        convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
+    } else if (link_speed != XST_FAILURE){
+        SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
+        convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
+    } else {
+        xil_printf("Phy setup error \r\n");
+        return XST_FAILURE;
+    }
 #elif    defined(CONFIG_LINKSPEED1000)
     SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
     link_speed = 1000;
@@ -370,9 +370,9 @@ u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
     sleep(1);
 #endif
     if (conv_present) {
-	    XEmacPs_PhyWrite(xemacpsp, convphyaddr,
-	    XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);
-	}
+        XEmacPs_PhyWrite(xemacpsp, convphyaddr,
+        XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);
+    }
 
     xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
     return link_speed;
@@ -405,10 +405,10 @@ static u32_t get_phy_speed_ksz9031(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-					   &control);
+                       &control);
     control |= ADVERTISE_1000;
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-					   control);
+                       control);
 
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, &control);
@@ -416,7 +416,7 @@ static u32_t get_phy_speed_ksz9031(XEmacPs *xemacpsp, u32_t phy_addr)
     control |= (7 << 12); /* max number of gigabit attempts */
     control |= (1 << 11); /* enable downshift */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
-					 control);
+                     control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
     control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
@@ -428,45 +428,45 @@ static u32_t get_phy_speed_ksz9031(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
 
     while (1) {
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
-	    if (control & IEEE_CTRL_RESET_MASK)
-			 continue;
-	    else
-		    break;
-	}
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+        if (control & IEEE_CTRL_RESET_MASK)
+             continue;
+        else
+            break;
+    }
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
 
     while (!(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)) {
-	    sleep(1);
-	    XEmacPs_PhyRead(xemacpsp, phy_addr,
-						    IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp);
-	    timeout_counter++;
-	    if ((phy_init_flag == 0) && (timeout_counter > 1))
-		{
-		    phy_init_flag = 1;
-		    return XST_FAILURE;
-		}
-	    if (timeout_counter == 30) {
-		    xil_printf("Auto negotiation error \r\n");
-		    return XST_FAILURE;
-		}
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	}
+        sleep(1);
+        XEmacPs_PhyRead(xemacpsp, phy_addr,
+                            IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp);
+        timeout_counter++;
+        if ((phy_init_flag == 0) && (timeout_counter > 1))
+        {
+            phy_init_flag = 1;
+            return XST_FAILURE;
+        }
+        if (timeout_counter == 30) {
+            xil_printf("Auto negotiation error \r\n");
+            return XST_FAILURE;
+        }
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    }
     xil_printf("autonegotiation complete \r\n");
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1f, &status_speed);
 
     if ((status_speed & 0x40) == 0x40) /* 1000Mbps */
-	    return 1000;
+        return 1000;
     else if ((status_speed & 0x20) == 0x20) /* 100Mbps */
-	    return 100;
+        return 100;
     else if ((status_speed & 0x10) == 0x10) /* 10Mbps */
-	    return 10;
+        return 10;
     else
-	    return 0;
+        return 0;
     return XST_SUCCESS;
 }
 
@@ -488,75 +488,75 @@ static u32_t get_TI_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, 0x1F, phyregtemp);
     RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1F, (u16_t *)&phyregtemp);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error during sw reset \n\r");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error during sw reset \n\r");
+        return XST_FAILURE;
+    }
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
     phyregtemp |= 0x8000;
     XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, phyregtemp);
 
-	/*
-	 * Delay
-	 */
+    /*
+     * Delay
+     */
     for(i=0;i<1000000000;i++);
 
     RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error during reset \n\r");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error during reset \n\r");
+        return XST_FAILURE;
+    }
 
-	/* FIFO depth */
+    /* FIFO depth */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_TI_CR, PHY_TI_CRVAL);
     RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_TI_CR, (u16_t *)&phyregtemp);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error writing to 0x10 \n\r");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error writing to 0x10 \n\r");
+        return XST_FAILURE;
+    }
 
-	/* TX/RX tuning */
-	/* Write to PHY_RGMIIDCTL */
+    /* TX/RX tuning */
+    /* Write to PHY_RGMIIDCTL */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
     RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xA8);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error in tuning");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error in tuning");
+        return XST_FAILURE;
+    }
 
-	/* Read PHY_RGMIIDCTL */
+    /* Read PHY_RGMIIDCTL */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
     RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error in tuning");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error in tuning");
+        return XST_FAILURE;
+    }
 
-	/* Write PHY_RGMIICTL */
+    /* Write PHY_RGMIICTL */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
     RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xD3);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error in tuning");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error in tuning");
+        return XST_FAILURE;
+    }
 
-	/* Read PHY_RGMIICTL */
+    /* Read PHY_RGMIICTL */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
     RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
     if (RetStatus != XST_SUCCESS) {
-	    xil_printf("Error in tuning");
-	    return XST_FAILURE;
-	}
+        xil_printf("Error in tuning");
+        return XST_FAILURE;
+    }
 
-	/* SW workaround for unstable link when RX_CTRL is not STRAP MODE 3 or 4 */
+    /* SW workaround for unstable link when RX_CTRL is not STRAP MODE 3 or 4 */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_TI_CFG4);
     XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
@@ -575,10 +575,10 @@ static u32_t get_TI_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-					&control);
+                    &control);
     control |= ADVERTISE_1000;
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-				    control);
+                    control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
     control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
@@ -591,29 +591,29 @@ static u32_t get_TI_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
 
     while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
-	    sleep(1);
-	    timeout_counter++;
-	    if ((phy_init_flag == 0) && (timeout_counter > 1))
-		{
-		    phy_init_flag = 1;
-		    return XST_FAILURE;
-		}
-	    if (timeout_counter == 30) {
-		    xil_printf("Auto negotiation error \r\n");
-		    return XST_FAILURE;
-		}
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	}
+        sleep(1);
+        timeout_counter++;
+        if ((phy_init_flag == 0) && (timeout_counter > 1))
+        {
+            phy_init_flag = 1;
+            return XST_FAILURE;
+        }
+        if (timeout_counter == 30) {
+            xil_printf("Auto negotiation error \r\n");
+            return XST_FAILURE;
+        }
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    }
     xil_printf("autonegotiation complete \r\n");
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_STS, &status_speed);
     if ((status_speed & 0xC000) == 0x8000) {
-	    return 1000;
-	} else if ((status_speed & 0xC000) == 0x4000) {
-	    return 100;
-	} else {
-	    return 10;
-	}
+        return 1000;
+    } else if ((status_speed & 0xC000) == 0x4000) {
+        return 100;
+    } else {
+        return 10;
+    }
 
     return XST_SUCCESS;
 }
@@ -645,18 +645,18 @@ static u32_t get_Marvell_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-					&control);
+                    &control);
     control |= ADVERTISE_1000;
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-				    control);
+                    control);
 
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
-																&control);
-    control |= (7 << 12);	/* max number of gigabit attempts */
-    control |= (1 << 11);	/* enable downshift */
+                                                                &control);
+    control |= (7 << 12);    /* max number of gigabit attempts */
+    control |= (1 << 11);    /* enable downshift */
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
-															    control);
+                                                                control);
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
     control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
     control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
@@ -667,47 +667,47 @@ static u32_t get_Marvell_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
 
     while (1) {
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
-	    if (control & IEEE_CTRL_RESET_MASK)
-		    continue;
-	    else
-		    break;
-	}
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+        if (control & IEEE_CTRL_RESET_MASK)
+            continue;
+        else
+            break;
+    }
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
 
     while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
-	    sleep(1);
-	    XEmacPs_PhyRead(xemacpsp, phy_addr,
-					    IEEE_COPPER_SPECIFIC_STATUS_REG_2,  &temp);
-	    timeout_counter++;
-	    if ((phy_init_flag == 0) && (timeout_counter > 1))
-		{
-		    phy_init_flag = 1;
-		    return XST_FAILURE;
-		}
-	    if (timeout_counter == 30) {
-		    xil_printf("Auto negotiation error \r\n");
-		    return XST_FAILURE;
-		}
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	}
+        sleep(1);
+        XEmacPs_PhyRead(xemacpsp, phy_addr,
+                        IEEE_COPPER_SPECIFIC_STATUS_REG_2,  &temp);
+        timeout_counter++;
+        if ((phy_init_flag == 0) && (timeout_counter > 1))
+        {
+            phy_init_flag = 1;
+            return XST_FAILURE;
+        }
+        if (timeout_counter == 30) {
+            xil_printf("Auto negotiation error \r\n");
+            return XST_FAILURE;
+        }
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    }
     xil_printf("autonegotiation complete \r\n");
 
     XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
-					&status_speed);
+                    &status_speed);
     if (status_speed & 0x400) {
-	    temp_speed = status_speed & IEEE_SPEED_MASK;
+        temp_speed = status_speed & IEEE_SPEED_MASK;
 
-	    if (temp_speed == IEEE_SPEED_1000)
-		    return 1000;
-	    else if(temp_speed == IEEE_SPEED_100)
-		    return 100;
-	    else
-		    return 10;
-	}
+        if (temp_speed == IEEE_SPEED_1000)
+            return 1000;
+        else if(temp_speed == IEEE_SPEED_100)
+            return 100;
+        else
+            return 10;
+    }
 
     return XST_SUCCESS;
 }
@@ -731,10 +731,10 @@ static u32_t get_Realtek_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-					&control);
+                    &control);
     control |= ADVERTISE_1000;
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
-				    control);
+                    control);
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
     control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
@@ -746,45 +746,45 @@ static u32_t get_Realtek_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
 
     while (1) {
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
-	    if (control & IEEE_CTRL_RESET_MASK)
-		    continue;
-	    else
-		    break;
-	}
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+        if (control & IEEE_CTRL_RESET_MASK)
+            continue;
+        else
+            break;
+    }
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
 
     xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
 
     while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
-	    sleep(1);
-	    timeout_counter++;
-	    if ((phy_init_flag == 0) && (timeout_counter > 1))
-		{
-		    phy_init_flag = 1;
-		    return XST_FAILURE;
-		}
-	    if (timeout_counter == 30) {
-		    xil_printf("Auto negotiation error \r\n");
-		    return XST_FAILURE;
-		}
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
-	}
+        sleep(1);
+        timeout_counter++;
+        if ((phy_init_flag == 0) && (timeout_counter > 1))
+        {
+            phy_init_flag = 1;
+            return XST_FAILURE;
+        }
+        if (timeout_counter == 30) {
+            xil_printf("Auto negotiation error \r\n");
+            return XST_FAILURE;
+        }
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+    }
     xil_printf("autonegotiation complete \r\n");
 
     XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
-					&status_speed);
+                    &status_speed);
     if (status_speed & 0x400) {
-	    temp_speed = status_speed & IEEE_SPEED_MASK;
+        temp_speed = status_speed & IEEE_SPEED_MASK;
 
-	    if (temp_speed == IEEE_SPEED_1000)
-		    return 1000;
-	    else if(temp_speed == IEEE_SPEED_100)
-		    return 100;
-	    else
-		    return 10;
-	}
+        if (temp_speed == IEEE_SPEED_1000)
+            return 1000;
+        else if(temp_speed == IEEE_SPEED_100)
+            return 100;
+        else
+            return 10;
+    }
 
     return XST_FAILURE;
 }
@@ -795,23 +795,23 @@ static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
     u32_t RetStatus;
 
     XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
-					&phy_identity);
+                    &phy_identity);
     if(phy_identity == MICREL_PHY_IDENTIFIER){
-	    RetStatus = get_phy_speed_ksz9031(xemacpsp, phy_addr);
-	} else if (phy_identity == PHY_TI_IDENTIFIER) {
-	    RetStatus = get_TI_phy_speed(xemacpsp, phy_addr);
-	} else if (phy_identity == PHY_REALTEK_IDENTIFIER) {
-	    RetStatus = get_Realtek_phy_speed(xemacpsp, phy_addr);
-	} else {
-	    RetStatus = get_Marvell_phy_speed(xemacpsp, phy_addr);
-	}
+        RetStatus = get_phy_speed_ksz9031(xemacpsp, phy_addr);
+    } else if (phy_identity == PHY_TI_IDENTIFIER) {
+        RetStatus = get_TI_phy_speed(xemacpsp, phy_addr);
+    } else if (phy_identity == PHY_REALTEK_IDENTIFIER) {
+        RetStatus = get_Realtek_phy_speed(xemacpsp, phy_addr);
+    } else {
+        RetStatus = get_Marvell_phy_speed(xemacpsp, phy_addr);
+    }
 
     return RetStatus;
 }
 #endif
 
 #if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
-	|| defined (CONFIG_LINKSPEED10)
+    || defined (CONFIG_LINKSPEED10)
 static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed)
 {
     u16_t control;
@@ -835,68 +835,68 @@ static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t s
     control &= ~IEEE_CTRL_LINKSPEED_10M;
 
     if (speed == 1000) {
-	    control |= IEEE_CTRL_LINKSPEED_1000M;
+        control |= IEEE_CTRL_LINKSPEED_1000M;
 
-		/* Don't advertise PHY speed of 100 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg &= (~ADVERTISE_100);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+        /* Don't advertise PHY speed of 100 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg &= (~ADVERTISE_100);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
 
-		/* Don't advertise PHY speed of 10 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg &= (~ADVERTISE_10);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+        /* Don't advertise PHY speed of 10 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg &= (~ADVERTISE_10);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
 
-		/* Advertise PHY speed of 1000 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
-	    autonereg |= ADVERTISE_1000;
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
-	}
+        /* Advertise PHY speed of 1000 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+        autonereg |= ADVERTISE_1000;
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+    }
 
     else if (speed == 100) {
-	    control |= IEEE_CTRL_LINKSPEED_100M;
+        control |= IEEE_CTRL_LINKSPEED_100M;
 
-		/* Don't advertise PHY speed of 1000 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
-	    autonereg &= (~ADVERTISE_1000);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+        /* Don't advertise PHY speed of 1000 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+        autonereg &= (~ADVERTISE_1000);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
 
-		/* Don't advertise PHY speed of 10 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg &= (~ADVERTISE_10);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+        /* Don't advertise PHY speed of 10 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg &= (~ADVERTISE_10);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
 
-		/* Advertise PHY speed of 100 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg |= ADVERTISE_100;
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
-	}
+        /* Advertise PHY speed of 100 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg |= ADVERTISE_100;
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+    }
 
     else if (speed == 10) {
-	    control |= IEEE_CTRL_LINKSPEED_10M;
+        control |= IEEE_CTRL_LINKSPEED_10M;
 
-		/* Don't advertise PHY speed of 1000 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
-	    autonereg &= (~ADVERTISE_1000);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+        /* Don't advertise PHY speed of 1000 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+        autonereg &= (~ADVERTISE_1000);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
 
-		/* Don't advertise PHY speed of 100 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg &= (~ADVERTISE_100);
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+        /* Don't advertise PHY speed of 100 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg &= (~ADVERTISE_100);
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
 
-		/* Advertise PHY speed of 10 Mbps */
-	    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
-	    autonereg |= ADVERTISE_10;
-	    XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
-	}
+        /* Advertise PHY speed of 10 Mbps */
+        XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+        autonereg |= ADVERTISE_10;
+        XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+    }
 
     XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET,
-										    control | IEEE_CTRL_RESET_MASK);
-	{
-	    volatile s32_t wait;
-	    for (wait=0; wait < 100000; wait++);
-	}
+                                            control | IEEE_CTRL_RESET_MASK);
+    {
+        volatile s32_t wait;
+        for (wait=0; wait < 100000; wait++);
+    }
     return 0;
 }
 #endif
@@ -920,233 +920,233 @@ static void SetUpSLCRDivisors(u32_t mac_baseaddr, s32_t speed)
     gigeversion = ((Xil_In32(mac_baseaddr + 0xFC)) >> 16) & 0xFFF;
     if (gigeversion == 2) {
 
-		*(volatile u32_t *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
+        *(volatile u32_t *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
 
-	    if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
-		    slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
-		} else {
-		    slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
-		}
+        if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
+            slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
+        } else {
+            slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
+        }
 
-	    if((*(volatile u32_t *)(UINTPTR)(slcrBaseAddress)) &
-		    SLCR_GEM_SRCSEL_EMIO) {
-			    return;
-		}
+        if((*(volatile u32_t *)(UINTPTR)(slcrBaseAddress)) &
+            SLCR_GEM_SRCSEL_EMIO) {
+                return;
+        }
 
-	    if (speed == 1000) {
-		    if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
+        if (speed == 1000) {
+            if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			} else {
+            } else {
 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			}
-		} else if (speed == 100) {
-		    if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
+            }
+        } else if (speed == 100) {
+            if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
 #endif
-			} else {
+            } else {
 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
 #endif
-			}
-		} else {
-		    if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
+            }
+        } else {
+            if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
 #endif
-			} else {
+            } else {
 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
-			    SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
-			    SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
+                SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+                SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
 #endif
-			}
-		}
-
-	    if (SlcrDiv0 != 0 && SlcrDiv1 != 0) {
-		    SlcrTxClkCntrl = *(volatile u32_t *)(UINTPTR)(slcrBaseAddress);
-		    SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
-		    SlcrTxClkCntrl |= (SlcrDiv1 << 20);
-		    SlcrTxClkCntrl |= (SlcrDiv0 << 8);
-			*(volatile u32_t *)(UINTPTR)(slcrBaseAddress) = SlcrTxClkCntrl;
-			*(volatile u32_t *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
-		} else {
-		    xil_printf("Clock Divisors incorrect - Please check\r\n");
-		}
-	} else if (gigeversion == GEM_VERSION_ZYNQMP) {
-		/* Setup divisors in CRL_APB for Zynq Ultrascale+ MPSoC */
-	    if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
-		    CrlApbBaseAddr = CRL_APB_GEM0_REF_CTRL;
-		} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
-		    CrlApbBaseAddr = CRL_APB_GEM1_REF_CTRL;
-		} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
-		    CrlApbBaseAddr = CRL_APB_GEM2_REF_CTRL;
-		} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
-		    CrlApbBaseAddr = CRL_APB_GEM3_REF_CTRL;
-		}
-
-	    if (speed == 1000) {
-		    if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+            }
+        }
+
+        if (SlcrDiv0 != 0 && SlcrDiv1 != 0) {
+            SlcrTxClkCntrl = *(volatile u32_t *)(UINTPTR)(slcrBaseAddress);
+            SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
+            SlcrTxClkCntrl |= (SlcrDiv1 << 20);
+            SlcrTxClkCntrl |= (SlcrDiv0 << 8);
+            *(volatile u32_t *)(UINTPTR)(slcrBaseAddress) = SlcrTxClkCntrl;
+            *(volatile u32_t *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
+        } else {
+            xil_printf("Clock Divisors incorrect - Please check\r\n");
+        }
+    } else if (gigeversion == GEM_VERSION_ZYNQMP) {
+        /* Setup divisors in CRL_APB for Zynq Ultrascale+ MPSoC */
+        if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+            CrlApbBaseAddr = CRL_APB_GEM0_REF_CTRL;
+        } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+            CrlApbBaseAddr = CRL_APB_GEM1_REF_CTRL;
+        } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+            CrlApbBaseAddr = CRL_APB_GEM2_REF_CTRL;
+        } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+            CrlApbBaseAddr = CRL_APB_GEM3_REF_CTRL;
+        }
+
+        if (speed == 1000) {
+            if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1;
 #endif
-			}
-		} else if (speed == 100) {
-		    if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+            }
+        } else if (speed == 100) {
+            if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1;
 #endif
-			}
-		} else {
-		    if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+            }
+        } else {
+            if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1;
 #endif
-			} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+            } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
 #ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0;
-			    CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1;
+                CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1;
 #endif
-			}
-		}
-
-	    if (CrlApbDiv0 != 0 && CrlApbDiv1 != 0) {
-		#if EL1_NONSECURE
-		    XSmc_OutVar RegRead;
-		    RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
-							    0, 0, 0, 0, 0, 0);
-		    CrlApbGemCtrl = RegRead.Arg0 >> 32;
-		#else
-		    CrlApbGemCtrl = *(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr);
+            }
+        }
+
+        if (CrlApbDiv0 != 0 && CrlApbDiv1 != 0) {
+        #if EL1_NONSECURE
+            XSmc_OutVar RegRead;
+            RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+                                0, 0, 0, 0, 0, 0);
+            CrlApbGemCtrl = RegRead.Arg0 >> 32;
+        #else
+            CrlApbGemCtrl = *(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr);
         #endif
-		    CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
-		    CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
-		    CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
-		    CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
-		#if EL1_NONSECURE
-		    Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(CrlApbBaseAddr) | ((u64)(0xFFFFFFFF) << 32),
-				(u64)CrlApbGemCtrl, 0, 0, 0, 0, 0);
-		    do {
-		    RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
-			    0, 0, 0, 0, 0, 0);
-			} while((RegRead.Arg0 >> 32) != CrlApbGemCtrl);
-		#else
-			*(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr) = CrlApbGemCtrl;
+            CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
+            CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
+            CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
+            CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
+        #if EL1_NONSECURE
+            Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(CrlApbBaseAddr) | ((u64)(0xFFFFFFFF) << 32),
+                (u64)CrlApbGemCtrl, 0, 0, 0, 0, 0);
+            do {
+            RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+                0, 0, 0, 0, 0, 0);
+            } while((RegRead.Arg0 >> 32) != CrlApbGemCtrl);
+        #else
+            *(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr) = CrlApbGemCtrl;
         #endif
-		} else {
-		    xil_printf("Clock Divisors incorrect - Please check\r\n");
-		}
-	} else if (gigeversion == GEM_VERSION_VERSAL) {
-		/* Setup divisors in CRL for Versal */
-	    if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
-		    CrlApbBaseAddr = VERSAL_CRL_GEM0_REF_CTRL;
+        } else {
+            xil_printf("Clock Divisors incorrect - Please check\r\n");
+        }
+    } else if (gigeversion == GEM_VERSION_VERSAL) {
+        /* Setup divisors in CRL for Versal */
+        if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+            CrlApbBaseAddr = VERSAL_CRL_GEM0_REF_CTRL;
 #if EL1_NONSECURE
-		    ClkId = CLK_GEM0_REF;
+            ClkId = CLK_GEM0_REF;
 #endif
-		} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
-		    CrlApbBaseAddr = VERSAL_CRL_GEM1_REF_CTRL;
+        } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+            CrlApbBaseAddr = VERSAL_CRL_GEM1_REF_CTRL;
 #if EL1_NONSECURE
-		    ClkId = CLK_GEM1_REF;
+            ClkId = CLK_GEM1_REF;
 #endif
-		}
+        }
 
-	    if (speed == 1000) {
-		    if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+        if (speed == 1000) {
+            if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
 #endif
-			} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
 #endif
-			}
-		} else if (speed == 100) {
-		    if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+            }
+        } else if (speed == 100) {
+            if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
 #endif
-			} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
 #endif
-			}
-		} else {
-		    if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+            }
+        } else {
+            if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
 #endif
-			} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+            } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
 #ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
-			    CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+                CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
 #endif
-			}
-		}
+            }
+        }
 
-	    if (CrlApbDiv0 != 0) {
+        if (CrlApbDiv0 != 0) {
 #if EL1_NONSECURE
-		    Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)CrlApbDiv0 << 32) | ClkId), 0, 0, 0, 0, 0, 0);
+            Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)CrlApbDiv0 << 32) | ClkId), 0, 0, 0, 0, 0, 0);
 #else
-		    CrlApbGemCtrl = Xil_In32((UINTPTR)CrlApbBaseAddr);
-		    CrlApbGemCtrl &= ~VERSAL_CRL_GEM_DIV_MASK;
-		    CrlApbGemCtrl |= CrlApbDiv0 << VERSAL_CRL_APB_GEM_DIV_SHIFT;
+            CrlApbGemCtrl = Xil_In32((UINTPTR)CrlApbBaseAddr);
+            CrlApbGemCtrl &= ~VERSAL_CRL_GEM_DIV_MASK;
+            CrlApbGemCtrl |= CrlApbDiv0 << VERSAL_CRL_APB_GEM_DIV_SHIFT;
 
-		    Xil_Out32((UINTPTR)CrlApbBaseAddr, CrlApbGemCtrl);
+            Xil_Out32((UINTPTR)CrlApbBaseAddr, CrlApbGemCtrl);
 #endif
-		} else {
-		    xil_printf("Clock Divisors incorrect - Please check\r\n");
-		}
-	}
+        } else {
+            xil_printf("Clock Divisors incorrect - Please check\r\n");
+        }
+    }
 
     return;
 }

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c

@@ -44,14 +44,14 @@ pq_create_queue()
     pq_queue_t *q = NULL;
 
     if (i >= NUM_QUEUES) {
-	    xil_printf("ERR: Max Queues allocated\n\r");
-	    return q;
-	}
+        xil_printf("ERR: Max Queues allocated\n\r");
+        return q;
+    }
 
     q = &pq_queue[i++];
 
     if (!q)
-	    return q;
+        return q;
 
     q->head = q->tail = q->len = 0;
 
@@ -62,7 +62,7 @@ int
 pq_enqueue(pq_queue_t *q, void *p)
 {
     if (q->len == PQ_QUEUE_SIZE)
-	    return -1;
+        return -1;
 
     q->data[q->head] = p;
     q->head = (q->head + 1)%PQ_QUEUE_SIZE;
@@ -77,7 +77,7 @@ pq_dequeue(pq_queue_t *q)
     int ptail;
 
     if (q->len == 0)
-	    return NULL;
+        return NULL;
 
     ptail = q->tail;
     q->tail = (q->tail + 1)%PQ_QUEUE_SIZE;

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c

@@ -2,14 +2,14 @@
 #include "xparameters.h"
 
 struct xtopology_t xtopology[] = {
-	{
-	    0xFF0E0000,
-	    xemac_type_emacps,
-	    0x0,
-	    0x0,
-	    0xF8F00100,
-	    XPAR_XEMACPS_3_INTR,
-	},
+    {
+        0xFF0E0000,
+        xemac_type_emacps,
+        0x0,
+        0x0,
+        0xF8F00100,
+        XPAR_XEMACPS_3_INTR,
+    },
 };
 
 int xtopology_n_emacs = 1;

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h

@@ -20,7 +20,7 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00     pkp  	 05/29/14 First release
+* 5.00     pkp       05/29/14 First release
 * 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
 *                         ARM processors
 * 7.20  har      01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
@@ -132,7 +132,7 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
 static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 {
     volatile u8 *LocalAddr = (volatile u8 *)Addr;
-	*LocalAddr = Value;
+    *LocalAddr = Value;
 }
 
 /*****************************************************************************/
@@ -150,7 +150,7 @@ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 {
     volatile u16 *LocalAddr = (volatile u16 *)Addr;
-	*LocalAddr = Value;
+    *LocalAddr = Value;
 }
 
 /*****************************************************************************/
@@ -170,7 +170,7 @@ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 {
 #ifndef ENABLE_SAFETY
     volatile u32 *LocalAddr = (volatile u32 *)Addr;
-	*LocalAddr = Value;
+    *LocalAddr = Value;
 #else
     XStl_RegUpdate(Addr, Value);
 #endif
@@ -191,7 +191,7 @@ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
 {
     volatile u64 *LocalAddr = (volatile u64 *)Addr;
-	*LocalAddr = Value;
+    *LocalAddr = Value;
 }
 
 #ifdef __cplusplus

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h

@@ -13,4 +13,4 @@ extern "C" {
 }
 #endif
 
-#endif	/* end of protection macro */
+#endif    /* end of protection macro */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h

@@ -1,5 +1,5 @@
-#ifndef XIL_TYPES_H	/* prevent circular inclusions */
-#define XIL_TYPES_H	/* by using protection macros */
+#ifndef XIL_TYPES_H    /* prevent circular inclusions */
+#define XIL_TYPES_H    /* by using protection macros */
 
 #include <rtdef.h>
 #include <stdint.h>
@@ -12,25 +12,25 @@ extern "C" {
 /************************** Constant Definitions *****************************/
 
 #ifndef TRUE
-#  define TRUE	    1U
+#  define TRUE        1U
 #endif
 
 #ifndef FALSE
-#  define FALSE	    0U
+#  define FALSE        0U
 #endif
 
 #ifndef NULL
-#define NULL	    0U
+#define NULL        0U
 #endif
 
 #define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
                                                  assigend to "IsReady" member of driver
-												 instance to indicate that driver
-												 instance is initialized and ready to use. */
+                                                 instance to indicate that driver
+                                                 instance is initialized and ready to use. */
 #define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
                                                  "IsStarted" member of driver instance
-												 to indicate that driver instance is
-												 started and it can be enabled. */
+                                                 to indicate that driver instance is
+                                                 started and it can be enabled. */
 
 typedef rt_uint8_t u8;
 typedef rt_uint16_t u16;
@@ -55,7 +55,7 @@ typedef unsigned long ULONG;
 #endif
 
 #define ULONG64_HI_MASK    0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+#define ULONG64_LO_MASK    ~ULONG64_HI_MASK
 
 /** @{ */
 /**
@@ -73,15 +73,15 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 /************************** Constant Definitions *****************************/
 
 #ifndef TRUE
-#define TRUE	    1U
+#define TRUE        1U
 #endif
 
 #ifndef FALSE
-#define FALSE	    0U
+#define FALSE        0U
 #endif
 
 #ifndef NULL
-#define NULL	    0U
+#define NULL        0U
 #endif
 
 #ifdef __cplusplus
@@ -93,7 +93,7 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 }
 #endif
 
-#endif	/* end of protection macro */
+#endif    /* end of protection macro */
 /**
 * @} End of "addtogroup common_types".
 */

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h

@@ -48,103 +48,103 @@ extern "C" {
  */
 
 /* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR	    0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR	    0x3FFFFFFFU
+#define XPAR_DDR_MEM_BASEADDR        0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR        0x3FFFFFFFU
 
 /* Canonical definitions for Interrupts  */
-#define XPAR_XUARTPS_0_INTR	    XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR	    XPS_UART1_INT_ID
-#define XPAR_XIICPS_0_INTR	    XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR	    XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR	    XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR	    XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR	    XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR	    XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR	    XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR	    XPS_GEM0_INT_ID
+#define XPAR_XUARTPS_0_INTR        XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR        XPS_UART1_INT_ID
+#define XPAR_XIICPS_0_INTR        XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR        XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR        XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR        XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR        XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR        XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR        XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR        XPS_GEM0_INT_ID
 #define XPAR_XEMACPS_0_WAKE_INTR    XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR	    XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_INTR        XPS_GEM1_INT_ID
 #define XPAR_XEMACPS_1_WAKE_INTR    XPS_GEM1_WAKE_INT_ID
-#define XPAR_XEMACPS_2_INTR	    XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_INTR        XPS_GEM2_INT_ID
 #define XPAR_XEMACPS_2_WAKE_INTR    XPS_GEM2_WAKE_INT_ID
-#define XPAR_XEMACPS_3_INTR	    XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_INTR        XPS_GEM3_INT_ID
 #define XPAR_XEMACPS_3_WAKE_INTR    XPS_GEM3_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR	    XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR	    XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR	    XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR	    XPS_CSU_WDT_INT_ID
-#define XPAR_XWDTPS_1_INTR	    XPS_LPD_SWDT_INT_ID
-#define XPAR_XWDTPS_2_INTR	    XPS_FPD_SWDT_INT_ID
-#define XPAR_XDCFG_0_INTR	    XPS_DVC_INT_ID
-#define XPAR_XTTCPS_0_INTR	    XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR	    XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR	    XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR	    XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR	    XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR	    XPS_TTC1_2_INT_ID
-#define XPAR_XTTCPS_6_INTR	    XPS_TTC2_0_INT_ID
-#define XPAR_XTTCPS_7_INTR	    XPS_TTC2_1_INT_ID
-#define XPAR_XTTCPS_8_INTR	    XPS_TTC2_2_INT_ID
-#define XPAR_XTTCPS_9_INTR	    XPS_TTC3_0_INT_ID
-#define XPAR_XTTCPS_10_INTR	    XPS_TTC3_1_INT_ID
-#define XPAR_XTTCPS_11_INTR	    XPS_TTC3_2_INT_ID
+#define XPAR_XSDIOPS_0_INTR        XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR        XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR        XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR        XPS_CSU_WDT_INT_ID
+#define XPAR_XWDTPS_1_INTR        XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_2_INTR        XPS_FPD_SWDT_INT_ID
+#define XPAR_XDCFG_0_INTR        XPS_DVC_INT_ID
+#define XPAR_XTTCPS_0_INTR        XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR        XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR        XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR        XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR        XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR        XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR        XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR        XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR        XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR        XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR        XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR        XPS_TTC3_2_INT_ID
 #define XPAR_XNANDPS8_0_INTR            XPS_NAND_INT_ID
-#define XPAR_XADMAPS_0_INTR 	    XPS_ADMA_CH0_INT_ID
-#define XPAR_XADMAPS_1_INTR 	    XPS_ADMA_CH1_INT_ID
-#define XPAR_XADMAPS_2_INTR	    XPS_ADMA_CH2_INT_ID
-#define XPAR_XADMAPS_3_INTR 	    XPS_ADMA_CH3_INT_ID
-#define XPAR_XADMAPS_4_INTR	    XPS_ADMA_CH4_INT_ID
-#define XPAR_XADMAPS_5_INTR 	    XPS_ADMA_CH5_INT_ID
-#define XPAR_XADMAPS_6_INTR 	    XPS_ADMA_CH6_INT_ID
-#define XPAR_XADMAPS_7_INTR 	    XPS_ADMA_CH7_INT_ID
-#define XPAR_XCSUDMA_INTR 	    XPS_CSU_DMA_INT_ID
-#define XPAR_PSU_ADMA_0_INTR 	    XPS_ADMA_CH0_INT_ID
-#define XPAR_PSU_ADMA_1_INTR 	    XPS_ADMA_CH1_INT_ID
-#define XPAR_PSU_ADMA_2_INTR	    XPS_ADMA_CH2_INT_ID
-#define XPAR_PSU_ADMA_3_INTR 	    XPS_ADMA_CH3_INT_ID
-#define XPAR_PSU_ADMA_4_INTR	    XPS_ADMA_CH4_INT_ID
-#define XPAR_PSU_ADMA_5_INTR 	    XPS_ADMA_CH5_INT_ID
-#define XPAR_PSU_ADMA_6_INTR 	    XPS_ADMA_CH6_INT_ID
-#define XPAR_PSU_ADMA_7_INTR 	    XPS_ADMA_CH7_INT_ID
-#define XPAR_PSU_CSUDMA_INTR 	    XPS_CSU_DMA_INT_ID
-#define XPAR_XMPU_LPD_INTR 	    XPS_XMPU_LPD_INT_ID
-#define XPAR_XZDMAPS_0_INTR	    XPS_ZDMA_CH0_INT_ID
-#define XPAR_XZDMAPS_1_INTR	    XPS_ZDMA_CH1_INT_ID
-#define XPAR_XZDMAPS_2_INTR 	    XPS_ZDMA_CH2_INT_ID
-#define XPAR_XZDMAPS_3_INTR 	    XPS_ZDMA_CH3_INT_ID
-#define XPAR_XZDMAPS_4_INTR	    XPS_ZDMA_CH4_INT_ID
-#define XPAR_XZDMAPS_5_INTR 	    XPS_ZDMA_CH5_INT_ID
-#define XPAR_XZDMAPS_6_INTR 	    XPS_ZDMA_CH6_INT_ID
-#define XPAR_XZDMAPS_7_INTR 	    XPS_ZDMA_CH7_INT_ID
-#define XPAR_PSU_GDMA_0_INTR	    XPS_ZDMA_CH0_INT_ID
-#define XPAR_PSU_GDMA_1_INTR	    XPS_ZDMA_CH1_INT_ID
-#define XPAR_PSU_GDMA_2_INTR 	    XPS_ZDMA_CH2_INT_ID
-#define XPAR_PSU_GDMA_3_INTR 	    XPS_ZDMA_CH3_INT_ID
-#define XPAR_PSU_GDMA_4_INTR	    XPS_ZDMA_CH4_INT_ID
-#define XPAR_PSU_GDMA_5_INTR 	    XPS_ZDMA_CH5_INT_ID
-#define XPAR_PSU_GDMA_6_INTR 	    XPS_ZDMA_CH6_INT_ID
-#define XPAR_PSU_GDMA_7_INTR 	    XPS_ZDMA_CH7_INT_ID
-#define XPAR_XMPU_FPD_INTR 	    XPS_XMPU_FPD_INT_ID
-#define XPAR_XCCI_FPD_INTR 	    XPS_FPD_CCI_INT_ID
-#define XPAR_XSMMU_FPD_INTR 	    XPS_FPD_SMMU_INT_ID
-#define XPAR_XUSBPS_0_INTR	    XPS_USB3_0_ENDPT_INT_ID
-#define XPAR_XUSBPS_1_INTR	    XPS_USB3_1_ENDPT_INT_ID
-#define XPAR_XUSBPS_0_WAKE_INTR	    XPS_USB3_0_WAKE_INT_ID
-#define XPAR_XUSBPS_1_WAKE_INTR	    XPS_USB3_1_WAKE_INT_ID
+#define XPAR_XADMAPS_0_INTR         XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR         XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR        XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR         XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR        XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR         XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR         XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR         XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR         XPS_CSU_DMA_INT_ID
+#define XPAR_PSU_ADMA_0_INTR         XPS_ADMA_CH0_INT_ID
+#define XPAR_PSU_ADMA_1_INTR         XPS_ADMA_CH1_INT_ID
+#define XPAR_PSU_ADMA_2_INTR        XPS_ADMA_CH2_INT_ID
+#define XPAR_PSU_ADMA_3_INTR         XPS_ADMA_CH3_INT_ID
+#define XPAR_PSU_ADMA_4_INTR        XPS_ADMA_CH4_INT_ID
+#define XPAR_PSU_ADMA_5_INTR         XPS_ADMA_CH5_INT_ID
+#define XPAR_PSU_ADMA_6_INTR         XPS_ADMA_CH6_INT_ID
+#define XPAR_PSU_ADMA_7_INTR         XPS_ADMA_CH7_INT_ID
+#define XPAR_PSU_CSUDMA_INTR         XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR         XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR        XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR        XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR         XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR         XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR        XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR         XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR         XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR         XPS_ZDMA_CH7_INT_ID
+#define XPAR_PSU_GDMA_0_INTR        XPS_ZDMA_CH0_INT_ID
+#define XPAR_PSU_GDMA_1_INTR        XPS_ZDMA_CH1_INT_ID
+#define XPAR_PSU_GDMA_2_INTR         XPS_ZDMA_CH2_INT_ID
+#define XPAR_PSU_GDMA_3_INTR         XPS_ZDMA_CH3_INT_ID
+#define XPAR_PSU_GDMA_4_INTR        XPS_ZDMA_CH4_INT_ID
+#define XPAR_PSU_GDMA_5_INTR         XPS_ZDMA_CH5_INT_ID
+#define XPAR_PSU_GDMA_6_INTR         XPS_ZDMA_CH6_INT_ID
+#define XPAR_PSU_GDMA_7_INTR         XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR         XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR         XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR         XPS_FPD_SMMU_INT_ID
+#define XPAR_XUSBPS_0_INTR        XPS_USB3_0_ENDPT_INT_ID
+#define XPAR_XUSBPS_1_INTR        XPS_USB3_1_ENDPT_INT_ID
+#define XPAR_XUSBPS_0_WAKE_INTR        XPS_USB3_0_WAKE_INT_ID
+#define XPAR_XUSBPS_1_WAKE_INTR        XPS_USB3_1_WAKE_INT_ID
 #define    XPAR_XRTCPSU_ALARM_INTR     XPS_RTC_ALARM_INT_ID
 #define    XPAR_XRTCPSU_SECONDS_INTR    XPS_RTC_SEC_INT_ID
-#define XPAR_XAPMPS_0_INTR	    XPS_APM0_INT_ID
-#define XPAR_XAPMPS_1_INTR	    XPS_APM1_INT_ID
-#define XPAR_XAPMPS_2_INTR	    XPS_APM2_INT_ID
-#define XPAR_XAPMPS_5_INTR	    XPS_APM5_INT_ID
-#define XPAR_XSYSMONPSU_INTR	    XPS_AMS_INT_ID
+#define XPAR_XAPMPS_0_INTR        XPS_APM0_INT_ID
+#define XPAR_XAPMPS_1_INTR        XPS_APM1_INT_ID
+#define XPAR_XAPMPS_2_INTR        XPS_APM2_INT_ID
+#define XPAR_XAPMPS_5_INTR        XPS_APM5_INT_ID
+#define XPAR_XSYSMONPSU_INTR        XPS_AMS_INT_ID
 
 /* Canonical definitions for SCU GIC */
 #define XPAR_SCUGIC_NUM_INSTANCES    1U
 #define XPAR_SCUGIC_SINGLE_DEVICE_ID    0U
-#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
-#define XPAR_SCUGIC_ACK_BEFORE	    0U
+#define XPAR_SCUGIC_CPU_BASEADDR    (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_DIST_BASEADDR    (XPS_SCU_PERIPH_BASE + 0x00002000U)
+#define XPAR_SCUGIC_ACK_BEFORE        0U
 
 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
 
@@ -155,97 +155,97 @@ extern "C" {
  */
 
 #define XPS_SYS_CTRL_BASEADDR    0xFF180000U
-#define XPS_SCU_PERIPH_BASE	    0xF9000000U
+#define XPS_SCU_PERIPH_BASE        0xF9000000U
 
 
 /* Shared Peripheral Interrupts (SPI) */
-#define XPS_FPGA0_INT_ID	    121U
-#define XPS_FPGA1_INT_ID	    122U
-#define XPS_FPGA2_INT_ID	    123U
-#define XPS_FPGA3_INT_ID	    124U
-#define XPS_FPGA4_INT_ID	    125U
-#define XPS_FPGA5_INT_ID	    126U
-#define XPS_FPGA6_INT_ID	    127U
-#define XPS_FPGA7_INT_ID	    128U
-#define XPS_FPGA8_INT_ID	    136U
-#define XPS_FPGA9_INT_ID	    137U
-#define XPS_FPGA10_INT_ID	    138U
-#define XPS_FPGA11_INT_ID	    139U
-#define XPS_FPGA12_INT_ID	    140U
-#define XPS_FPGA13_INT_ID	    141U
-#define XPS_FPGA14_INT_ID	    142U
-#define XPS_FPGA15_INT_ID	    143U
+#define XPS_FPGA0_INT_ID        121U
+#define XPS_FPGA1_INT_ID        122U
+#define XPS_FPGA2_INT_ID        123U
+#define XPS_FPGA3_INT_ID        124U
+#define XPS_FPGA4_INT_ID        125U
+#define XPS_FPGA5_INT_ID        126U
+#define XPS_FPGA6_INT_ID        127U
+#define XPS_FPGA7_INT_ID        128U
+#define XPS_FPGA8_INT_ID        136U
+#define XPS_FPGA9_INT_ID        137U
+#define XPS_FPGA10_INT_ID        138U
+#define XPS_FPGA11_INT_ID        139U
+#define XPS_FPGA12_INT_ID        140U
+#define XPS_FPGA13_INT_ID        141U
+#define XPS_FPGA14_INT_ID        142U
+#define XPS_FPGA15_INT_ID        143U
 
 /* Updated Interrupt-IDs */
-#define XPS_OCMINTR_INT_ID		(10U + 32U)
-#define XPS_NAND_INT_ID        		(14U + 32U)
-#define XPS_QSPI_INT_ID			(15U + 32U)
-#define XPS_GPIO_INT_ID			(16U + 32U)
-#define XPS_I2C0_INT_ID			(17U + 32U)
-#define XPS_I2C1_INT_ID			(18U + 32U)
-#define XPS_SPI0_INT_ID			(19U + 32U)
-#define XPS_SPI1_INT_ID			(20U + 32U)
-#define XPS_UART0_INT_ID		(21U + 32U)
-#define XPS_UART1_INT_ID		(22U + 32U)
-#define XPS_CAN0_INT_ID			(23U + 32U)
-#define XPS_CAN1_INT_ID			(24U + 32U)
-#define    XPS_RTC_ALARM_INT_ID 	(26U + 32U)
-#define    XPS_RTC_SEC_INT_ID	 	(27U + 32U)
-#define XPS_LPD_SWDT_INT_ID		(52U + 32U)
-#define XPS_CSU_WDT_INT_ID	    (53U + 32U)
-#define XPS_FPD_SWDT_INT_ID		(113U + 32U)
-#define XPS_TTC0_0_INT_ID		(36U + 32U)
-#define XPS_TTC0_1_INT_ID		(37U + 32U)
-#define XPS_TTC0_2_INT_ID 		(38U + 32U)
-#define XPS_TTC1_0_INT_ID		(39U + 32U)
-#define XPS_TTC1_1_INT_ID		(40U + 32U)
-#define XPS_TTC1_2_INT_ID		(41U + 32U)
-#define XPS_TTC2_0_INT_ID		(42U + 32U)
-#define XPS_TTC2_1_INT_ID		(43U + 32U)
-#define XPS_TTC2_2_INT_ID		(44U + 32U)
-#define XPS_TTC3_0_INT_ID		(45U + 32U)
-#define XPS_TTC3_1_INT_ID		(46U + 32U)
-#define XPS_TTC3_2_INT_ID		(47U + 32U)
-#define XPS_SDIO0_INT_ID		(48U + 32U)
-#define XPS_SDIO1_INT_ID		(49U + 32U)
-#define XPS_AMS_INT_ID			(56U + 32U)
-#define XPS_GEM0_INT_ID			(57U + 32U)
-#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
-#define XPS_GEM1_INT_ID			(59U + 32U)
-#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
-#define XPS_GEM2_INT_ID			(61U + 32U)
-#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
-#define XPS_GEM3_INT_ID			(63U + 32U)
-#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
-#define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
-#define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
-#define XPS_USB3_0_WAKE_INT_ID		(75U + 32U)
-#define XPS_USB3_1_WAKE_INT_ID		(76U + 32U)
-#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
-#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
-#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
-#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
-#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
-#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
-#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
-#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
-#define XPS_CSU_DMA_INT_ID		(86U + 32U)
-#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
-#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
-#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
-#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
-#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
-#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
-#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
-#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
-#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
-#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
-#define XPS_FPD_CCI_INT_ID		(154U + 32U)
-#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
-#define XPS_APM0_INT_ID		(123U + 32U)
-#define XPS_APM1_INT_ID		(25U + 32U)
-#define XPS_APM2_INT_ID		(25U + 32U)
-#define XPS_APM5_INT_ID		(123U + 32U)
+#define XPS_OCMINTR_INT_ID        (10U + 32U)
+#define XPS_NAND_INT_ID                (14U + 32U)
+#define XPS_QSPI_INT_ID            (15U + 32U)
+#define XPS_GPIO_INT_ID            (16U + 32U)
+#define XPS_I2C0_INT_ID            (17U + 32U)
+#define XPS_I2C1_INT_ID            (18U + 32U)
+#define XPS_SPI0_INT_ID            (19U + 32U)
+#define XPS_SPI1_INT_ID            (20U + 32U)
+#define XPS_UART0_INT_ID        (21U + 32U)
+#define XPS_UART1_INT_ID        (22U + 32U)
+#define XPS_CAN0_INT_ID            (23U + 32U)
+#define XPS_CAN1_INT_ID            (24U + 32U)
+#define    XPS_RTC_ALARM_INT_ID     (26U + 32U)
+#define    XPS_RTC_SEC_INT_ID         (27U + 32U)
+#define XPS_LPD_SWDT_INT_ID        (52U + 32U)
+#define XPS_CSU_WDT_INT_ID        (53U + 32U)
+#define XPS_FPD_SWDT_INT_ID        (113U + 32U)
+#define XPS_TTC0_0_INT_ID        (36U + 32U)
+#define XPS_TTC0_1_INT_ID        (37U + 32U)
+#define XPS_TTC0_2_INT_ID         (38U + 32U)
+#define XPS_TTC1_0_INT_ID        (39U + 32U)
+#define XPS_TTC1_1_INT_ID        (40U + 32U)
+#define XPS_TTC1_2_INT_ID        (41U + 32U)
+#define XPS_TTC2_0_INT_ID        (42U + 32U)
+#define XPS_TTC2_1_INT_ID        (43U + 32U)
+#define XPS_TTC2_2_INT_ID        (44U + 32U)
+#define XPS_TTC3_0_INT_ID        (45U + 32U)
+#define XPS_TTC3_1_INT_ID        (46U + 32U)
+#define XPS_TTC3_2_INT_ID        (47U + 32U)
+#define XPS_SDIO0_INT_ID        (48U + 32U)
+#define XPS_SDIO1_INT_ID        (49U + 32U)
+#define XPS_AMS_INT_ID            (56U + 32U)
+#define XPS_GEM0_INT_ID            (57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID        (58U + 32U)
+#define XPS_GEM1_INT_ID            (59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID        (60U + 32U)
+#define XPS_GEM2_INT_ID            (61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID        (62U + 32U)
+#define XPS_GEM3_INT_ID            (63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID        (64U + 32U)
+#define XPS_USB3_0_ENDPT_INT_ID        (65U + 32U)
+#define XPS_USB3_1_ENDPT_INT_ID        (70U + 32U)
+#define XPS_USB3_0_WAKE_INT_ID        (75U + 32U)
+#define XPS_USB3_1_WAKE_INT_ID        (76U + 32U)
+#define XPS_ADMA_CH0_INT_ID        (77U + 32U)
+#define XPS_ADMA_CH1_INT_ID        (78U + 32U)
+#define XPS_ADMA_CH2_INT_ID        (79U + 32U)
+#define XPS_ADMA_CH3_INT_ID        (80U + 32U)
+#define XPS_ADMA_CH4_INT_ID        (81U + 32U)
+#define XPS_ADMA_CH5_INT_ID        (82U + 32U)
+#define XPS_ADMA_CH6_INT_ID        (83U + 32U)
+#define XPS_ADMA_CH7_INT_ID        (84U + 32U)
+#define XPS_CSU_DMA_INT_ID        (86U + 32U)
+#define XPS_XMPU_LPD_INT_ID        (88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID        (124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID        (125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID        (126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID        (127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID        (128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID        (129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID        (130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID        (131U + 32U)
+#define XPS_XMPU_FPD_INT_ID        (134U + 32U)
+#define XPS_FPD_CCI_INT_ID        (154U + 32U)
+#define XPS_FPD_SMMU_INT_ID        (155U + 32U)
+#define XPS_APM0_INT_ID        (123U + 32U)
+#define XPS_APM1_INT_ID        (25U + 32U)
+#define XPS_APM2_INT_ID        (25U + 32U)
+#define XPS_APM5_INT_ID        (123U + 32U)
 
 /* REDEFINES for TEST APP */
 #define XPAR_PSU_UART_0_INTR        XPS_UART0_INT_ID
@@ -268,7 +268,7 @@ extern "C" {
 #define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
 #define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
 #define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR    	    XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_0_INTR            XPS_LPD_SWDT_INT_ID
 #define XPAR_PSU_WDT_1_INTR         XPS_FPD_SWDT_INT_ID
 #define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
 #define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
@@ -277,32 +277,32 @@ extern "C" {
 #define XPAR_PSU_TTC_3_INTR         XPS_TTC1_0_INT_ID
 #define XPAR_PSU_TTC_4_INTR         XPS_TTC1_1_INT_ID
 #define XPAR_PSU_TTC_5_INTR         XPS_TTC1_2_INT_ID
-#define XPAR_PSU_TTC_6_INTR		    XPS_TTC2_0_INT_ID
-#define XPAR_PSU_TTC_7_INTR		    XPS_TTC2_1_INT_ID
-#define XPAR_PSU_TTC_8_INTR		    XPS_TTC2_2_INT_ID
-#define XPAR_PSU_TTC_9_INTR		    XPS_TTC3_0_INT_ID
-#define XPAR_PSU_TTC_10_INTR	    XPS_TTC3_1_INT_ID
-#define XPAR_PSU_TTC_11_INTR	    XPS_TTC3_2_INT_ID
-#define XPAR_PSU_AMS_INTR		    XPS_AMS_INT_ID
+#define XPAR_PSU_TTC_6_INTR            XPS_TTC2_0_INT_ID
+#define XPAR_PSU_TTC_7_INTR            XPS_TTC2_1_INT_ID
+#define XPAR_PSU_TTC_8_INTR            XPS_TTC2_2_INT_ID
+#define XPAR_PSU_TTC_9_INTR            XPS_TTC3_0_INT_ID
+#define XPAR_PSU_TTC_10_INTR        XPS_TTC3_1_INT_ID
+#define XPAR_PSU_TTC_11_INTR        XPS_TTC3_2_INT_ID
+#define XPAR_PSU_AMS_INTR            XPS_AMS_INT_ID
 
 #define XPAR_XADCPS_NUM_INSTANCES 1U
 #define XPAR_XADCPS_0_DEVICE_ID   0U
-#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
-#define XPAR_XADCPS_INT_ID	    XPS_SYSMON_INT_ID
+#define XPAR_XADCPS_0_BASEADDR      (0xF8007000U)
+#define XPAR_XADCPS_INT_ID        XPS_SYSMON_INT_ID
 
 /* For backwards compatibility */
-#define XPAR_XUARTPS_0_CLOCK_HZ	    XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ	    XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ	    XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ	    XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ	    XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ	    XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ	    XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ	    XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ	    XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ	    XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+#define XPAR_XUARTPS_0_CLOCK_HZ        XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ        XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ        XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ        XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ        XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ        XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ        XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ        XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ        XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ        XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
 
-#define XPAR_XQSPIPS_0_CLOCK_HZ	    XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+#define XPAR_XQSPIPS_0_CLOCK_HZ        XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
 
 #ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
@@ -312,7 +312,7 @@ extern "C" {
 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
 #endif
 
-#define XPAR_SCUWDT_DEVICE_ID	    0U
+#define XPAR_SCUWDT_DEVICE_ID        0U
 
 
 #ifdef __cplusplus

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h

@@ -1,5 +1,5 @@
-#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
-#define XPLATFORM_INFO_H		/* by using protection macros */
+#ifndef XPLATFORM_INFO_H        /* prevent circular inclusions */
+#define XPLATFORM_INFO_H        /* by using protection macros */
 
 #include "xil_types.h"
 #include "xparameters.h"
@@ -12,12 +12,12 @@ extern "C" {
 #define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
 #define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
 #define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
-								    XPAR_PMC_TAP_VERSION_OFFSET)
+                                    XPAR_PMC_TAP_VERSION_OFFSET)
 #else
 #define XPAR_CSU_BASEADDR 0xFFCA0000U
 #define    XPAR_CSU_VER_OFFSET 0x00000044U
 #define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
-								    XPAR_CSU_VER_OFFSET)
+                                    XPAR_CSU_VER_OFFSET)
 #endif
 #define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
 #define XPLAT_ZYNQ_ULTRA_MP 0x1

bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h

@@ -16,8 +16,8 @@
 * @{
 ******************************************************************************/
 
-#ifndef XSTATUS_H		/* prevent circular inclusions */
-#define XSTATUS_H		/* by using protection macros */
+#ifndef XSTATUS_H        /* prevent circular inclusions */
+#define XSTATUS_H        /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -42,53 +42,53 @@ extern "C" {
 #define XST_INVALID_VERSION             4L
 #define XST_DEVICE_IS_STARTED           5L
 #define XST_DEVICE_IS_STOPPED           6L
-#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
-						   operation with a FIFO such as
-						   an underrun or overrun, this
-						   error requires the device to
-						   be reset */
-#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
-						   the device to be reset */
-#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
-						   typically requires the device
-						   using the DMA to be reset */
-#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
-						   polled mode operation */
-#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
-						   the specified data into */
-#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
-						   to hold the expected data */
-#define XST_NO_DATA                     13L	/*!< There was no data available */
-#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
-						   expected value */
-#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
-						   into the function */
-#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
-						   scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
-#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
-						   registered */
-#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
-						   the requested feature */
-#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
-						   interrupt mode operation */
-#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
-#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
-						   have maxed out */
-#define XST_IS_STARTED                  23L	/*!< Used when part of device is
-						   already started i.e.
-						   sub channel */
-#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
-						   already stopped i.e.
-						   sub channel */
-#define XST_DATA_LOST                   26L	/*!< Driver defined error */
-#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
-#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
-#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
-						   available because it has not
-						   been enabled */
-#define XST_NO_ACCESS		    30L	/* Generic access error */
-#define XST_TIMEOUT                     31L	/*!< Event timeout occurred */
+#define XST_FIFO_ERROR                  7L    /*!< An error occurred during an
+                           operation with a FIFO such as
+                           an underrun or overrun, this
+                           error requires the device to
+                           be reset */
+#define XST_RESET_ERROR                 8L    /*!< An error occurred which requires
+                           the device to be reset */
+#define XST_DMA_ERROR                   9L    /*!< A DMA error occurred, this error
+                           typically requires the device
+                           using the DMA to be reset */
+#define XST_NOT_POLLED                  10L    /*!< The device is not configured for
+                           polled mode operation */
+#define XST_FIFO_NO_ROOM                11L    /*!< A FIFO did not have room to put
+                           the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L    /*!< The buffer is not large enough
+                           to hold the expected data */
+#define XST_NO_DATA                     13L    /*!< There was no data available */
+#define XST_REGISTER_ERROR              14L    /*!< A register did not contain the
+                           expected value */
+#define XST_INVALID_PARAM               15L    /*!< An invalid parameter was passed
+                           into the function */
+#define XST_NOT_SGDMA                   16L    /*!< The device is not configured for
+                           scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L    /*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L    /*!< A callback has not yet been
+                           registered */
+#define XST_NO_FEATURE                  19L    /*!< Device is not configured with
+                           the requested feature */
+#define XST_NOT_INTERRUPT               20L    /*!< Device is not configured for
+                           interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L    /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L    /*!< The error counters of a device
+                           have maxed out */
+#define XST_IS_STARTED                  23L    /*!< Used when part of device is
+                           already started i.e.
+                           sub channel */
+#define XST_IS_STOPPED                  24L    /*!< Used when part of device is
+                           already stopped i.e.
+                           sub channel */
+#define XST_DATA_LOST                   26L    /*!< Driver defined error */
+#define XST_RECV_ERROR                  27L    /*!< Generic receive error */
+#define XST_SEND_ERROR                  28L    /*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L    /*!< A requested service is not
+                           available because it has not
+                           been enabled */
+#define XST_NO_ACCESS            30L    /* Generic access error */
+#define XST_TIMEOUT                     31L    /*!< Event timeout occurred */
 
 /** @} */
 /***************** Utility Component statuses 401 - 500  *********************/
@@ -96,7 +96,7 @@ extern "C" {
 @name Utility Component Status Codes 401 - 500
 @{
 */
-#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+#define XST_MEMTEST_FAILED              401L    /*!< Memory test failed */
 
 /** @} */
 /***************** Common Components statuses 501 - 1000 *********************/
@@ -106,14 +106,14 @@ extern "C" {
 */
 /********************* Packet Fifo statuses 501 - 510 ************************/
 
-#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
-#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
-#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
-						   was invalid after reset */
-#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
-						 * empty and full simultaneously
-						 */
+#define XST_PFIFO_LACK_OF_DATA          501L    /*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L    /*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L    /*!< Self test, a register value
+                           was invalid after reset */
+#define XST_PFIFO_ERROR                 504L    /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L    /*!< Packet FIFO is reporting
+                         * empty and full simultaneously
+                         */
 /** @} */
 /**
 @name DMA Status Codes 511 - 530
@@ -121,44 +121,44 @@ extern "C" {
 */
 /************************** DMA statuses 511 - 530 ***************************/
 
-#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
-						   failed */
-#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
-						   was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
-						   no buffer descriptors ready
-						   to be processed */
-#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer descriptors of
-						   the scatter gather list are
-						   being used */
-#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
-						   descriptor which is to be
-						   copied over in the scatter
-						   list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
-						   put into the scatter gather
-						   list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
-						   specified was larger than the
-						   total # of buffer descriptors
-						   in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
-						   already been created */
-#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
-						   been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
-						   being started was not committed
-						   to the list */
-#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
-						   has already been used by the
-						   hardware so it can't be reused
-						 */
-#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
-						   error */
-#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
-						   error */
+#define XST_DMA_TRANSFER_ERROR          511L    /*!< Self test, DMA transfer
+                           failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L    /*!< Self test, a register value
+                           was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L    /*!< Scatter gather list contains
+                           no buffer descriptors ready
+                           to be processed */
+#define XST_DMA_SG_IS_STARTED           514L    /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L    /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L    /*!< All the buffer descriptors of
+                           the scatter gather list are
+                           being used */
+#define XST_DMA_SG_BD_LOCKED            518L    /*!< The scatter gather buffer
+                           descriptor which is to be
+                           copied over in the scatter
+                           list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L    /*!< No buffer descriptors have been
+                           put into the scatter gather
+                           list to be committed */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L    /*!< The packet count threshold
+                           specified was larger than the
+                           total # of buffer descriptors
+                           in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L    /*!< The scatter gather list has
+                           already been created */
+#define XST_DMA_SG_NO_LIST              523L    /*!< No scatter gather list has
+                           been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L    /*!< The buffer descriptor which was
+                           being started was not committed
+                           to the list */
+#define XST_DMA_SG_NO_DATA              525L    /*!< The buffer descriptor to start
+                           has already been used by the
+                           hardware so it can't be reused
+                         */
+#define XST_DMA_SG_LIST_ERROR           526L    /*!< General purpose list access
+                           error */
+#define XST_DMA_BD_ERROR                527L    /*!< General buffer descriptor
+                           error */
 /** @} */
 /**
 @name IPIF Status Codes Codes 531 - 550
@@ -166,34 +166,34 @@ extern "C" {
 */
 /************************** IPIF statuses 531 - 550 ***************************/
 
-#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
-						   was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
-						   reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
-						   register did not reset when
-						   acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
-						   register was not updated when
-						   other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
-						   did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
-						   not updated correctly when other
-						   registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
-						   register did not indicate the
-						   expected value */
-#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
-						   did not indicate the expected
-						   value */
-#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+#define XST_IPIF_REG_WIDTH_ERROR        531L    /*!< An invalid register width
+                           was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L    /*!< The value of a register at
+                           reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L    /*!< A write to the device interrupt
+                           status register did not read
+                           back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L    /*!< The device interrupt status
+                           register did not reset when
+                           acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L    /*!< The device interrupt enable
+                           register was not updated when
+                           other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L    /*!< A write to the IP interrupt
+                           status register did not read
+                           back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L    /*!< The IP interrupt status register
+                           did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L    /*!< IP interrupt enable register was
+                           not updated correctly when other
+                           registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L    /*!< The device interrupt pending
+                           register did not indicate the
+                           expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L    /*!< The device interrupt ID register
+                           did not indicate the expected
+                           value */
+#define XST_IPIF_ERROR                  541L    /*!< Generic ipif error */
 /** @} */
 
 /****************** Device specific statuses 1001 - 4095 *********************/
@@ -203,16 +203,16 @@ extern "C" {
 */
 /********************* Ethernet statuses 1001 - 1050 *************************/
 
-#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
-						 * to hold the minimum number of
-						 * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
-#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
-						 * collision on polled send */
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L    /*!< Memory space is not big enough
+                         * to hold the minimum number of
+                         * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L    /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L    /*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L    /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L    /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L    /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L    /*!< Excess deferral or late
+                         * collision on polled send */
 /** @} */
 /**
 @name UART Status Codes 1051 - 1075
@@ -235,30 +235,30 @@ extern "C" {
 */
 /************************ IIC statuses 1076 - 1100 ***************************/
 
-#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
-#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
-#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
-					     /* general call address        */
-#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
-					     /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
-					     /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
-					     /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
-					     /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
-					     /* didn't return written value */
-#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
-#define XST_IIC_ARB_LOST 			    1089 	/*!< Arbitration lost for master	*/
+#define XST_IIC_SELFTEST_FAILED         1076    /*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077    /*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078    /*!< mastersend attempted with   */
+                         /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079    /*!< A non parameterizable reg   */
+                         /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080    /*!< Tx fifo included in design  */
+                         /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081    /*!< Rx fifo included in design  */
+                         /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082    /*!< 10 bit addr incl in design  */
+                         /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083    /*!< Read of the control register */
+                         /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084    /*!< Read of the data Tx reg     */
+                         /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085    /*!< Read of the data Receive reg */
+                         /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086    /*!< Read of the data Tx reg     */
+                         /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087    /*!< Read of the 10 bit addr reg */
+                         /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088    /*!< The device isn't a slave    */
+#define XST_IIC_ARB_LOST                 1089     /*!< Arbitration lost for master    */
 /** @} */
 /**
 @name ATMC Status Codes 1101 - 1125
@@ -266,10 +266,10 @@ extern "C" {
 */
 /*********************** ATMC statuses 1101 - 1125 ***************************/
 
-#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
-						   controller hit the max value
-						   which requires the statistics
-						   to be cleared */
+#define XST_ATMC_ERROR_COUNT_MAX    1101L    /*!< the error counters in the ATM
+                           controller hit the max value
+                           which requires the statistics
+                           to be cleared */
 /** @} */
 /**
 @name Flash Status Codes 1126 - 1150
@@ -277,31 +277,31 @@ extern "C" {
 */
 /*********************** Flash statuses 1126 - 1150 **************************/
 
-#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
-						 */
-#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
-#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
-						   error. Use XFlash_DeviceControl
-						   to retrieve device specific codes
-						 */
-#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
-						 */
-#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
-						 */
-#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
-						   driver */
-#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
-						   aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
-						   addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
-						   write/erase function with
-						   XFL_NON_BLOCKING_WRITE/ERASE
-						   option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+#define XST_FLASH_BUSY                1126L    /*!< Flash is erasing or programming
+                         */
+#define XST_FLASH_READY               1127L    /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L    /*!< Flash had detected an internal
+                           error. Use XFlash_DeviceControl
+                           to retrieve device specific codes
+                         */
+#define XST_FLASH_ERASE_SUSPENDED     1129L    /*!< Flash is in suspended erase state
+                         */
+#define XST_FLASH_WRITE_SUSPENDED     1130L    /*!< Flash is in suspended write state
+                         */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L    /*!< Flash type not supported by
+                           driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L    /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L    /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L    /*!< Programming or erase operation
+                           aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L    /*!< Accessed flash outside its
+                           addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L    /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L    /*!< Couldn't return immediately from
+                           write/erase function with
+                           XFL_NON_BLOCKING_WRITE/ERASE
+                           option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L    /*!< Failed to query the device */
 /** @} */
 /**
 @name SPI Status Codes 1151 - 1175
@@ -309,23 +309,23 @@ extern "C" {
 */
 /*********************** SPI statuses 1151 - 1175 ****************************/
 
-#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
-						 * selected */
-#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
-						 */
-#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_MODE_FAULT          1151    /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152    /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153    /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154    /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155    /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156    /*!< more than one slave is being
+                         * selected */
+#define XST_SPI_NOT_MASTER          1157    /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158    /*!< device is configured as slave-only
+                         */
+#define XST_SPI_SLAVE_MODE_FAULT    1159    /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160    /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161    /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162    /*!< unrecognised command - qspi only */
 #define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
-						   device for status */
+                           device for status */
 /** @} */
 /**
 @name OPB Arbiter Status Codes 1176 - 1200
@@ -333,23 +333,23 @@ extern "C" {
 */
 /********************** OPB Arbiter statuses 1176 - 1200 *********************/
 
-#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
-						 * one master assigned to two or more
-						 * priorities, or one master not
-						 * assigned to any priority
-						 */
-#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
-						 * priority levels without first
-						 * suspending the use of priority
-						 * levels
-						 */
-#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
-						 * bus parking was not enabled
-						 */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
-						 * priority mode to allow the
-						 * priorities to be changed
-						 */
+#define XST_OPBARB_INVALID_PRIORITY  1176    /*!< the priority registers have either
+                         * one master assigned to two or more
+                         * priorities, or one master not
+                         * assigned to any priority
+                         */
+#define XST_OPBARB_NOT_SUSPENDED     1177    /*!< an attempt was made to modify the
+                         * priority levels without first
+                         * suspending the use of priority
+                         * levels
+                         */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178    /*!< bus parking by id was enabled but
+                         * bus parking was not enabled
+                         */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179    /*!< the arbiter must be in fixed
+                         * priority mode to allow the
+                         * priorities to be changed
+                         */
 /** @} */
 /**
 @name INTC Status Codes 1201 - 1225
@@ -357,8 +357,8 @@ extern "C" {
 */
 /************************ Intc statuses 1201 - 1225 **************************/
 
-#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
-#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+#define XST_INTC_FAIL_SELFTEST      1201    /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202    /*!< interrupt already in use */
 /** @} */
 /**
 @name TmrCtr Status Codes 1226 - 1250
@@ -366,7 +366,7 @@ extern "C" {
 */
 /********************** TmrCtr statuses 1226 - 1250 **************************/
 
-#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+#define XST_TMRCTR_TIMER_FAILED     1226    /*!< self test failed */
 /** @} */
 /**
 @name WdtTb Status Codes 1251 - 1275
@@ -406,7 +406,7 @@ extern "C" {
 */
 /********************** SysAce statuses 1351 - 1360 **************************/
 
-#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+#define XST_SYSACE_NO_LOCK          1351L    /*!< No MPU lock has been granted */
 /** @} */
 /**
 @name PCI Bridge Status Codes 1361 - 1375
@@ -422,10 +422,10 @@ extern "C" {
 */
 /********************** FlexRay constants 1400 - 1409 *************************/
 
-#define XST_FR_TX_ERROR		    1400
-#define XST_FR_TX_BUSY		    1401
-#define XST_FR_BUF_LOCKED	    1402
-#define XST_FR_NO_BUF		    1403
+#define XST_FR_TX_ERROR            1400
+#define XST_FR_TX_BUSY            1401
+#define XST_FR_BUF_LOCKED        1402
+#define XST_FR_NO_BUF            1403
 /** @} */
 /**
 @name USB constants 1410 - 1420
@@ -434,10 +434,10 @@ extern "C" {
 /****************** USB constants 1410 - 1420  *******************************/
 
 #define XST_USB_ALREADY_CONFIGURED    1410
-#define XST_USB_BUF_ALIGN_ERROR	    1411
+#define XST_USB_BUF_ALIGN_ERROR        1411
 #define XST_USB_NO_DESC_AVAILABLE    1412
-#define XST_USB_BUF_TOO_BIG	    1413
-#define XST_USB_NO_BUF		    1414
+#define XST_USB_BUF_TOO_BIG        1413
+#define XST_USB_NO_BUF            1414
 /** @} */
 /**
 @name HWICAP constants 1421 - 1429
@@ -445,7 +445,7 @@ extern "C" {
 */
 /****************** HWICAP constants 1421 - 1429  *****************************/
 
-#define XST_HWICAP_WRITE_DONE	    1421
+#define XST_HWICAP_WRITE_DONE        1421
 
 /** @} */
 /**
@@ -454,7 +454,7 @@ extern "C" {
 */
 /****************** AXI VDMA constants 1430 - 1440  *****************************/
 
-#define XST_VDMA_MISMATCH_ERROR	    1430
+#define XST_VDMA_MISMATCH_ERROR        1430
 /** @} */
 /**
 @name NAND Flash Status Codes 1441 - 1459
@@ -462,36 +462,36 @@ extern "C" {
 */
 /*********************** NAND Flash statuses 1441 - 1459  *********************/
 
-#define XST_NAND_BUSY		    1441L	/*!< Flash is erasing or
-						 * programming
-						 */
-#define XST_NAND_READY		    1442L	/*!< Flash is ready for commands
-						 */
-#define XST_NAND_ERROR		    1443L	/*!< Flash had detected an
-						 * internal error.
-						 */
-#define XST_NAND_PART_NOT_SUPPORTED    1444L	/*!< Flash type not supported by
-						 * driver
-						 */
-#define XST_NAND_OPT_NOT_SUPPORTED    1445L	/*!< Operation not supported
-						 */
-#define XST_NAND_TIMEOUT_ERROR	    1446L	/*!< Programming or erase
-						 * operation aborted due to a
-						 * timeout
-						 */
-#define XST_NAND_ADDRESS_ERROR	    1447L	/*!< Accessed flash outside its
-						 * addressible range
-						 */
-#define XST_NAND_ALIGNMENT_ERROR    1448L	/*!< Write alignment error
-						 */
-#define XST_NAND_PARAM_PAGE_ERROR    1449L	/*!< Failed to read parameter
-						 * page of the device
-						 */
-#define XST_NAND_CACHE_ERROR	    1450L	/*!< Flash page buffer error
-						 */
-
-#define XST_NAND_WRITE_PROTECTED    1451L	/*!< Flash is write protected
-						 */
+#define XST_NAND_BUSY            1441L    /*!< Flash is erasing or
+                         * programming
+                         */
+#define XST_NAND_READY            1442L    /*!< Flash is ready for commands
+                         */
+#define XST_NAND_ERROR            1443L    /*!< Flash had detected an
+                         * internal error.
+                         */
+#define XST_NAND_PART_NOT_SUPPORTED    1444L    /*!< Flash type not supported by
+                         * driver
+                         */
+#define XST_NAND_OPT_NOT_SUPPORTED    1445L    /*!< Operation not supported
+                         */
+#define XST_NAND_TIMEOUT_ERROR        1446L    /*!< Programming or erase
+                         * operation aborted due to a
+                         * timeout
+                         */
+#define XST_NAND_ADDRESS_ERROR        1447L    /*!< Accessed flash outside its
+                         * addressible range
+                         */
+#define XST_NAND_ALIGNMENT_ERROR    1448L    /*!< Write alignment error
+                         */
+#define XST_NAND_PARAM_PAGE_ERROR    1449L    /*!< Failed to read parameter
+                         * page of the device
+                         */
+#define XST_NAND_CACHE_ERROR        1450L    /*!< Flash page buffer error
+                         */
+
+#define XST_NAND_WRITE_PROTECTED    1451L    /*!< Flash is write protected
+                         */
 /** @} */
 
 /**************************** Type Definitions *******************************/

bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c

@@ -184,9 +184,9 @@ static DSTATUS disk_initialize(
     if (CardDetect)
     {
         /*
-			 * Card detection check
-			 * If the HC detects the No Card State, power will be cleared
-			 */
+             * Card detection check
+             * If the HC detects the No Card State, power will be cleared
+             */
         while (!((XSDPS_PSR_CARD_DPL_MASK |
                   XSDPS_PSR_CARD_STABLE_MASK |
                   XSDPS_PSR_CARD_INSRT_MASK) ==
@@ -198,8 +198,8 @@ static DSTATUS disk_initialize(
     }
 
     /*
-	 * Initialize the host controller
-	 */
+     * Initialize the host controller
+     */
     SdConfig = XSdPs_LookupConfig((u16)pdrv);
     if (NULL == SdConfig)
     {
@@ -223,9 +223,9 @@ static DSTATUS disk_initialize(
     }
 
     /*
-	 * Disk is initialized.
-	 * Store the same in Stat.
-	 */
+     * Disk is initialized.
+     * Store the same in Stat.
+     */
     s &= (~STA_NOINIT);
 
     Stat[pdrv] = s;

bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c

@@ -21,7 +21,7 @@
 
 #define XUARTPS_MAX_RATE    921600U
 #define XUARTPS_MIN_RATE    110U
-#define XUARTPS_MAX_BAUD_ERROR_RATE     3U	/* max % error allowed */
+#define XUARTPS_MAX_BAUD_ERROR_RATE     3U    /* max % error allowed */
 
 #define ZynqMP_UART_INT_DISABLE(UART)       \
     (UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
@@ -92,12 +92,12 @@ static void rt_hw_uart_isr(int irqno, void *param)
 
 static rt_err_t XUartPsSetBandRate(struct hw_uart_device *pdev, rt_uint32_t targetBandRate)
 {
-    rt_uint32_t IterBAUDDIV;	/* Iterator for available baud divisor values */
-    rt_uint32_t BRGR_Value;		/* Calculated value for baud rate generator */
-    rt_uint32_t CalcBaudRate;	/* Calculated baud rate */
-    rt_uint32_t BaudError;		/* Diff between calculated and requested baud rate */
-    rt_uint32_t Best_BRGR = 0U;	/* Best value for baud rate generator */
-    rt_uint8_t Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+    rt_uint32_t IterBAUDDIV;    /* Iterator for available baud divisor values */
+    rt_uint32_t BRGR_Value;        /* Calculated value for baud rate generator */
+    rt_uint32_t CalcBaudRate;    /* Calculated baud rate */
+    rt_uint32_t BaudError;        /* Diff between calculated and requested baud rate */
+    rt_uint32_t Best_BRGR = 0U;    /* Best value for baud rate generator */
+    rt_uint8_t Best_BAUDDIV = 0U;    /* Best value for baud divisor */
     rt_uint32_t Best_Error = 0xFFFFFFFFU;
     rt_uint32_t PercentError;
     rt_uint32_t ModeReg;

bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h

@@ -9,8 +9,8 @@
 #define __REG8(x)  (*((volatile rt_uint8_t *)(x)))
 
 #define ZynqMP_CRL_APB_BASEADDR        XPAR_PSU_CRL_APB_S_AXI_BASEADDR
-#define ZynqMP_CRL_APB_IOPLL_CTRL	   0x020
-#define ZynqMP_CRL_APB_IOPLL_CFG	   0x024
+#define ZynqMP_CRL_APB_IOPLL_CTRL       0x020
+#define ZynqMP_CRL_APB_IOPLL_CFG       0x024
 #define ZynqMP_CRL_APB_UART0_REF_CTRL  0x074
 #define ZynqMP_CRL_APB_UART1_REF_CTRL  0x078
 #define ZynqMP_CRL_APB_LPD_LSBUS_CTRL  0x0AC

bsp/zynqmp-r5-axu4ev/rtconfig.py

@@ -9,8 +9,8 @@ if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
 # only support GNU GCC compiler
-PLATFORM 	= 'gcc'
-EXEC_PATH 	= '/opt/arm-none-eabi-gcc'
+PLATFORM     = 'gcc'
+EXEC_PATH     = '/opt/arm-none-eabi-gcc'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')