Add BSP for HPM6750EVK and HPM6750EVKMINI (#6374)

* Add CANFD support and correct typos

- Added CANFD required fields to can.h
- Fixed typos in can.h and can.c
- Corrected all the projects affected by the typo
- Fixed wrong line-ending in some affected can driver files

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

* update

* bsp: support boards from hpmicro

- Supported HPM6750EVKMINI
- Supported HPM6750EVK

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
Co-authored-by: Meco Man <920369182@qq.com>

bsp/hpmicro/hpm6750evk/.config

@@ -0,0 +1,714 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+CONFIG_RT_USING_LEGACY=y
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Sensor libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display libraries
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HPM6000=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART13 is not set
+# CONFIG_BSP_USING_UART14 is not set
+# CONFIG_BSP_USING_SPI is not set
+CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SDXC is not set
+# CONFIG_BSP_USING_TOUCH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_GPTMR is not set
+# CONFIG_BSP_USING_I2C is not set
+CONFIG_BSP_USING_DRAM=y
+CONFIG_INIT_EXT_RAM_FOR_DATA=y
+# CONFIG_BSP_USING_XPI_FLASH is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_DAO is not set
+# CONFIG_BSP_USING_PDM is not set
+# CONFIG_BSP_USING_I2S is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_WDG is not set
+# CONFIG_BSP_USING_CAN is not set

bsp/hpmicro/hpm6750evk/.settings/blink_led.OpenOCD.Debug.rttlaunch

@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-hpmicro_debugger_relative_path}/bin/openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f ${project_loc}/board/debug_scripts/openocd/probes/ft2232.cfg&#13;&#10;-f ${project_loc}/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg&#13;&#10;-f ${project_loc}/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${toolchain_install_path}/${risc-v-gcc-rv32_relative_path}/bin/${cross_prefix}gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${config_name}/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="blink_led"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/blink_led"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

bsp/hpmicro/hpm6750evk/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.512258282=${toolchain_install_path}/RISC-V/RISC-V-GCC-RV32/2022-04-12/bin

bsp/hpmicro/hpm6750evk/.settings/language.settings.xml

@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.576542909" name="flash_debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1420929001440872898" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.576542909.2015579467" name="ram_debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1472663581447918959" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8

bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

bsp/hpmicro/hpm6750evk/.settings/projcfg.ini

@@ -0,0 +1,19 @@
+#RT-Thread Studio Project Configuration
+#Thu Feb 17 15:17:36 CST 2022
+cfg_version=v3.0
+board_name=HPM6750EVKMINI
+example_name=blink_led
+hardware_adapter=FT2232
+project_type=rt-thread
+board_base_nano_proj=False
+chip_name=HPM6750
+selected_rtt_version=4.0.5
+bsp_version=0.3.0
+os_branch=full
+output_project_path=C\:/DevTools/RT-ThreadStudio/workspace
+is_base_example_project=True
+is_use_scons_build=True
+project_base_bsp=true
+project_name=blink_led
+os_version=4.0.5
+bsp_path=repo/Local/Board_Support_Packages/HPMicro/HPM6750EVKMINI/0.3.0(offline)/hpm6750-rtt-bsp

bsp/hpmicro/hpm6750evk/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hpmicro/hpm6750evk/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hpmicro/hpm6750evk/SConstruct

@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hpmicro/hpm6750evk/applications/SConscript

@@ -0,0 +1,14 @@
+import rtconfig
+
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('*.c')
+
+CPPDEFINES=[]
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evk/applications/main.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+
+void thread_entry(void *arg);
+
+
+
+int main(void)
+{
+
+    app_init_led_pins();
+
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    while(1){
+        app_led_write(0, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(0, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}

bsp/hpmicro/hpm6750evk/board/Kconfig

@@ -0,0 +1,379 @@
+menu "Hardware Drivers Config"
+
+config SOC_HPM6000
+    bool
+    select SOC_SERIES_HPM6000
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART0
+                bool "Enable UART0 (Debugger)"
+                default y
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_USING_DMA
+                        bool "Enable UART0 RX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_TX_USING_DMA
+                        bool "Enable UART0 TX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_RX_DMA_CHANNEL
+                        int "Set UART0 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART0_TX_DMA_CHANNEL
+                        int "Set UART0 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART0_RX_BUFSIZE
+                        int "Set UART0 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART0_TX_BUFSIZE
+                        int "Set UART0 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_USING_DMA
+                        bool "Enable UART6 RX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_TX_USING_DMA
+                        bool "Enable UART6 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_RX_DMA_CHANNEL
+                        int "Set UART6 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART6_TX_DMA_CHANNEL
+                        int "Set UART6 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART13
+                bool "Enable UART13"
+                default n
+                if BSP_USING_UART13
+                    config BSP_UART13_RX_USING_DMA
+                        bool "Enable UART13 RX DMA"
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART13_TX_USING_DMA
+                        bool "Enable UART13 TX DMA"
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART13_RX_DMA_CHANNEL
+                        int "Set UART13 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART13_TX_DMA_CHANNEL
+                        int "Set UART13 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART13_RX_BUFSIZE
+                        int "Set UART13 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART13_TX_BUFSIZE
+                        int "Set UART13 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART14
+                bool "Enable UART14"
+                default n
+                if BSP_USING_UART14
+                    config BSP_UART14_RX_USING_DMA
+                        bool "Enable UART14 RX DMA"
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART14_TX_USING_DMA
+                        bool "Enable UART14 TX DMA"
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART14_RX_DMA_CHANNEL
+                        int "Set UART14 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART14_TX_DMA_CHANNEL
+                        int "Set UART14 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART14_RX_BUFSIZE
+                        int "Set UART14 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART14_TX_BUFSIZE
+                        int "Set UART14 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+        
+
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                    default y
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                    default n
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_RTC
+       bool "Enable RTC"
+       default n
+
+    menuconfig BSP_USING_ETH
+       bool "Enable Ethernet"       
+       default n 
+       
+       select RT_USING_ETH
+       if BSP_USING_ETH
+       		choice 
+		prompt "ETH"			
+	    	config BSP_USING_ETH0
+	        bool "Enable ETH0"	  	
+	    		        	   
+	    	config BSP_USING_ETH1
+	        bool "Enable ETH1"			        	        
+	   	endchoice	
+       endif       
+	    	       	
+    menuconfig BSP_USING_SDXC
+        bool "Enable SDXC"
+        default n
+        select RT_USING_SDIO if BSP_USING_SDXC
+        if BSP_USING_SDXC
+            config BSP_USING_SDXC0
+                bool "Enable SDXC0"
+                    default n
+
+            config BSP_USING_SDXC1
+                bool "Enable SDXC1"
+                    default y
+        endif
+
+    menuconfig BSP_USING_TOUCH
+       bool "Enable touch"
+       default n
+        if BSP_USING_TOUCH
+            config BSP_USING_TOUCH_GT911
+                bool "Enable GT911"
+                    default y
+
+            config BSP_USING_TOUCH_FT5406
+                bool "Enable FT5406"
+                    default n
+        endif
+
+    menuconfig BSP_USING_LCD
+    	bool "Enable LCD"
+    	default n
+
+    menuconfig BSP_USING_LVGL
+        bool "Enable LVGL"
+        default n
+        select PKG_USING_LVGL if BSP_USING_LVGL
+
+    menuconfig BSP_USING_GPTMR
+	   	bool "Enable GPTMR"
+	   	default n
+	   	select RT_USING_HWTIMER if BSP_USING_GPTMR
+	   	if BSP_USING_GPTMR
+	   		config BSP_USING_GPTMR1
+	   			bool "Enable GPTMR1"
+	   			default n
+	   		config BSP_USING_GPTMR2
+	   			bool "Enable GPTMR2"
+	   			default n
+	   		config BSP_USING_GPTMR3
+	   			bool "Enable GPTMR3"
+	   			default n
+	   		config BSP_USING_GPTMR4
+	   			bool "Enable GPTMR4"
+	   			default n
+	   		config BSP_USING_GPTMR5
+	   			bool "Enable GPTMR5"
+	   			default n
+	   		config BSP_USING_GPTMR6
+	   			bool "Enable GPTMR6"
+	   			default n
+	   		config BSP_USING_GPTMR7
+	   			bool "Enable GPTMR7"
+	   			default n
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        select RT_USING_I2C if BSP_USING_I2C
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                    default y
+        endif
+
+    menuconfig BSP_USING_DRAM
+       bool "Enable DRAM"
+       default y
+    menuconfig INIT_EXT_RAM_FOR_DATA
+        bool "INIT_EXT_RAM_FOR_DATA"
+        default y
+        
+        
+    menuconfig BSP_USING_XPI_FLASH
+    	bool "Enable XPI FLASH"
+	default n 
+    	select PKG_USING_FAL if BSP_USING_XPI_FLASH
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+	default n
+
+    menuconfig BSP_USING_DAO
+        bool "Enable Audio DAO play"
+        default n
+        select RT_USING_AUDIO if BSP_USING_DAO
+
+    menuconfig BSP_USING_PDM
+        bool "Enable Audio PDM record"
+        default n
+        select RT_USING_AUDIO if BSP_USING_PDM
+
+    menuconfig BSP_USING_I2S
+        bool "Enable Audio I2S device"
+        default n
+        select RT_USING_AUDIO if BSP_USING_I2S
+        if BSP_USING_I2S
+            config BSP_USING_I2S0
+                bool "Enable I2S0"
+                    default y
+        endif
+
+    menuconfig BSP_USING_USB
+       bool "Enable USB"
+       default n
+       if BSP_USING_USB
+       		config BSP_USING_USB_DEVICE
+                bool "Enable USB Device"
+                    default n
+            config BSP_USING_USB_HOST
+                bool "Enable USB Host"
+                    default n
+       endif
+       
+     
+     menuconfig BSP_USING_WDG
+     	bool "Enable Watchdog"
+     	default n
+     	select RT_USING_WDT if BSP_USING_WDG
+     	if BSP_USING_WDG
+     		config BSP_USING_WDG0
+     			bool "Enable WDG0"
+     			default n
+     		config BSP_USING_WDG1
+     			bool "Enable WDG1"
+     			default n
+     		config BSP_USING_WDG2
+     			bool "Enable WDG2"
+     			default n
+     		config BSP_USING_WDG3
+     			bool "Enable WDG3"
+     			default n
+     	endif
+     		
+     menuconfig BSP_USING_CAN
+     	bool "Enable CAN"
+     	default n
+     	select RT_USING_CAN if BSP_USING_CAN
+     	if BSP_USING_CAN
+     		config BSP_USING_CAN0
+     			bool "Enable CAN0"
+     			default n
+     		config BSP_USING_CAN1
+     			bool "Enable CAN1"
+     			default n
+     		config BSP_USING_CAN2
+     			bool "Enable CAN2"
+     			default n
+     		config BSP_USING_CAN3
+     			bool "Enable CAN3"
+     			default n
+     endif
+endmenu
+
+
+
+endmenu

bsp/hpmicro/hpm6750evk/board/SConscript

@@ -0,0 +1,20 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    eth_phy_port.c
+    fal_flash_port.c
+    hpm_sgtl5000.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6750']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evk/board/board.c

@@ -0,0 +1,1026 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gptmr_drv.h"
+#include "hpm_lcdc_drv.h"
+#include "hpm_i2c_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_debug_console.h"
+#include "hpm_dram_drv.h"
+#include "pinmux.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include "hpm_sdxc_drv.h"
+#include "hpm_pwm_drv.h"
+#include "hpm_trgm_drv.h"
+#include "hpm_pllctl_drv.h"
+
+static board_timer_cb timer_cb;
+
+/**
+ * @brief FLASH configuration option definitions:
+ * option[0]:
+ *    [31:16] 0xfcf9 - FLASH configuration option tag
+ *    [15:4]  0 - Reserved
+ *    [3:0]   option words (exclude option[0])
+ * option[1]:
+ *    [31:28] Flash probe type
+ *      0 - SFDP SDR / 1 - SFDP DDR
+ *      2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+ *      4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+ *      6 - OctaBus DDR (SPI -> OPI DDR)
+ *      8 - Xccela DDR (SPI -> OPI DDR)
+ *      10 - EcoXiP DDR (SPI -> OPI DDR)
+ *    [27:24] Command Pads after Power-on Reset
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [23:20] Command Pads after Configuring FLASH
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+ *      0 - Not needed
+ *      1 - QE bit is at bit 6 in Status Register 1
+ *      2 - QE bit is at bit1 in Status Register 2
+ *      3 - QE bit is at bit7 in Status Register 2
+ *      4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+ *    [15:8] Dummy cycles
+ *      0 - Auto-probed / detected / default value
+ *      Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+ *    [7:4] Misc.
+ *      0 - Not used
+ *      1 - SPI mode
+ *      2 - Internal loopback
+ *      3 - External DQS
+ *    [3:0] Frequency option
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+ *
+ * option[2] (Effective only if the bit[3:0] in option[0] > 1)
+ *    [31:20]  Reserved
+ *    [19:16] IO voltage
+ *      0 - 3V / 1 - 1.8V
+ *    [15:12] Pin group
+ *      0 - 1st group / 1 - 2nd group
+ *    [11:8] Connection selection
+ *      0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+ *    [7:0] Drive Strength
+ *      0 - Default value
+ * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
+ *              JESD216)
+ *    [31:16] reserved
+ *    [15:12] Sector Erase Command Option, not required here
+ *    [11:8]  Sector Size Option, not required here
+ *    [7:0] Flash Size Option
+ *      0 - 4MB / 1 - 8MB / 2 - 16MB
+ */
+#if defined(FLASH_XIP) && FLASH_XIP
+__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0};
+#endif
+
+#if defined(FLASH_UF2) && FLASH_UF2
+ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+#endif
+
+void board_init_console(void)
+{
+#if BOARD_CONSOLE_TYPE == console_type_uart
+    console_config_t cfg;
+
+    /* Configure the UART clock to 24MHz */
+    clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
+
+    cfg.type = BOARD_CONSOLE_TYPE;
+    cfg.base = (uint32_t) BOARD_CONSOLE_BASE;
+    cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
+    cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
+
+    init_uart_pins((UART_Type *) cfg.base);
+
+    if (status_success != console_init(&cfg)) {
+        /* failed to  initialize debug console */
+        while (1) {
+        }
+    }
+#else
+    while(1);
+#endif
+}
+
+void board_print_clock_freq(void)
+{
+    printf("==============================\n");
+    printf(" %s clock summary\n", BOARD_NAME);
+    printf("==============================\n");
+    printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
+    printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1));
+    printf("axi0:\t\t %dHz\n", clock_get_frequency(clock_axi0));
+    printf("axi1:\t\t %dHz\n", clock_get_frequency(clock_axi1));
+    printf("axi2:\t\t %dHz\n", clock_get_frequency(clock_axi2));
+    printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb));
+    printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
+    printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1));
+    printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
+    printf("xpi1:\t\t %dHz\n", clock_get_frequency(clock_xpi1));
+    printf("dram:\t\t %dHz\n", clock_get_frequency(clock_dram));
+    printf("display:\t %dHz\n", clock_get_frequency(clock_display));
+    printf("cam0:\t\t %dHz\n", clock_get_frequency(clock_camera0));
+    printf("cam1:\t\t %dHz\n", clock_get_frequency(clock_camera1));
+    printf("jpeg:\t\t %dHz\n", clock_get_frequency(clock_jpeg));
+    printf("pdma:\t\t %dHz\n", clock_get_frequency(clock_pdma));
+    printf("==============================\n");
+}
+
+void board_init_uart(UART_Type *ptr)
+{
+    init_uart_pins(ptr);
+}
+
+void board_init_ahb(void)
+{
+    clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/
+}
+
+void board_print_banner(void)
+{
+    const uint8_t banner[] = {"\n\
+----------------------------------------------------------------------\n\
+$$\\   $$\\ $$$$$$$\\  $$\\      $$\\ $$\\\n\
+$$ |  $$ |$$  __$$\\ $$$\\    $$$ |\\__|\n\
+$$ |  $$ |$$ |  $$ |$$$$\\  $$$$ |$$\\  $$$$$$$\\  $$$$$$\\   $$$$$$\\\n\
+$$$$$$$$ |$$$$$$$  |$$\\$$\\$$ $$ |$$ |$$  _____|$$  __$$\\ $$  __$$\\\n\
+$$  __$$ |$$  ____/ $$ \\$$$  $$ |$$ |$$ /      $$ |  \\__|$$ /  $$ |\n\
+$$ |  $$ |$$ |      $$ |\\$  /$$ |$$ |$$ |      $$ |      $$ |  $$ |\n\
+$$ |  $$ |$$ |      $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ |      \\$$$$$$  |\n\
+\\__|  \\__|\\__|      \\__|     \\__|\\__| \\_______|\\__|       \\______/\n\
+----------------------------------------------------------------------\n"};
+    printf("%s", banner);
+}
+
+static void board_turnoff_rgb_led(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
+    HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
+    HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
+
+    HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
+}
+
+void board_ungate_mchtmr_at_lp_mode(void)
+{
+    /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
+    sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
+}
+
+void board_init(void)
+{
+    board_turnoff_rgb_led();
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+    board_init_ahb();
+#if BOARD_SHOW_CLOCK
+    board_print_clock_freq();
+#endif
+#if BOARD_SHOW_BANNER
+    board_print_banner();
+#endif
+}
+
+void board_init_sdram_pins(void)
+{
+    init_sdram_pins();
+}
+
+uint32_t board_init_dram_clock(void)
+{
+    clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */
+    /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */
+
+    return clock_get_frequency(clock_dram);
+}
+
+void board_power_cycle_lcd(void)
+{
+    /* turn off backlight */
+    gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN);
+    gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0);
+
+    board_delay_ms(150);
+    /* power recycle */
+    gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN);
+    gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0);
+    board_delay_ms(150);
+    gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1);
+    board_delay_ms(150);
+
+    /* turn on backlight */
+    gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1);
+
+}
+
+void board_init_lcd(void)
+{
+    board_init_lcd_clock();
+    init_lcd_pins(BOARD_LCD_BASE);
+
+    board_power_cycle_lcd();
+}
+
+void board_delay_ms(uint32_t ms)
+{
+    clock_cpu_delay_ms(ms);
+}
+
+void board_timer_isr(void)
+{
+    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
+        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
+        timer_cb();
+    }
+}
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
+
+void board_timer_create(uint32_t ms, board_timer_cb cb)
+{
+    uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    timer_cb = cb;
+    gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
+
+    clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
+    gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
+
+    config.reload = gptmr_freq / 1000 * ms;
+    gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
+    gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
+    intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
+
+    gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
+}
+
+void board_i2c_bus_clear(I2C_Type *ptr)
+{
+    init_i2c_pins_as_gpio(ptr);
+    if (ptr == BOARD_CAP_I2C_BASE) {
+        gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN);
+        gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
+        if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) {
+            printf("CLK is low, please power cycle the board\n");
+            while (1) {}
+        }
+        if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) {
+            printf("SDA is low, try to issue I2C bus clear\n");
+        } else {
+            printf("I2C bus is ready\n");
+            return;
+        }
+
+        gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
+        while (1) {
+            for (uint32_t i = 0; i < 9; i++) {
+                gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1);
+                board_delay_ms(10);
+                gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0);
+                board_delay_ms(10);
+            }
+            board_delay_ms(100);
+        }
+        printf("I2C bus is cleared\n");
+    }
+}
+
+void board_init_i2c(I2C_Type *ptr)
+{
+    hpm_stat_t stat;
+    uint32_t freq;
+    i2c_config_t config;
+
+    board_i2c_bus_clear(ptr);
+
+    init_i2c_pins(ptr);
+    clock_add_to_group(clock_i2c0, 0);
+    clock_add_to_group(clock_i2c1, 0);
+    clock_add_to_group(clock_i2c2, 0);
+    clock_add_to_group(clock_i2c3, 0);
+    /* Configure the I2C clock to 24MHz */
+    clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U);
+
+    config.i2c_mode = i2c_mode_normal;
+    config.is_10bit_addressing = false;
+    freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME);
+    stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config);
+    if (stat != status_success) {
+        printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE);
+        while (1) {}
+    }
+}
+
+uint32_t board_init_uart_clock(UART_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_UART0) {
+        clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart0);
+    } else if (ptr == HPM_UART6) {
+        clock_set_source_divider(clock_uart6, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart6);
+    } else if (ptr == HPM_UART13) {
+        clock_set_source_divider(clock_uart13, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart13);
+    } else if (ptr == HPM_UART14) {
+        clock_set_source_divider(clock_uart14, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart14);
+    } else {
+        /* Not supported */
+    }
+    return freq;
+}
+
+uint32_t board_init_spi_clock(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI2) {
+        /* SPI2 clock configure */
+        clock_add_to_group(clock_spi2, 0);
+        clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U);
+
+        return clock_get_frequency(clock_spi2);
+    }
+    return 0;
+}
+
+void board_init_cap_touch(void)
+{
+    init_cap_pins();
+    gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
+    gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
+
+    board_delay_ms(1);
+    gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1);
+    board_delay_ms(10);
+    gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
+
+    gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
+    board_init_i2c(BOARD_CAP_I2C_BASE);
+}
+
+void board_init_gpio_pins(void)
+{
+    init_gpio_pins();
+}
+
+void board_init_spi_pins(SPI_Type *ptr)
+{
+    init_spi_pins(ptr);
+}
+
+void board_init_led_pins(void)
+{
+    init_led_pins_as_gpio();
+    gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+    gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+    gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void board_led_toggle(void)
+{
+#ifdef BOARD_LED_TOGGLE_RGB
+    static uint8_t i;
+    gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN);
+    i++;
+    i = i % 3;
+#else
+    gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+#endif
+}
+
+void board_led_write(uint8_t state)
+{
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+void board_init_cam_pins(void)
+{
+    init_cam_pins();
+    /* enable cam RST pin out with high level */
+    gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1);
+}
+
+void board_write_cam_rst(uint8_t state)
+{
+    gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state);
+
+}
+
+void board_init_usb_pins(void)
+{
+    /* set pull-up for USBx OC pins and ID pins */
+    init_usb_pins();
+
+    /* configure USBx ID pins as input function */
+    gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
+    gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN);
+
+    /* configure USBx OC Flag pins as input function */
+    gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN);
+    gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN);
+}
+
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
+{
+}
+
+void board_init_pmp(void)
+{
+    extern uint32_t __noncacheable_start__[];
+    extern uint32_t __noncacheable_end__[];
+
+    uint32_t start_addr = (uint32_t) __noncacheable_start__;
+    uint32_t end_addr = (uint32_t) __noncacheable_end__;
+    uint32_t length = end_addr - start_addr;
+
+    if (length == 0) {
+        return;
+    }
+
+    /* Ensure the address and the length are power of 2 aligned */
+    assert((length & (length - 1U)) == 0U);
+    assert((start_addr & (length - 1U)) == 0U);
+
+    pmp_entry_t pmp_entry[1];
+    pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
+    pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
+    pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
+    pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
+
+    pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry));
+}
+
+void board_init_clock(void)
+{
+    uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
+    hpm_core_clock = cpu0_freq;
+    if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
+        /* Configure the External OSC ramp-up time: ~9ms */
+        pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
+
+        /* Select clock setting preset1 */
+        sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
+    }
+
+    /* Add most Clocks to group 0 */
+    clock_add_to_group(clock_cpu0, 0);
+    clock_add_to_group(clock_mchtmr0, 0);
+    clock_add_to_group(clock_axi0, 0);
+    clock_add_to_group(clock_axi1, 0);
+    clock_add_to_group(clock_axi2, 0);
+    clock_add_to_group(clock_ahb, 0);
+    clock_add_to_group(clock_dram, 0);
+    clock_add_to_group(clock_xpi0, 0);
+    clock_add_to_group(clock_xpi1, 0);
+    clock_add_to_group(clock_gptmr0, 0);
+    clock_add_to_group(clock_gptmr1, 0);
+    clock_add_to_group(clock_gptmr2, 0);
+    clock_add_to_group(clock_gptmr3, 0);
+    clock_add_to_group(clock_gptmr4, 0);
+    clock_add_to_group(clock_gptmr5, 0);
+    clock_add_to_group(clock_gptmr6, 0);
+    clock_add_to_group(clock_gptmr7, 0);
+    clock_add_to_group(clock_uart0, 0);
+    clock_add_to_group(clock_uart1, 0);
+    clock_add_to_group(clock_uart2, 0);
+    clock_add_to_group(clock_uart3, 0);
+    clock_add_to_group(clock_uart13, 0);
+    clock_add_to_group(clock_i2c0, 0);
+    clock_add_to_group(clock_i2c1, 0);
+    clock_add_to_group(clock_i2c2, 0);
+    clock_add_to_group(clock_i2c3, 0);
+    clock_add_to_group(clock_spi0, 0);
+    clock_add_to_group(clock_spi1, 0);
+    clock_add_to_group(clock_spi2, 0);
+    clock_add_to_group(clock_spi3, 0);
+    clock_add_to_group(clock_can0, 0);
+    clock_add_to_group(clock_can1, 0);
+    clock_add_to_group(clock_can2, 0);
+    clock_add_to_group(clock_can3, 0);
+    clock_add_to_group(clock_display, 0);
+    clock_add_to_group(clock_sdxc0, 0);
+    clock_add_to_group(clock_sdxc1, 0);
+    clock_add_to_group(clock_camera0, 0);
+    clock_add_to_group(clock_camera1, 0);
+    clock_add_to_group(clock_ptpc, 0);
+    clock_add_to_group(clock_ref0, 0);
+    clock_add_to_group(clock_ref1, 0);
+    clock_add_to_group(clock_watchdog0, 0);
+    clock_add_to_group(clock_eth0, 0);
+    clock_add_to_group(clock_eth1, 0);
+    clock_add_to_group(clock_sdp, 0);
+    clock_add_to_group(clock_xdma, 0);
+    clock_add_to_group(clock_ram0, 0);
+    clock_add_to_group(clock_ram1, 0);
+    clock_add_to_group(clock_usb0, 0);
+    clock_add_to_group(clock_usb1, 0);
+    clock_add_to_group(clock_jpeg, 0);
+    clock_add_to_group(clock_pdma, 0);
+    clock_add_to_group(clock_kman, 0);
+    clock_add_to_group(clock_gpio, 0);
+    clock_add_to_group(clock_mbx0, 0);
+    clock_add_to_group(clock_hdma, 0);
+    clock_add_to_group(clock_rng, 0);
+    clock_add_to_group(clock_mot0, 0);
+    clock_add_to_group(clock_mot1, 0);
+    clock_add_to_group(clock_mot2, 0);
+    clock_add_to_group(clock_mot3, 0);
+    clock_add_to_group(clock_acmp, 0);
+    clock_add_to_group(clock_dao, 0);
+    clock_add_to_group(clock_msyn, 0);
+    clock_add_to_group(clock_lmm0, 0);
+    clock_add_to_group(clock_lmm1, 0);
+
+    clock_add_to_group(clock_adc0, 0);
+    clock_add_to_group(clock_adc1, 0);
+    clock_add_to_group(clock_adc2, 0);
+    clock_add_to_group(clock_adc3, 0);
+
+    clock_add_to_group(clock_i2s0, 0);
+    clock_add_to_group(clock_i2s1, 0);
+    clock_add_to_group(clock_i2s2, 0);
+    clock_add_to_group(clock_i2s3, 0);
+
+    /* Add the CPU1 clock to Group1 */
+    clock_add_to_group(clock_mchtmr1, 1);
+    clock_add_to_group(clock_mbx1, 1);
+
+    /* Connect Group0 to CPU0 */
+    clock_connect_group_to_cpu(0, 0);
+
+    if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
+        printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ);
+        while(1);
+    }
+
+    clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
+    clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
+    /* Connect Group1 to CPU1 */
+    clock_connect_group_to_cpu(1, 1);
+}
+
+uint32_t board_init_cam_clock(CAM_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_CAM0) {
+        /* Configure camera clock to 24MHz */
+        clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U);
+        freq = clock_get_frequency(clock_camera0);
+    } else if (ptr == HPM_CAM1) {
+        /* Configure camera clock to 24MHz */
+        clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U);
+        freq = clock_get_frequency(clock_camera1);
+    } else {
+        /* Invalid camera instance */
+    }
+    return freq;
+}
+
+uint32_t board_init_lcd_clock(void)
+{
+    uint32_t freq;
+    clock_add_to_group(clock_display, 0);
+    /* Configure LCDC clock to 29.7MHz */
+    clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U);
+    freq = clock_get_frequency(clock_display);
+    return freq;
+}
+
+uint32_t board_init_adc12_clock(ADC12_Type *ptr)
+{
+    uint32_t freq = 0;
+    switch ((uint32_t) ptr) {
+    case HPM_ADC0_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc0);
+        break;
+    case HPM_ADC1_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc1, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc1);
+        break;
+    case HPM_ADC2_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc2, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc2);
+        break;
+    default:
+        /* Invalid ADC instance */
+        break;
+    }
+
+    return freq;
+}
+
+uint32_t board_init_dao_clock(void)
+{
+    clock_add_to_group(clock_dao, 0);
+
+    sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+    sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk);
+
+    return clock_get_frequency(clock_dao);
+}
+
+uint32_t board_init_pdm_clock(void)
+{
+    clock_add_to_group(clock_pdm, 0);
+
+    sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+    sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
+
+    return clock_get_frequency(clock_pdm);
+}
+
+uint32_t board_init_i2s_clock(I2S_Type *ptr)
+{
+    if (ptr == HPM_I2S0) {
+        clock_add_to_group(clock_i2s0, 0);
+
+        sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+        sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
+
+        return clock_get_frequency(clock_i2s0);
+    }
+    return 0;
+}
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_ADC3) {
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc3, clk_adc_src_ana1);
+        clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc3);
+    }
+
+    return freq;
+}
+
+void board_init_can(CAN_Type *ptr)
+{
+    init_can_pins(ptr);
+}
+
+uint32_t board_init_can_clock(CAN_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_CAN0) {
+        /* Set the CAN0 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can0);
+    } else if (ptr == HPM_CAN1) {
+        /* Set the CAN1 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can1);
+    } else if (ptr == HPM_CAN2) {
+        /* Set the CAN2 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can2);
+    } else if (ptr == HPM_CAN3) {
+        /* Set the CAN3 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can3);
+    } else {
+        /* Invalid CAN instance */
+    }
+    return freq;
+}
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, 0);
+        clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr0);
+    }
+    else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, 0);
+        clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr1);
+    }
+    else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, 0);
+        clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr2);
+    }
+    else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, 0);
+        clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr3);
+    }
+    else if (ptr == HPM_GPTMR4) {
+        clock_add_to_group(clock_gptmr4, 0);
+        clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr4);
+    }
+    else if (ptr == HPM_GPTMR5) {
+        clock_add_to_group(clock_gptmr5, 0);
+        clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr5);
+    }
+    else if (ptr == HPM_GPTMR6) {
+        clock_add_to_group(clock_gptmr6, 0);
+        clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr6);
+    }
+    else if (ptr == HPM_GPTMR7) {
+        clock_add_to_group(clock_gptmr7, 0);
+        clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr7);
+    }
+    else {
+        /* Invalid instance */
+    }
+}
+
+
+/*
+ * this function will be called during startup to initialize external memory for data use
+ */
+void _init_ext_ram(void)
+{
+    uint32_t dram_clk_in_hz;
+    board_init_sdram_pins();
+    dram_clk_in_hz = board_init_dram_clock();
+
+    dram_config_t config = {0};
+    dram_sdram_config_t sdram_config = {0};
+
+    dram_default_config(HPM_DRAM, &config);
+    config.dqs = DRAM_DQS_INTERNAL;
+    dram_init(HPM_DRAM, &config);
+
+    sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4;
+    sdram_config.prescaler = 0x3;
+    sdram_config.burst_len_in_byte = 8;
+    sdram_config.auto_refresh_count_in_one_burst = 1;
+    sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS;
+    sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3;
+
+    sdram_config.precharge_to_act_in_ns = 18;   /* Trp */
+    sdram_config.act_to_rw_in_ns = 18;          /* Trcd */
+    sdram_config.refresh_recover_in_ns = 70;     /* Trfc/Trc */
+    sdram_config.write_recover_in_ns = 12;      /* Twr/Tdpl */
+    sdram_config.cke_off_in_ns = 42;             /* Trcd */
+    sdram_config.act_to_precharge_in_ns = 42;   /* Tras */
+
+    sdram_config.self_refresh_recover_in_ns = 66;   /* Txsr */
+    sdram_config.refresh_to_refresh_in_ns = 66;     /* Trfc/Trc */
+    sdram_config.act_to_act_in_ns = 12;             /* Trrd */
+    sdram_config.idle_timeout_in_ns = 6;
+    sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED;
+
+    sdram_config.cs = BOARD_SDRAM_CS;
+    sdram_config.base_address = BOARD_SDRAM_ADDRESS;
+    sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
+    sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
+    sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
+    sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
+    sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
+    sdram_config.delay_cell_value = 29;
+
+    dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config);
+}
+
+
+void board_init_sd_pins(SDXC_Type *ptr)
+{
+    init_sdxc_pins(ptr, false);
+}
+
+
+uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
+{
+    uint32_t actual_freq = 0;
+    do {
+        if (ptr != HPM_SDXC1) {
+            break;
+        }
+        clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
+        sdxc_enable_sd_clock(ptr, false);
+        /* Configure the clock below 400KHz for the identification state */
+        if (freq <= 400000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63);
+        }
+            /* configure the clock to 24MHz for the SDR12/Default speed */
+        else if (freq <= 25000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
+        }
+            /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
+        else if (freq <= 50000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8);
+        }
+            /* Configure the clock to 100MHz for the SDR50 */
+        else if (freq <= 100000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
+        }
+            /* Configure the clock to 166MHz for SDR104/HS200/HS400  */
+        else if (freq <= 208000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
+        }
+            /* For other unsupported clock ranges, configure the clock to 24MHz */
+        else {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
+        }
+        sdxc_enable_sd_clock(ptr, true);
+        actual_freq = clock_get_frequency(sdxc_clk);
+    } while (false);
+
+    return actual_freq;
+}
+
+void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
+{
+    /* This feature is not supported */
+}
+
+bool board_sd_detect_card(SDXC_Type *ptr)
+{
+    return ((BOARD_APP_SDCARD_CDN_GPIO_CTRL->DI[GPIO_DI_GPIOD].VALUE & (1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN)) == 0U);
+}
+
+static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index)
+{
+    pwm_cmp_config_t cmp_config = {0};
+    pwm_output_channel_t ch_config = {0};
+
+    pwm_stop_counter(ptr);
+    pwm_get_default_cmp_config(ptr, &cmp_config);
+    pwm_get_default_output_channel_config(ptr, &ch_config);
+
+    pwm_set_reload(ptr, 0, 0xF);
+    pwm_set_start_count(ptr, 0, 0);
+
+    cmp_config.mode = pwm_cmp_mode_output_compare;
+    cmp_config.cmp = 0x10;
+    cmp_config.update_trigger = pwm_shadow_register_update_on_modify;
+    pwm_config_cmp(ptr, cmp_index, &cmp_config);
+
+    ch_config.cmp_start_index = cmp_index;
+    ch_config.cmp_end_index = cmp_index;
+    ch_config.invert_output = false;
+
+    pwm_config_output_channel(ptr, pin, &ch_config);
+}
+
+void board_init_rgb_pwm_pins(void)
+{
+    trgm_output_t config = {0};
+    board_turnoff_rgb_led();
+
+    set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP);
+    set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP);
+    set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP);
+
+    init_rgb_pwm_pins();
+
+    config.type = 0;
+    config.invert = false;
+
+    /* Red: TRGM1 P1 */
+    config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH8REF;
+    trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT1, &config);
+
+    /* Green: TRGM0 P6 */
+    config.input = HPM_TRGM0_INPUT_SRC_PWM0_CH8REF;
+    trgm_output_config(HPM_TRGM0, TRGM_TRGOCFG_TRGM_OUT6, &config);
+
+    /* Blue: TRGM1 P3 */
+    config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH9REF;
+    trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT3, &config);
+}
+
+void board_disable_output_rgb_led(uint8_t color)
+{
+    switch (color) {
+    case BOARD_RGB_RED:
+        trgm_disable_io_output(HPM_TRGM1, 1 << 1);
+        break;
+    case BOARD_RGB_GREEN:
+        trgm_disable_io_output(HPM_TRGM0, 1 << 6);
+        break;
+    case BOARD_RGB_BLUE:
+        trgm_disable_io_output(HPM_TRGM1, 1 << 3);
+        break;
+    default:
+        while (1) {
+            ;
+        }
+    }
+}
+
+void board_enable_output_rgb_led(uint8_t color)
+{
+    switch (color) {
+    case BOARD_RGB_RED:
+        trgm_enable_io_output(HPM_TRGM1, 1 << 1);
+        break;
+    case BOARD_RGB_GREEN:
+        trgm_enable_io_output(HPM_TRGM0, 1 << 6);
+        break;
+    case BOARD_RGB_BLUE:
+        trgm_enable_io_output(HPM_TRGM1, 1 << 3);
+        break;
+    default:
+        while (1) {
+            ;
+        }
+    }
+}
+
+hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
+{
+    /* set clock source */
+    if (ptr == HPM_ENET0) {
+        /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */
+        clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */
+    } else if (ptr == HPM_ENET1) {
+        /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */
+        clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
+{
+    if (internal == false) {
+        return status_success;
+    }
+    /* Configure Enet clock to output reference clock */
+    if (ptr == HPM_ENET0) {
+        /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */
+        clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5);
+    } else if (ptr == HPM_ENET1) {
+        /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */
+        clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */
+    } else {
+        return status_invalid_argument;
+    }
+    return status_success;
+}
+
+void board_init_adc12_pins(void)
+{
+    init_adc12_pins();
+}
+
+void board_init_adc16_pins(void)
+{
+    init_adc16_pins();
+}
+
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
+{
+    init_enet_pins(ptr);
+
+    if (ptr == HPM_ENET0) {
+        gpio_set_pin_output_with_initial(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0);
+       } else if (ptr == HPM_ENET1) {
+        gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0);
+        board_delay_ms(1);
+        gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1);
+    } else if (ptr == HPM_ENET1) {
+        gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0);
+        board_delay_ms(1);
+        gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}

bsp/hpmicro/hpm6750evk/board/board.h

@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _HPM_BOARD_H
+#define _HPM_BOARD_H
+#include <stdio.h>
+#include "hpm_common.h"
+#include "hpm_clock_drv.h"
+#include "hpm_soc.h"
+#include "hpm_soc_feature.h"
+#include "pinmux.h"
+
+#define BOARD_NAME "hpm6750evk"
+#define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
+
+/* uart section */
+#ifndef BOARD_RUNNING_CORE
+#define BOARD_RUNNING_CORE HPM_CORE0
+#endif
+#ifndef BOARD_APP_UART_BASE
+#define BOARD_APP_UART_BASE HPM_UART0
+#define BOARD_APP_UART_IRQ  IRQn_UART0
+#else
+#ifndef BOARD_APP_UART_IRQ
+#warning no IRQ specified for applicaiton uart
+#endif
+#endif
+
+/* uart rx idle demo section */
+#define BOARD_UART_IDLE HPM_UART13
+#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX
+
+#define BOARD_UART_IDLE_TRGM HPM_TRGM2
+#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19
+#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9
+#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2
+#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI
+
+#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4
+#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4
+#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4
+#define BOARD_UART_IDLE_GPTMR_CMP_CH 0
+#define BOARD_UART_IDLE_GPTMR_CAP_CH 2
+
+#define BOARD_APP_UART_BAUDRATE (115200UL)
+#define BOARD_APP_UART_CLK_NAME clock_uart0
+
+#ifndef BOARD_CONSOLE_TYPE
+#define BOARD_CONSOLE_TYPE console_type_uart
+#endif
+
+#if BOARD_CONSOLE_TYPE == console_type_uart
+#ifndef BOARD_CONSOLE_BASE
+#if BOARD_RUNNING_CORE == HPM_CORE0
+#define BOARD_CONSOLE_BASE HPM_UART0
+#define BOARD_CONSOLE_CLK_NAME clock_uart0
+#else
+#define BOARD_CONSOLE_BASE HPM_UART13
+#define BOARD_CONSOLE_CLK_NAME clock_uart13
+#endif
+#endif
+#define BOARD_CONSOLE_BAUDRATE (115200UL)
+#endif
+
+
+#define BOARD_FREEMASTER_UART_BASE HPM_UART0
+#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0
+#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0
+
+/* sdram section */
+#define BOARD_SDRAM_ADDRESS  (0x40000000UL)
+#define BOARD_SDRAM_SIZE     (32*SIZE_1MB)
+#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS
+#define BOARD_SDRAM_REFRESH_COUNT (8192UL)
+#define BOARD_SDRAM_REFRESH_IN_MS (64UL)
+#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL)
+
+#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL)
+#define BOARD_FLASH_SIZE (16 << 20)
+
+/* lcd section */
+#define BOARD_LCD_BASE HPM_LCDC
+#define BOARD_LCD_IRQ  IRQn_LCDC_D0
+#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0
+#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB
+#define BOARD_LCD_POWER_GPIO_PIN 16
+#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0
+#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB
+#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10
+
+/* i2c section */
+#define BOARD_APP_I2C_BASE HPM_I2C0
+#define BOARD_APP_I2C_CLK_NAME clock_i2c0
+#define BOARD_APP_I2C_DMA HPM_HDMA
+#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX
+#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0
+#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
+
+#define BOARD_CAM_I2C_BASE HPM_I2C0
+#define BOARD_CAM_I2C_CLK_NAME clock_i2c0
+#define BOARD_SUPPORT_CAM_RESET
+#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0
+#define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY
+#define BOARD_CAM_RST_GPIO_PIN 5
+
+#define BOARD_CAP_I2C_BASE (HPM_I2C0)
+#define BOARD_CAP_I2C_CLK_NAME clock_i2c0
+#define BOARD_CAP_RST_GPIO (HPM_GPIO0)
+#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_RST_GPIO_PIN (9)
+#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B)
+#define BOARD_CAP_INTR_GPIO (HPM_GPIO0)
+#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_INTR_GPIO_PIN (8)
+#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B)
+#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ)
+#define BOARD_CAP_I2C_SDA_GPIO_PIN (10)
+#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ)
+#define BOARD_CAP_I2C_CLK_GPIO_PIN (11)
+
+/* ACMP desction */
+#define BOARD_ACMP HPM_ACMP
+#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1
+#define BOARD_ACMP_IRQ IRQn_ACMP_1
+#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */
+#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */
+
+/* dma section */
+#define BOARD_APP_XDMA HPM_XDMA
+#define BOARD_APP_HDMA HPM_HDMA
+#define BOARD_APP_XDMA_IRQ IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ IRQn_HDMA
+#define BOARD_APP_DMAMUX HPM_DMAMUX
+
+/* gptmr section */
+#define BOARD_GPTMR HPM_GPTMR4
+#define BOARD_GPTMR_IRQ IRQn_GPTMR4
+#define BOARD_GPTMR_CHANNEL 1
+#define BOARD_GPTMR_PWM HPM_GPTMR3
+#define BOARD_GPTMR_PWM_CHANNEL 1
+
+/* gpio section */
+#define BOARD_R_GPIO_CTRL HPM_GPIO0
+#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_R_GPIO_PIN 11
+#define BOARD_G_GPIO_CTRL HPM_GPIO0
+#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_G_GPIO_PIN 12
+#define BOARD_B_GPIO_CTRL HPM_GPIO0
+#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_B_GPIO_PIN 13
+
+#define BOARD_LED_GPIO_CTRL HPM_GPIO0
+
+#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_LED_GPIO_PIN 12
+#define BOARD_LED_OFF_LEVEL 1
+#define BOARD_LED_ON_LEVEL 0
+
+#define BOARD_LED_TOGGLE_RGB 1
+
+#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ
+#define BOARD_APP_GPIO_PIN 2
+
+/* pinmux section */
+#define USING_GPIO0_FOR_GPIOZ
+#ifndef USING_GPIO0_FOR_GPIOZ
+#define BOARD_APP_GPIO_CTRL HPM_BGPIO
+#define BOARD_APP_GPIO_IRQ IRQn_BGPIO
+#else
+#define BOARD_APP_GPIO_CTRL HPM_GPIO0
+#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z
+#endif
+
+/* gpiom section */
+#define BOARD_APP_GPIOM_BASE            HPM_GPIOM
+#define BOARD_APP_GPIOM_USING_CTRL      HPM_FGPIO
+#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
+
+/* spi section */
+#define BOARD_APP_SPI_BASE HPM_SPI2
+#define BOARD_APP_SPI_CLK_SRC_FREQ      (24000000UL)
+#define BOARD_APP_SPI_SCLK_FREQ         (1562500UL)
+#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
+#define BOARD_APP_SPI_DATA_LEN_IN_BITS  (8U)
+#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX
+#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
+#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX
+#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1
+
+
+/* Flash section */
+#define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
+#define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90001U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000005U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)
+
+/* lcd section */
+#ifndef BOARD_LCD_WIDTH
+#define BOARD_LCD_WIDTH (800)
+#endif
+#ifndef BOARD_LCD_HEIGHT
+#define BOARD_LCD_HEIGHT (480)
+#endif
+
+/* pdma section */
+#define BOARD_PDMA_BASE HPM_PDMA
+
+/* i2s section */
+#define BOARD_APP_I2S_BASE HPM_I2S0
+#define BOARD_APP_I2S_DATA_LINE      (2U)
+#define BOARD_APP_I2S_CLK_NAME clock_i2s0
+#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0
+#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0
+
+/* enet section */
+#define BOARD_ENET0_RST_GPIO       HPM_GPIO0
+#define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF
+#define BOARD_ENET0_RST_GPIO_PIN   (0U)
+#define BOARD_ENET0_INF            enet_inf_rgmii
+#define BOARD_ENET0                HPM_ENET0
+#define BOARD_ENET0_TX_DLY         (0U)
+#define BOARD_ENET0_RX_DLY         (21U)
+#define BOARD_ENET0_PTP_CLOCK      (clock_ptp0)
+
+#define BOARD_ENET1_RST_GPIO        HPM_GPIO0
+#define BOARD_ENET1_RST_GPIO_INDEX  GPIO_DO_GPIOE
+#define BOARD_ENET1_RST_GPIO_PIN    (26U)
+#define BOARD_ENET1_INF             enet_inf_rmii
+#define BOARD_ENET1                 HPM_ENET1
+#define BOARD_ENET1_INT_REF_CLK     (1U)
+#define BOARD_ENET1_PTP_CLOCK       (clock_ptp1)
+
+/* ADC section */
+#define BOARD_APP_ADC12_NAME "ADC0"
+#define BOARD_APP_ADC12_BASE HPM_ADC0
+#define BOARD_APP_ADC12_IRQn IRQn_ADC0
+#define BOARD_APP_ADC12_CH                       (11U)
+
+#define BOARD_APP_ADC16_NAME "ADC3"
+#define BOARD_APP_ADC16_BASE HPM_ADC3
+#define BOARD_APP_ADC16_IRQn IRQn_ADC3
+#define BOARD_APP_ADC16_CH                       (2U)
+
+#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES     (1024U)
+#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES     (192U)
+#define BOARD_APP_ADC_PREEMPT_TRIG_LEN           (1U)
+#define BOARD_APP_ADC_SINGLE_CONV_CNT            (6)
+#define BOARD_APP_ADC_TRIG_PWMT0                 HPM_PWM0
+#define BOARD_APP_ADC_TRIG_PWMT1                 HPM_PWM1
+#define BOARD_APP_ADC_TRIG_TRGM0                 HPM_TRGM0
+#define BOARD_APP_ADC_TRIG_TRGM1                 HPM_TRGM1
+#define BOARD_APP_ADC_TRIG_PWM_SYNC              HPM_SYNT
+
+/* CAN section */
+#define BOARD_APP_CAN_BASE                       HPM_CAN0
+#define BOARD_APP_CAN_IRQn                       IRQn_CAN0
+
+
+/*
+ * timer for board delay
+ */
+#define BOARD_DELAY_TIMER (HPM_GPTMR7)
+#define BOARD_DELAY_TIMER_CH 0
+#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7)
+
+#define BOARD_CALLBACK_TIMER (HPM_GPTMR7)
+#define BOARD_CALLBACK_TIMER_CH 1
+#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7
+#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7)
+
+/* SDXC section */
+#define BOARD_APP_SDCARD_SDXC_BASE            (HPM_SDXC1)
+#define BOARD_APP_SDCARD_CDN_GPIO_CTRL        (HPM_GPIO0)
+#define BOARD_APP_SDCARD_CDN_GPIO_PIN         (15UL)
+#define BOARD_APP_SDCARD_SUPPORT_1V8          (0)
+
+/* USB section */
+#define BOARD_USB0_ID_PORT       (HPM_GPIO0)
+#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF)
+#define BOARD_USB0_ID_GPIO_PIN   (10)
+
+#define BOARD_USB0_OC_PORT       (HPM_GPIO0)
+#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF)
+#define BOARD_USB0_OC_GPIO_PIN   (8)
+
+#define BOARD_USB1_ID_PORT       (HPM_GPIO0)
+#define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF)
+#define BOARD_USB1_ID_GPIO_PIN   (7)
+
+#define BOARD_USB1_OC_PORT       (HPM_GPIO0)
+#define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF)
+#define BOARD_USB1_OC_GPIO_PIN   (5)
+
+/*BLDC pwm*/
+
+/*PWM define*/
+#define BOARD_BLDCPWM                     HPM_PWM2
+#define BOARD_BLDC_UH_PWM_OUTPIN         (0U)
+#define BOARD_BLDC_UL_PWM_OUTPIN         (1U)
+#define BOARD_BLDC_VH_PWM_OUTPIN         (2U)
+#define BOARD_BLDC_VL_PWM_OUTPIN         (3U)
+#define BOARD_BLDC_WH_PWM_OUTPIN         (4U)
+#define BOARD_BLDC_WL_PWM_OUTPIN         (5U)
+#define BOARD_BLDCPWM_TRGM                HPM_TRGM2
+#define BOARD_BLDCAPP_PWM_IRQ             IRQn_PWM2
+#define BOARD_BLDCPWM_CMP_INDEX_0         (0U)
+#define BOARD_BLDCPWM_CMP_INDEX_1         (1U)
+#define BOARD_BLDCPWM_CMP_INDEX_2         (2U)
+#define BOARD_BLDCPWM_CMP_INDEX_3         (3U)
+#define BOARD_BLDCPWM_CMP_INDEX_4         (4U)
+#define BOARD_BLDCPWM_CMP_INDEX_5         (5U)
+
+/*HALL define*/
+
+#define BOARD_BLDC_HALL_BASE                 HPM_HALL2
+#define BOARD_BLDC_HALL_TRGM                 HPM_TRGM2
+#define BOARD_BLDC_HALL_IRQ                  IRQn_HALL2
+#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC      HPM_TRGM2_INPUT_SRC_TRGM2_P6
+#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC      HPM_TRGM2_INPUT_SRC_TRGM2_P7
+#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC      HPM_TRGM2_INPUT_SRC_TRGM2_P8
+#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV        (1000U)
+
+
+
+/*QEI*/
+
+#define BOARD_BLDC_QEI_BASE              HPM_QEI2
+#define BOARD_BLDC_QEI_IRQ               IRQn_QEI2
+#define BOARD_BLDC_QEI_TRGM              HPM_TRGM2
+#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC    HPM_TRGM2_INPUT_SRC_TRGM2_P9
+#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC    HPM_TRGM2_INPUT_SRC_TRGM2_P10
+#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV     (16U)
+#define BOARD_BLDC_QEI_CLOCK_SOURCE      clock_mot2
+#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV       (4000U)
+
+/*Timer define*/
+
+#define BOARD_TMR_1MS                       HPM_GPTMR2
+#define BOARD_TMR_1MS_CH                        0
+#define BOARD_TMR_1MS_CMP                       0
+#define BOARD_TMR_1MS_IRQ                       IRQn_GPTMR2
+#define BOARD_TMR_1MS_RELOAD                    (100000U)
+
+#define BOARD_BLDC_TMR_1MS                       BOARD_TMR_1MS
+#define BOARD_BLDC_TMR_CH                        BOARD_TMR_1MS_CH
+#define BOARD_BLDC_TMR_CMP                       BOARD_TMR_1MS_CMP
+#define BOARD_BLDC_TMR_IRQ                       BOARD_TMR_1MS_IRQ
+#define BOARD_BLDC_TMR_RELOAD                    BOARD_TMR_1MS_RELOAD
+#define BOARD_BLDC_ADC_TRG                       ADC12_CONFIG_TRG2A
+
+/*adc*/
+#define BOARD_BLDC_ADC_MODULE                  ADCX_MODULE_ADC12
+#define BOARD_BLDC_ADC_U_BASE                  HPM_ADC0
+#define BOARD_BLDC_ADC_V_BASE                  HPM_ADC1
+#define BOARD_BLDC_ADC_W_BASE                  HPM_ADC2
+#define BOARD_BLDC_ADC_TRIG_FLAG               adc12_event_trig_complete
+
+#define BOARD_BLDC_ADC_CH_U                    (7U)
+#define BOARD_BLDC_ADC_CH_V                    (10U)
+#define BOARD_BLDC_ADC_CH_W                    (11U)
+#define BOARD_BLDC_ADC_IRQn                    IRQn_ADC0
+#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES  (40U)
+#define BOARD_BLDC_ADC_TRG                    ADC12_CONFIG_TRG2A
+#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN        (1U)
+#define BOARD_BLDC_PWM_TRIG_CMP_INDEX          (8U)
+#define BOARD_BLDC_TRIGMUX_IN_NUM              HPM_TRGM2_INPUT_SRC_PWM2_CH8REF
+#define BOARD_BLDC_TRG_NUM                     TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_ADC_IRQn                    IRQn_ADC0
+
+/* APP PWM */
+#define BOARD_APP_PWM HPM_PWM2
+#define BOARD_APP_PWM_CLOCK_NAME clock_mot2
+#define BOARD_APP_PWM_OUT1 0
+#define BOARD_APP_PWM_OUT2 1
+#define BOARD_APP_TRGM HPM_TRGM2
+
+/* RGB LED Section */
+#define BOARD_RED_PWM_IRQ IRQn_PWM1
+#define BOARD_RED_PWM HPM_PWM1
+#define BOARD_RED_PWM_OUT 8
+#define BOARD_RED_PWM_CMP 8
+#define BOARD_RED_PWM_CMP_INITIAL_ZERO true
+#define BOARD_RED_PWM_CLOCK_NAME clock_mot1
+
+#define BOARD_GREEN_PWM_IRQ IRQn_PWM0
+#define BOARD_GREEN_PWM HPM_PWM0
+#define BOARD_GREEN_PWM_OUT 8
+#define BOARD_GREEN_PWM_CMP 8
+#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true
+#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0
+
+#define BOARD_BLUE_PWM_IRQ IRQn_PWM1
+#define BOARD_BLUE_PWM HPM_PWM1
+#define BOARD_BLUE_PWM_OUT 9
+#define BOARD_BLUE_PWM_CMP 9
+#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true
+#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1
+
+#define BOARD_RGB_RED 0
+#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1)
+#define BOARD_RGB_BLUE  (BOARD_RGB_RED + 2)
+
+#define BOARD_CPU_FREQ (816000000UL)
+
+#define BOARD_APP_DISPLAY_CLOCK clock_display
+
+#ifndef BOARD_SHOW_CLOCK
+#define BOARD_SHOW_CLOCK 1
+#endif
+#ifndef BOARD_SHOW_BANNER
+#define BOARD_SHOW_BANNER 1
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void (*board_timer_cb)(void);
+
+void board_init(void);
+void board_init_console(void);
+
+void board_init_uart(UART_Type *ptr);
+void board_init_i2c(I2C_Type *ptr);
+void board_init_lcd(void);
+
+void board_init_can(CAN_Type *ptr);
+
+uint32_t board_init_dram_clock(void);
+
+void board_init_sdram_pins(void);
+void board_init_gpio_pins(void);
+void board_init_spi_pins(SPI_Type *ptr);
+void board_init_led_pins(void);
+
+/* cap touch */
+void board_init_cap_touch(void);
+
+void board_led_write(uint8_t state);
+void board_led_toggle(void);
+
+void board_fpga_power_enable(void);
+
+void board_init_cam_pins(void);
+void board_write_cam_rst(uint8_t state);
+
+/* Initialize SoC overall clocks */
+void board_init_clock(void);
+
+/* Initialize the UART clock */
+uint32_t board_init_uart_clock(UART_Type *ptr);
+
+/* Initialize the CAM(camera) dot clock */
+uint32_t board_init_cam_clock(CAM_Type *ptr);
+
+/* Initialize the LCD pixel clock */
+uint32_t board_init_lcd_clock(void);
+
+uint32_t board_init_spi_clock(SPI_Type *ptr);
+
+uint32_t board_init_adc12_clock(ADC12_Type *ptr);
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr);
+
+uint32_t board_init_can_clock(CAN_Type *ptr);
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
+uint32_t board_init_i2s_clock(I2S_Type *ptr);
+uint32_t board_init_pdm_clock(void);
+uint32_t board_init_dao_clock(void);
+
+void board_init_sd_pins(SDXC_Type *ptr);
+uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
+void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
+bool board_sd_detect_card(SDXC_Type *ptr);
+
+void board_init_adc12_pins(void);
+void board_init_adc16_pins(void);
+
+void board_init_usb_pins(void);
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
+
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
+
+hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
+
+/*
+ * @brief Initialize PMP and PMA for but not limited to the following purposes:
+ *      -- non-cacheable memory initialization
+ */
+void board_init_pmp(void);
+
+void board_delay_ms(uint32_t ms);
+
+void board_timer_create(uint32_t ms, board_timer_cb cb);
+
+void board_init_rgb_pwm_pins(void);
+void board_enable_output_rgb_led(uint8_t color);
+void board_disable_output_rgb_led(uint8_t color);
+
+/*
+ * Keep mchtmr clock on low power mode
+ */
+void board_ungate_mchtmr_at_lp_mode(void);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _HPM_BOARD_H */

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg

@@ -0,0 +1,345 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# openocd flash driver argument:
+#   - option0:
+#       [31:28] Flash probe type
+#         0 - SFDP SDR / 1 - SFDP DDR
+#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+#         6 - OctaBus DDR (SPI -> OPI DDR)
+#         8 - Xccela DDR (SPI -> OPI DDR)
+#         10 - EcoXiP DDR (SPI -> OPI DDR)
+#       [27:24] Command Pads after Power-on Reset
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [23:20] Command Pads after Configuring FLASH
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+#         0 - Not needed
+#         1 - QE bit is at bit 6 in Status Register 1
+#         2 - QE bit is at bit1 in Status Register 2
+#         3 - QE bit is at bit7 in Status Register 2
+#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+#       [15:8] Dummy cycles
+#         0 - Auto-probed / detected / default value
+#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+#       [7:4] Misc.
+#         0 - Not used
+#         1 - SPI mode
+#         2 - Internal loopback
+#         3 - External DQS
+#       [3:0] Frequency option
+#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+#   - option1:
+#       [31:20]  Reserved
+#       [19:16] IO voltage
+#         0 - 3V / 1 - 1.8V
+#       [15:12] Pin group
+#         0 - 1st group / 1 - 2nd group
+#       [11:8] Connection selection
+#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+#       [7:0] Drive Strength
+#         0 - Default value
+
+# xpi0 configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3040000
+#   - base address:     0x80000000
+#   - flash size:       0x2000000
+#   - flash option0:    0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+    echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure dram frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+    #$::_TARGET0 riscv dmi_write 0x39 0xF4001820
+    $::_TARGET0 riscv dmi_write 0x3C 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+    $::_TARGET0 riscv dmi_write 0x39 0xF4001820
+    $::_TARGET0 riscv dmi_write 0x3C 0x401
+    # PC01
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040208
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC00
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040200
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB31
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401F8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB30
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401F0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB29
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401E8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB28
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401E0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB27
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401D8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB26
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401D0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB25
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401C8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB24
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401C0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB23
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401B8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB22
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401B0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB21
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401A8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB20
+    $::_TARGET0 riscv dmi_write 0x39 0xF40401A0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB19
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040198
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PB18
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040190
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # PD13
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040368
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD12
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040360
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD10
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040350
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD09
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040348
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD08
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040340
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD07
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040338
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD06
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040330
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD05
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040328
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD04
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040320
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD03
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040318
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD02
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040310
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD01
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040308
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD00
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040300
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC29
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402E8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC28
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402E0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC27
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402D8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # PC22
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402B0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC21
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402A8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC17
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040288
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC15
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040278
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC12
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040260
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC11
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040258
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC10
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040250
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC09
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040248
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC08
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040240
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC07
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040238
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC06
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040230
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC05
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040228
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC04
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040220
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # PC14
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040270
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC13
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040268
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC16
+    # $::_TARGET0 riscv dmi_write 0x39 0xF4040280
+    $::_TARGET0 riscv dmi_write 0x3C 0x1000C
+    # PC26
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402D0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC25
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402C8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC19
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040298
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC18
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040290
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC23
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402B8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC24
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402C0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC30
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402F0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC31
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402F8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC02
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040210
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC03
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040218
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # dramc configuration
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+    sleep 10
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050008
+    $::_TARGET0 riscv dmi_write 0x3C 0x30524
+    $::_TARGET0 riscv dmi_write 0x39 0xF305000C
+    $::_TARGET0 riscv dmi_write 0x3C 0x6030524
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x10000000
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050010
+    $::_TARGET0 riscv dmi_write 0x3C 0x4000001b
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050014
+    $::_TARGET0 riscv dmi_write 0x3C 0
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050040
+    $::_TARGET0 riscv dmi_write 0x3C 0xf32
+
+    # 133Mhz configuration
+    #$::_TARGET0 riscv dmi_write 0x39 0xF3050044
+    $::_TARGET0 riscv dmi_write 0x3C 0x884e22
+    # 166Mhz configuration
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050044
+    $::_TARGET0 riscv dmi_write 0x3C 0x884e33
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+    $::_TARGET0 riscv dmi_write 0x3C 0x2020300
+
+    # config delay cell
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+    $::_TARGET0 riscv dmi_write 0x3C 0x3b
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+    $::_TARGET0 riscv dmi_write 0x3C 0x203b
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050094
+    $::_TARGET0 riscv dmi_write 0x3C 0
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050098
+    $::_TARGET0 riscv dmi_write 0x3C 0
+
+    # precharge all
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050090
+    $::_TARGET0 riscv dmi_write 0x3C 0x40000000
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+    # auto refresh
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+    # set mode
+    $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
+    $::_TARGET0 riscv dmi_write 0x3C 0x33
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+    $::_TARGET0 riscv dmi_write 0x3C 0x2020301
+    echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+    init_clock
+    init_sdram
+}
+
+$_TARGET0 configure -event gdb-attach {
+    reset halt
+}

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft2232.cfg

@@ -0,0 +1,15 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
+

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft232.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6014
+
+ftdi_layout_init 0x0018 0x001b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/jlink.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/jlink.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+reset_config srst_only
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x010b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg

@@ -0,0 +1 @@
+riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg

@@ -0,0 +1,38 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+
+proc release_core1 {} {
+    # set start point for core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C08
+    $::_TARGET0 riscv dmi_write 0x3C 0x20016284
+
+    # set boot flag for core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C
+    $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9
+
+    # release core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C00
+    $::_TARGET0 riscv dmi_write 0x3C 0x1000
+}
+
+$_TARGET1 configure -event reset-deassert-pre release_core1
+$_TARGET1 configure -event examine-start release_core1
+$_TARGET1 configure -event examine-end {
+    $::_TARGET1 arp_examine
+}
+
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg

@@ -0,0 +1,13 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0

bsp/hpmicro/hpm6750evk/board/eth_phy_port.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-01-11   hpmicro     First version
+ */
+
+#include "rtthread.h"
+
+#ifdef RT_USING_PHY
+#include <rtdevice.h>
+#include <rtdbg.h>
+#include "hpm_enet_drv.h"
+#include "eth_phy_port.h"
+#include "hpm_soc.h"
+#include "netif/ethernetif.h"
+#include "board.h"
+
+typedef struct
+{
+    char *mdio_name;
+    ENET_Type *instance;
+    struct eth_device *eth_dev;
+    phy_device_t *phy_dev;
+    struct rt_mdio_bus *mdio_bus;
+} eth_phy_handle_t;
+
+typedef struct
+{
+    uint8_t phy_handle_cnt;
+    eth_phy_handle_t **phy_handle;
+} eth_phy_monitor_handle_t;
+
+#ifdef BSP_USING_ETH0
+extern struct eth_device eth0_dev;
+static struct rt_mdio_bus mdio0_bus;
+static phy_device_t phy0_dev;
+static uint8_t phy0_reg_list[]= {PHY0_REG_LIST};
+
+static eth_phy_handle_t eth0_phy_handle =
+{
+    .instance  = HPM_ENET0,
+    .eth_dev   = &eth0_dev,
+    .phy_dev   = &phy0_dev,
+    .mdio_name = "MDIO0",
+    .mdio_bus  = &mdio0_bus,
+};
+#endif
+
+#ifdef BSP_USING_ETH1
+extern struct eth_device eth1_dev;
+static struct rt_mdio_bus mdio1_bus;
+static phy_device_t phy1_dev;
+static uint8_t phy1_reg_list[]= {PHY1_REG_LIST};
+
+static eth_phy_handle_t eth1_phy_handle =
+{
+    .instance     = HPM_ENET1,
+    .eth_dev      = &eth1_dev,
+    .phy_dev      = &phy1_dev,
+    .mdio_name    = "MDIO1",
+    .mdio_bus     = &mdio1_bus,
+};
+#endif
+
+static eth_phy_handle_t *s_gphys[] =
+{
+#ifdef BSP_USING_ETH0
+&eth0_phy_handle,
+#endif
+
+#ifdef BSP_USING_ETH1
+&eth1_phy_handle
+#endif
+};
+
+static uint8_t *s_gphy_reg_list[] =
+{
+#ifdef BSP_USING_ETH0
+phy0_reg_list,
+#endif
+
+#ifdef BSP_USING_ETH1
+phy1_reg_list,
+#endif
+};
+
+eth_phy_monitor_handle_t phy_monitor_handle =
+{
+    .phy_handle_cnt = ARRAY_SIZE(s_gphys),
+    .phy_handle     = s_gphys
+};
+
+static struct rt_phy_ops phy_ops;
+
+static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
+{
+    return PHY_STATUS_OK;
+}
+
+static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg);
+
+    return size;
+}
+
+static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg,  *(uint16_t *)data);
+
+    return size;
+}
+
+static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]);
+
+    #if PHY_AUTO_NEGO
+        reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+
+    #else
+        reg_status &= PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+    #endif
+
+    return PHY_STATUS_OK;
+}
+
+static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]);
+#if RGMII
+    if (PHY_STATUS_SPEED_1000M(reg_status))
+    {
+        *speed = PHY_SPEED_1000M;
+    }
+    else if (PHY_STATUS_SPEED_100M(reg_status))
+    {
+        *speed = PHY_SPEED_100M;
+    }
+    else
+    {
+        *speed = PHY_SPEED_10M;
+    }
+#else
+    if (PHY_STATUS_SPEED_10M(reg_status))
+    {
+        *speed = PHY_SPEED_10M;
+    }
+    else
+    {
+        *speed = PHY_SPEED_100M;
+    }
+#endif
+    *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX;
+
+    return PHY_STATUS_OK;
+}
+
+static void phy_poll_status(void *parameter)
+{
+    int ret;
+    phy_info_t phy_info;
+    rt_uint32_t status;
+    rt_device_t dev;
+    rt_phy_msg_t msg;
+    rt_uint32_t speed, duplex;
+    phy_device_t *phy_dev;
+    struct eth_device* eth_dev;
+    char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"};
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev;
+        phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev;
+
+        phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status);
+
+        if (status)
+        {
+            phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex);
+
+            ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            if (ret != 0)
+            {
+                memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            }
+        }
+
+        if (phy_dev->phy_link != status)
+        {
+            phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN;
+            eth_device_linkchange(eth_dev, status);
+            LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n");
+            if (status == PHY_LINK_UP)
+            {
+                LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]);
+                LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex");
+            }
+        }
+    }
+}
+
+static void phy_detection(void *parameter)
+{
+    uint8_t detected_count = 0;
+    struct rt_phy_msg msg = {0, 0};
+    phy_device_t *phy_dev = (phy_device_t *)parameter;
+    rt_uint32_t i;
+
+    msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX];
+    phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ);
+
+    while(phy_dev->phy.addr == 0xffff)
+    {
+        /* Search a PHY */
+        for (i = 0; i <= 0x1f; i++)
+        {
+            ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i;
+            phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1);
+
+            if (msg.value == PHY_ID1)
+            {
+                phy_dev->phy.addr = i;
+                LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr);
+                return;
+            }
+        }
+
+        phy_dev->phy.addr = 0xffff;
+        detected_count++;
+        rt_thread_mdelay(1000);
+
+        if (detected_count > 3)
+        {
+            LOG_E("No any PHY device is detected! Please check your hardware!\n");
+            return;
+        }
+    }
+}
+
+static void phy_monitor_thread_entry(void *args)
+{
+    rt_timer_t phy_status_timer;
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        LOG_D("Detect a PHY%d\n", i);
+        phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev);
+    }
+
+    phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER);
+
+    if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK)
+    {
+        LOG_E("Failed to start link change detection timer\n");
+    }
+}
+
+int phy_device_register(void)
+{
+    rt_err_t err = RT_ERROR;
+    rt_thread_t thread_phy_monitor;
+
+    /* Set ops for PHY */
+    phy_ops.init = phy_init;
+    phy_ops.get_link_status = phy_get_link_status;
+    phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex;
+
+    for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++)
+    {
+        /* Set PHY address */
+        s_gphys[i]->phy_dev->phy.addr = 0xffff;
+
+        /* Set MIDO bus */
+        s_gphys[i]->mdio_bus->hw_obj     = s_gphys[i]->instance;
+        s_gphys[i]->mdio_bus->name       = s_gphys[i]->mdio_name;
+        s_gphys[i]->mdio_bus->ops->read  = phy_read;
+        s_gphys[i]->mdio_bus->ops->write = phy_write;
+        s_gphys[i]->phy_dev->phy.bus     = s_gphys[i]->mdio_bus;
+        s_gphys[i]->phy_dev->phy.ops     = &phy_ops;
+
+        /* Set PHY register list */
+        s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i];
+
+        rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME);
+    }
+
+    /* Start PHY monitor */
+    thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2);
+
+    if (thread_phy_monitor != RT_NULL)
+    {
+        rt_thread_startup(thread_phy_monitor);
+    }
+    else
+    {
+        err = RT_ERROR;
+    }
+
+    return err;
+}
+INIT_PREV_EXPORT(phy_device_register);
+#endif /* RT_USING_PHY */

bsp/hpmicro/hpm6750evk/board/eth_phy_port.h

@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+*/
+
+#ifndef ETH_PHY_PORT_H
+#define ETH_PHY_PORT_H
+
+#include "hpm_ioc_regs.h"
+#include <rtdevice.h>
+
+#ifndef PHY_AUTO_NEGO
+#define PHY_AUTO_NEGO  (1U)
+#endif
+
+#ifndef PHY_MDIO_CSR_CLK_FREQ
+#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
+#endif
+
+enum phy_link_status
+{
+   PHY_LINK_DOWN = 0U,
+   PHY_LINK_UP
+};
+
+typedef struct {
+    rt_uint32_t phy_speed;
+    rt_uint32_t phy_duplex;
+} phy_info_t;
+
+typedef struct {
+    rt_uint32_t phy_link;
+    rt_phy_t phy;
+    phy_info_t phy_info;
+} phy_device_t;
+
+#ifdef BSP_USING_ETH0
+
+    #define RGMII  (1U)
+
+    /* DP83867 name and ID */
+    #define PHY_NAME                    ("DP83867")
+    #define PHY_ID1                     (0x2000U)
+    #define PHY_ID2                     (0x28U)
+
+    /* PHY_DP83867 basic control register */
+    #define PHY_BASIC_CONTROL_REG       (0x00U)
+    #define PHY_RESET_MASK              (1U << 15)
+    #define PHY_AUTO_NEGOTIATION_MASK   (1U << 12)
+
+    /* PHY_DP83867 basic status register */
+    #define PHY_BASIC_STATUS_REG        (0x01U)
+    #define PHY_LINKED_STATUS_MASK      (1U << 2)
+    #define PHY_AUTONEGO_COMPLETE_MASK  (1U << 5)
+
+    /* PHY_DP83867 ID one register */
+    #define PHY_ID1_REG                 (0x02U)
+
+    /* PHY_DP83867 ID two register */
+    #define PHY_ID2_REG                 (0x03U)
+
+    /* PHY_DP83867 auto-negotiate advertise register */
+    #define PHY_AUTONEG_ADVERTISE_REG   (0x04U)
+
+    /* PHY_DP83867 status register */
+    #define PHY_STATUS_REG              (0x11U)
+    #define PHY_100M_MASK               (1UL << 14)
+    #define PHY_1000M_MASK              (1UL << 15)
+    #define PHY_FULL_DUPLEX_MASK        (1UL << 13)
+    #define PHY_STATUS_SPEED_100M(SR)   ((SR) & PHY_100M_MASK)
+    #define PHY_STATUS_SPEED_1000M(SR)  ((SR) & PHY_1000M_MASK)
+    #define PHY_STATUS_FULL_DUPLEX(SR)  ((SR) & PHY_FULL_DUPLEX_MASK)
+    #define PHY_SPEED_SEL_SHIFT         (14U)
+    /* PHY_DP83867 interrupt control register */
+    #define PHY_INTERTUPT_CTRL_REG      (0x12U)
+
+    /* PHY_DP83867 interrupt status register */
+    #define PHY_INTERRUPT_STATUS_REG    (0x13U)
+
+    /* PHY register index */
+    typedef enum {
+        PHY_BASIC_CONTROL_REG_IDX = 0,
+        PHY_BASIC_STATUS_REG_IDX,
+        PHY_ID1_REG_IDX,
+        PHY_ID2_REG_IDX,
+        PHY_AUTONEG_ADVERTISE_REG_IDX,
+        PHY_STATUS_REG_IDX,
+        PHY_INTERRUPT_FLAG_REG_IDX,
+        PHY_INTERRUPT_MASK_REG_IDX
+    } phy_reg_idx_t;
+
+    /* ETH0 PHY register list */
+    #define PHY0_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                           PHY_BASIC_STATUS_REG,\
+                           PHY_ID1_REG,\
+                           PHY_ID2_REG,\
+                           PHY_AUTONEG_ADVERTISE_REG,\
+                           PHY_STATUS_REG,\
+                           PHY_INTERTUPT_CTRL_REG,\
+                           PHY_INTERRUPT_STATUS_REG
+
+#else
+    #define RMII  (1U)
+
+    /* DP83848 name and ID */
+    #define PHY_NAME                    ("DP83848")
+    #define PHY_ID1                     (0x2000U)
+    #define PHY_ID2                     (0x17U)
+
+    /* DP83848 basic control register */
+    #define PHY_BASIC_CONTROL_REG       (0x00U)
+    #define PHY_RESET_MASK              (1U << 15)
+    #define PHY_AUTO_NEGOTIATION_MASK   (1U << 12)
+
+    /* DP83848 basic status register */
+    #define PHY_BASIC_STATUS_REG        (0x01U)
+    #define PHY_LINKED_STATUS_MASK      (1U << 2)
+    #define PHY_AUTONEGO_COMPLETE_MASK  (1U << 5)
+
+    /* DP83848 ID one register */
+    #define PHY_ID1_REG                 (0x02U)
+
+    /* DP83848 ID two register */
+    #define PHY_ID2_REG                 (0x03U)
+
+    /* DP83848 auto-negotiate advertise register */
+    #define PHY_AUTONEG_ADVERTISE_REG   (0x04U)
+
+    /* DP83848 status register */
+    #define PHY_STATUS_REG              (0x10U)
+    #define PHY_10M_MASK                (1UL << 1)
+    #define PHY_FULL_DUPLEX_MASK        (1UL << 2)
+    #define PHY_STATUS_SPEED_10M(SR)    ((SR) & PHY_10M_MASK)
+    #define PHY_STATUS_FULL_DUPLEX(SR)  ((SR) & PHY_FULL_DUPLEX_MASK)
+
+    /* PHY register index */
+    typedef enum {
+        PHY_BASIC_CONTROL_REG_IDX = 0,
+        PHY_BASIC_STATUS_REG_IDX,
+        PHY_ID1_REG_IDX,
+        PHY_ID2_REG_IDX,
+        PHY_AUTONEG_ADVERTISE_REG_IDX,
+        PHY_STATUS_REG_IDX,
+    } phy_reg_idx_t;
+
+    /* ETH0 PHY register list */
+    #define PHY1_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                           PHY_BASIC_STATUS_REG,\
+                           PHY_ID1_REG,\
+                           PHY_ID2_REG,\
+                           PHY_AUTONEG_ADVERTISE_REG,\
+                           PHY_STATUS_REG
+
+#endif
+#endif
+
+
+
+

bsp/hpmicro/hpm6750evk/board/fal_cfg.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev stm32f2_onchip_flash;
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 9*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */

bsp/hpmicro/hpm6750evk/board/fal_flash_port.c

@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-03-09   hpmicro     First implementation
+ * 2022-08-01   hpmicro     Fixed random crashing during kvdb_init
+ * 2022-08-03   hpmicro     Improved erase speed
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_FAL
+#include "fal.h"
+#include "hpm_romapi.h"
+#include "board.h"
+#include "hpm_l1c_drv.h"
+
+#if defined(FLASH_XIP) && (FLASH_XIP == 1)
+
+#define FAL_ENTER_CRITICAL() do {\
+        rt_enter_critical();\
+        disable_irq_from_intc();\
+        fencei();\
+    }while(0)
+
+#define FAL_EXIT_CRITICAL() do {\
+        ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
+        fencei();\
+        rt_exit_critical();\
+        enable_irq_from_intc();\
+    }while(0)
+
+#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
+
+#else
+#define FAL_ENTER_CRITICAL()
+
+#define FAL_EXIT_CRITICAL()
+
+#define FAL_RAMFUNC
+
+#endif
+
+/***************************************************************************************************
+ *      FAL Porting Guide
+ *
+ *      1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
+ *         must be placed at RAM or ROM code
+ *      2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
+ *         interrupt related codes to RAM
+ *
+ ***************************************************************************************************/
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static xpi_nor_config_t s_flashcfg;
+
+/**
+ * @brief FAL Flash device context
+ */
+struct fal_flash_dev nor_flash0 =
+    {
+            .name = NOR_FLASH_DEV_NAME,
+            /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
+            .addr = NOR_FLASH_MEM_BASE,
+            .len = 8 * 1024 * 1024,
+            .blk_size = 4096,
+            .ops = { .init = init, .read = read, .write = write, .erase = erase },
+            .write_gran = 1
+    };
+
+/**
+ * @brief FAL initialization
+ *        This function probes the FLASH using the ROM API
+ */
+FAL_RAMFUNC static int init(void)
+{
+    int ret = RT_EOK;
+    xpi_nor_config_option_t cfg_option;
+    cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
+    cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
+    cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
+
+    FAL_ENTER_CRITICAL();
+    hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
+    FAL_EXIT_CRITICAL();
+    if (status != status_success)
+    {
+        ret = -RT_ERROR;
+    }
+    else
+    {
+        /* update the flash chip information */
+        uint32_t sector_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+        uint32_t flash_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
+        nor_flash0.blk_size = sector_size;
+        nor_flash0.len = flash_size;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief FAL read function
+ *        Read data from FLASH
+ * @param offset FLASH offset
+ * @param buf Buffer to hold data read by this API
+ * @param size Size of data to be read
+ * @return actual read bytes
+ */
+FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size)
+{
+    uint32_t flash_addr = nor_flash0.addr + offset;
+    uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
+    uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
+    uint32_t aligned_size = aligned_end - aligned_start;
+    rt_base_t level = rt_hw_interrupt_disable();
+    l1c_dc_invalidate(aligned_start, aligned_size);
+    rt_hw_interrupt_enable(level);
+
+    (void) rt_memcpy(buf, (void*) flash_addr, size);
+
+    return size;
+}
+
+/**
+ * @brief Write unaligned data to the page
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size)
+{
+    hpm_stat_t status;
+
+    FAL_ENTER_CRITICAL();
+    status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
+    FAL_EXIT_CRITICAL();
+
+    if (status != status_success)
+    {
+        return -RT_ERROR;
+        rt_kprintf("write failed, status=%d\n", status);
+    }
+
+    return size;
+}
+
+/**
+ * @brief FAL write function
+ *        Write data to specified FLASH address
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size)
+{
+    uint32_t *src = NULL;
+    uint32_t buf_32[64];
+    uint32_t write_size;
+    size_t remaining_size = size;
+    int ret = (int)size;
+
+    uint32_t page_size;
+    rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
+    uint32_t offset_in_page = offset % page_size;
+    if (offset_in_page != 0)
+    {
+        uint32_t write_size_in_page = page_size - offset_in_page;
+        uint32_t write_page_size = MIN(write_size_in_page, size);
+        (void) rt_memcpy(buf_32, buf, write_page_size);
+        write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
+        if (write_size < 0)
+        {
+            ret = -RT_ERROR;
+            goto write_quit;
+        }
+
+        remaining_size -= write_page_size;
+        offset += write_page_size;
+        buf += write_page_size;
+    }
+
+    while (remaining_size > 0)
+    {
+        write_size = MIN(remaining_size, sizeof(buf_32));
+        rt_memcpy(buf_32, buf, write_size);
+        src = &buf_32[0];
+
+        FAL_ENTER_CRITICAL();
+        hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
+                offset, write_size);
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            rt_kprintf("write failed, status=%d\n", status);
+            break;
+        }
+
+        remaining_size -= write_size;
+        buf += write_size;
+        offset += write_size;
+    }
+
+write_quit:
+    return ret;
+}
+
+/**
+ * @brief FAL erase function
+ *        Erase specified FLASH region
+ * @param offset the start FLASH address to be erased
+ * @param size size of the region to be erased
+ * @ret RT_EOK Erase operation is successful
+ * @retval -RT_ERROR Erase operation failed
+ */
+FAL_RAMFUNC static int erase(long offset, size_t size)
+{
+    uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
+    hpm_stat_t status;
+    int ret = (int)size;
+
+    uint32_t block_size;
+    uint32_t sector_size;
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
+    uint32_t erase_unit;
+    while (aligned_size > 0)
+    {
+        FAL_ENTER_CRITICAL();
+        if ((offset % block_size == 0) && (aligned_size >= block_size))
+        {
+            erase_unit = block_size;
+            status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        else
+        {
+            erase_unit = sector_size;
+            status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        offset += erase_unit;
+        aligned_size -= erase_unit;
+    }
+
+    return ret;
+}
+#endif /* RT_USING_FAL */

bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c

@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "hpm_sgtl5000.h"
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config)
+{
+    assert(context != NULL);
+    assert(config != NULL);
+
+    if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Set the data route */
+    if (sgtl_set_data_route(context, config->route) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Set sgtl5000 to master or slave */
+    sgtl_set_master_mode(context, config->master);
+
+    /* Input Volume Control
+    Configure ADC left and right analog volume to desired default.
+    Example shows volume of 0dB. */
+    if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Volume and Mute Control
+       Configure HP_OUT left and right volume to minimum, unmute.
+       HP_OUT and ramp the volume up to desired volume.*/
+    if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success)
+    {
+        return status_fail;
+    }
+
+    if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* LINEOUT and DAC volume control */
+    if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Configure DAC left and right digital volume */
+    if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Configure ADC volume, reduce 6db. */
+    if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Unmute DAC */
+    if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Unmute ADC */
+    if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Set the audio format */
+    if (sgtl_set_protocol(context, config->bus) != status_success)
+    {
+        return status_fail;
+    }
+
+    if (sgtl_config_data_format(context, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width) !=
+        status_success)
+    {
+        return status_fail;
+    }
+
+    /* sclk valid edge */
+    if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising)
+    {
+        if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE) !=
+            status_success)
+        {
+            return status_fail;
+        }
+    }
+    else
+    {
+        if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE) !=
+            status_success)
+        {
+            return status_fail;
+        }
+    }
+
+    return status_success;
+}
+
+hpm_stat_t sgtl_deinit(sgtl_context_t *context)
+{
+    hpm_stat_t stat = status_success;
+
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_adc));
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dac));
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dap));
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sin));
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sout));
+    HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_lineout));
+
+    return stat;
+}
+
+void sgtl_set_master_mode(sgtl_context_t *context, bool master)
+{
+    if (master == true)
+    {
+        (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_MASTER);
+    }
+    else
+    {
+        (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_SLAVE);
+    }
+}
+
+hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module)
+{
+    hpm_stat_t stat = status_success;
+    switch (module)
+    {
+        case sgtl_module_adc:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_dac:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_dap:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT)));
+            break;
+        case sgtl_module_i2sin:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT)));
+            break;
+        case sgtl_module_i2sout:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT)));
+            break;
+        case sgtl_module_hp:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_lineout:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK,
+                                 ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT)));
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module)
+{
+    hpm_stat_t stat = status_success;
+    switch (module)
+    {
+        case sgtl_module_adc:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_dac:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_dap:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT)));
+            HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT)));
+            break;
+        case sgtl_module_i2sin:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT)));
+            break;
+        case sgtl_module_i2sout:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT)));
+            break;
+        case sgtl_module_hp:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT)));
+            break;
+        case sgtl_module_lineout:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK,
+                                 ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT)));
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route)
+{
+    hpm_stat_t stat = status_success;
+    switch (route)
+    {
+        case sgtl_route_bypass:
+            /* Bypass means from line-in to HP*/
+            HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN));
+            break;
+        case sgtl_route_playback:
+            /* Data route I2S_IN-> DAC-> HP */
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC));
+            break;
+        case sgtl_route_playback_record:
+            /* I2S IN->DAC->HP  LINE_IN->ADC->I2S_OUT */
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC));
+            break;
+        case sgtl_route_playback_with_dap:
+            /* I2S_IN->DAP->DAC->HP */
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC));
+            break;
+        case sgtl_route_playback_with_dap_record:
+            /* I2S_IN->DAP->DAC->HP,  LINE_IN->ADC->I2S_OUT */
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap));
+            HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC));
+            break;
+        case sgtl_route_record:
+            /* LINE_IN->ADC->I2S_OUT */
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout));
+            HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC));
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol)
+{
+    hpm_stat_t stat = status_success;
+    switch (protocol)
+    {
+        case sgtl_bus_i2s:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE));
+            break;
+        case sgtl_bus_left_justified:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE));
+            break;
+        case sgtl_bus_right_justified:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE));
+            break;
+        case sgtl_bus_pcma:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE));
+            break;
+        case sgtl_bus_pcmb:
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY));
+            HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE));
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume)
+{
+    uint16_t vol = 0;
+    hpm_stat_t stat = status_success;
+    switch (module)
+    {
+        case sgtl_module_adc:
+            if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE)
+            {
+                return status_invalid_argument;
+            }
+
+            vol = (uint16_t)(volume | (volume << 4U));
+            stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL,
+                                 SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol);
+            break;
+        case sgtl_module_dac:
+            if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE))
+            {
+                return status_invalid_argument;
+            }
+            vol = (uint16_t)(volume | (volume << 8U));
+            stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol);
+            break;
+        case sgtl_module_hp:
+            if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE)
+            {
+                return status_invalid_argument;
+            }
+            vol = (uint16_t)(volume | (volume << 8U));
+            stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol);
+            break;
+        case sgtl_module_lineout:
+            if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE)
+            {
+                return status_invalid_argument;
+            }
+            vol = (uint16_t)(volume | (volume << 8U));
+            stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol);
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module)
+{
+    uint16_t vol = 0;
+    hpm_stat_t stat = status_success;
+
+    switch (module)
+    {
+        case sgtl_module_adc:
+            stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol);
+            vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT;
+            break;
+        case sgtl_module_dac:
+            stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol);
+            vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
+            break;
+        case sgtl_module_hp:
+            stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol);
+            vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT;
+            break;
+        case sgtl_module_lineout:
+            stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol);
+            vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT;
+            break;
+        default:
+            vol = 0;
+            break;
+    }
+    return stat == status_success ? vol : 0U;
+}
+
+hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute)
+{
+    hpm_stat_t stat = status_success;
+    switch (module)
+    {
+        case sgtl_module_adc:
+            stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U);
+            break;
+        case sgtl_module_dac:
+            if (mute)
+            {
+                stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL,
+                                     SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C);
+            }
+            else
+            {
+                stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL,
+                                     SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000);
+            }
+            break;
+        case sgtl_module_hp:
+            stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK,
+                                 ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT));
+            break;
+        case sgtl_module_lineout:
+            stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK,
+                                 ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT));
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+    return stat;
+}
+
+hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits)
+{
+    uint16_t val     = 0;
+    uint16_t regVal  = 0;
+    uint16_t mul_clk = 0U;
+    uint32_t sysFs   = 0U;
+    hpm_stat_t stat     = status_success;
+
+    /* Over sample rate can only up to 512, the least to 8k */
+    if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U))
+    {
+        return status_invalid_argument;
+    }
+
+    /* Configure the sample rate */
+    switch (sample_rate)
+    {
+        case 8000:
+            if (mclk > 32000U * 512U)
+            {
+                val   = 0x0038;
+                sysFs = 48000;
+            }
+            else
+            {
+                val   = 0x0020;
+                sysFs = 32000;
+            }
+            break;
+        case 11025:
+            val   = 0x0024;
+            sysFs = 44100;
+            break;
+        case 12000:
+            val   = 0x0028;
+            sysFs = 48000;
+            break;
+        case 16000:
+            if (mclk > 32000U * 512U)
+            {
+                val   = 0x003C;
+                sysFs = 96000;
+            }
+            else
+            {
+                val   = 0x0010;
+                sysFs = 32000;
+            }
+            break;
+        case 22050:
+            val   = 0x0014;
+            sysFs = 44100;
+            break;
+        case 24000:
+            if (mclk > 48000U * 512U)
+            {
+                val   = 0x002C;
+                sysFs = 96000;
+            }
+            else
+            {
+                val   = 0x0018;
+                sysFs = 48000;
+            }
+            break;
+        case 32000:
+            val   = 0x0000;
+            sysFs = 32000;
+            break;
+        case 44100:
+            val   = 0x0004;
+            sysFs = 44100;
+            break;
+        case 48000:
+            if (mclk > 48000U * 512U)
+            {
+                val   = 0x001C;
+                sysFs = 96000;
+            }
+            else
+            {
+                val   = 0x0008;
+                sysFs = 48000;
+            }
+            break;
+        case 96000:
+            val   = 0x000C;
+            sysFs = 96000;
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+
+    if (stat != status_success)
+    {
+        return stat;
+    }
+
+    if (sgtl_read_reg(context, CHIP_I2S_CTRL, &regVal) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* While as slave, Fs is input */
+    if ((regVal & SGTL5000_I2S_MS_GET_MASK) == 0U)
+    {
+        sysFs = sample_rate;
+    }
+    mul_clk = (uint16_t)(mclk / sysFs);
+    /* Configure the mul_clk. Sgtl-5000 only support 256, 384 and 512 oversample rate */
+    if ((mul_clk / 128U - 2U) > 2U)
+    {
+        return status_invalid_argument;
+    }
+    else
+    {
+        val |= (mul_clk / 128U - 2U);
+    }
+
+    if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Data bits configure,sgtl supports 16bit, 20bit 24bit, 32bit */
+    if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success)
+    {
+        return status_fail;
+    }
+
+    switch (bits)
+    {
+        case 16:
+            stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16);
+            break;
+        case 20:
+            stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20);
+            break;
+        case 24:
+            stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24);
+            break;
+        case 32:
+            stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32);
+            break;
+        default:
+            stat = status_invalid_argument;
+            break;
+    }
+
+    return stat;
+}
+
+hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource)
+{
+    uint16_t regValue = 0U, regBitMask = 0x40U;
+
+    /* headphone source form PGA */
+    if (playSource == (uint32_t)sgtl_play_source_linein)
+    {
+        regValue = 0x40U;
+    }
+    /* headphone source from DAC */
+    else
+    {
+        regValue = 0U;
+    }
+
+    return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue);
+}
+
+hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource)
+{
+    uint16_t regValue = 0U, regBitMask = 0x4U;
+
+    /* ADC source form LINEIN */
+    if (recordSource == (uint32_t)sgtl_record_source_linein)
+    {
+        regValue = 0x4U;
+    }
+    /* ADC source from MIC */
+    else
+    {
+        regValue = 0U;
+    }
+
+    return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue);
+}
+
+hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val)
+{
+    rt_size_t size;
+    rt_uint8_t data[4];
+    data[0] = reg >> 8;
+    data[1] = reg & 0xFF;
+    data[2] = (uint8_t) (val>>8);
+    data[3] = (uint8_t) (val & 0xFF);
+    size = rt_i2c_master_send(context->i2c_bus, context->slave_address, RT_I2C_WR, data, 4U);
+    if (size != 4) {
+        return status_fail;
+    }
+    return status_success;
+}
+
+hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val)
+{
+    rt_size_t size;
+    rt_uint8_t r[2];
+    uint8_t d[2];
+    r[0] = reg >> 8;
+    r[1] = reg & 0xFF;
+
+    size = rt_i2c_master_send(context->i2c_bus, context->slave_address, RT_I2C_WR, r, 2U);
+    if (size != 2) {
+        return status_fail;
+    }
+
+    size = rt_i2c_master_recv(context->i2c_bus, context->slave_address, RT_I2C_RD, d, 2U);
+    if (size != 2) {
+        return status_fail;
+    }
+    *val = (uint16_t)((d[0] << 8) | d[1]);
+    return status_success;
+}
+
+hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val)
+{
+    hpm_stat_t retval = 0;
+    uint16_t reg_val;
+
+    /* Read the register value out */
+    retval = sgtl_read_reg(context, reg, &reg_val);
+    if (retval != status_success)
+    {
+        return status_fail;
+    }
+
+    /* Modify the value */
+    reg_val &= clr_mask;
+    reg_val |= val;
+
+    /* Write the data to register */
+    retval = sgtl_write_reg(context, reg, reg_val);
+    if (retval != status_success)
+    {
+        return status_fail;
+    }
+
+    return status_success;
+}

bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.h

@@ -0,0 +1,1035 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _HPM_SGTL5000_H_
+#define _HPM_SGTL5000_H_
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include "drivers/i2c.h"
+
+/*!
+ * @addtogroup sgtl5000
+ * @ingroup codec
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define the register address of sgtl5000. */
+#define CHIP_ID                            0x0000U
+#define CHIP_DIG_POWER                     0x0002U
+#define CHIP_CLK_CTRL                      0x0004U
+#define CHIP_I2S_CTRL                      0x0006U
+#define CHIP_SSS_CTRL                      0x000AU
+#define CHIP_ADCDAC_CTRL                   0x000EU
+#define CHIP_DAC_VOL                       0x0010U
+#define CHIP_PAD_STRENGTH                  0x0014U
+#define CHIP_ANA_ADC_CTRL                  0x0020U
+#define CHIP_ANA_HP_CTRL                   0x0022U
+#define CHIP_ANA_CTRL                      0x0024U
+#define CHIP_LINREG_CTRL                   0x0026U
+#define CHIP_REF_CTRL                      0x0028U
+#define CHIP_MIC_CTRL                      0x002AU
+#define CHIP_LINE_OUT_CTRL                 0x002CU
+#define CHIP_LINE_OUT_VOL                  0x002EU
+#define CHIP_ANA_POWER                     0x0030U
+#define CHIP_PLL_CTRL                      0x0032U
+#define CHIP_CLK_TOP_CTRL                  0x0034U
+#define CHIP_ANA_STATUS                    0x0036U
+#define CHIP_ANA_TEST2                     0x003AU
+#define CHIP_SHORT_CTRL                    0x003CU
+#define SGTL5000_DAP_CONTROL               0x0100U
+#define SGTL5000_DAP_PEQ                   0x0102U
+#define SGTL5000_DAP_BASS_ENHANCE          0x0104U
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL     0x0106U
+#define SGTL5000_DAP_AUDIO_EQ              0x0108U
+#define SGTL5000_DAP_SGTL_SURROUND         0x010AU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS    0x010CU
+#define SGTL5000_DAP_COEF_WR_B0_MSB        0x010EU
+#define SGTL5000_DAP_COEF_WR_B0_LSB        0x0110U
+#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0   0x0116U
+#define SGTL5000_DAP_AUDIO_EQ_BAND1        0x0118U
+#define SGTL5000_DAP_AUDIO_EQ_BAND2        0x011AU
+#define SGTL5000_DAP_AUDIO_EQ_BAND3        0x011CU
+#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU
+#define SGTL5000_DAP_MAIN_CHAN             0x0120U
+#define SGTL5000_DAP_MIX_CHAN              0x0122U
+#define SGTL5000_DAP_AVC_CTRL              0x0124U
+#define SGTL5000_DAP_AVC_THRESHOLD         0x0126U
+#define SGTL5000_DAP_AVC_ATTACK            0x0128U
+#define SGTL5000_DAP_AVC_DECAY             0x012AU
+#define SGTL5000_DAP_COEF_WR_B1_MSB        0x012CU
+#define SGTL5000_DAP_COEF_WR_B1_LSB        0x012EU
+#define SGTL5000_DAP_COEF_WR_B2_MSB        0x0130U
+#define SGTL5000_DAP_COEF_WR_B2_LSB        0x0132U
+#define SGTL5000_DAP_COEF_WR_A1_MSB        0x0134U
+#define SGTL5000_DAP_COEF_WR_A1_LSB        0x0136U
+#define SGTL5000_DAP_COEF_WR_A2_MSB        0x0138U
+#define SGTL5000_DAP_COEF_WR_A2_LSB        0x013AU
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * SGTL5000_CHIP_DIG_POWER
+ */
+#define SGTL5000_ADC_ENABLE_CLR_MASK     0xFFBFU
+#define SGTL5000_ADC_ENABLE_GET_MASK     0x0040U
+#define SGTL5000_ADC_ENABLE_SHIFT        0x6U
+#define SGTL5000_DAC_ENABLE_CLR_MASK     0xFFDFU
+#define SGTL5000_DAC_ENABLE_GET_MASK     0x0020U
+#define SGTL5000_DAC_ENABLE_SHIFT        0x5U
+#define SGTL5000_DAP_ENABLE_CLR_MASK     0xFFEFU
+#define SGTL5000_DAP_ENABLE_GET_MASK     0x0010U
+#define SGTL5000_DAP_ENABLE_SHIFT        0x4U
+#define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU
+#define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U
+#define SGTL5000_I2S_OUT_ENABLE_SHIFT    0x1U
+#define SGTL5000_I2S_IN_ENABLE_CLR_MASK  0xFFFEU
+#define SGTL5000_I2S_IN_ENABLE_GET_MASK  0x0001U
+#define SGTL5000_I2S_IN_ENABLE_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_CLK_CTRL
+ */
+#define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU
+#define SGTL5000_RATE_MODE_GET_MASK 0x0030U
+#define SGTL5000_RATE_MODE_SHIFT    0x4U
+#define SGTL5000_RATE_MODE_DIV_1    0x0000U
+#define SGTL5000_RATE_MODE_DIV_2    0x0010U
+#define SGTL5000_RATE_MODE_DIV_4    0x0020U
+#define SGTL5000_RATE_MODE_DIV_6    0x0030U
+#define SGTL5000_SYS_FS_CLR_MASK    0xFFF3U
+#define SGTL5000_SYS_FS_GET_MASK    0x000CU
+#define SGTL5000_SYS_FS_SHIFT       0x2U
+#define SGTL5000_SYS_FS_32k         0x0000U
+#define SGTL5000_SYS_FS_44_1k       0x0004U
+#define SGTL5000_SYS_FS_48k         0x0008U
+#define SGTL5000_SYS_FS_96k         0x000CU
+#define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU
+#define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U
+#define SGTL5000_MCLK_FREQ_SHIFT    0x0U
+#define SGTL5000_MCLK_FREQ_256FS    0x0000U
+#define SGTL5000_MCLK_FREQ_384FS    0x0001U
+#define SGTL5000_MCLK_FREQ_512FS    0x0002U
+#define SGTL5000_MCLK_FREQ_PLL      0x0003U
+
+/*
+ * SGTL5000_CHIP_I2S_CTRL
+ */
+#define SGTL5000_I2S_SLCKFREQ_CLR_MASK  0xFEFFU
+#define SGTL5000_I2S_SCLKFREQ_GET_MASK  0x0100U
+#define SGTL5000_I2S_SCLKFREQ_SHIFT     0x8U
+#define SGTL5000_I2S_SCLKFREQ_64FS      0x0000U
+#define SGTL5000_I2S_SCLKFREQ_32FS      0x0100U /* Not for RJ mode */
+#define SGTL5000_I2S_MS_CLR_MASK        0xFF7FU
+#define SGTL5000_I2S_MS_GET_MASK        0x0080U
+#define SGTL5000_I2S_MS_SHIFT           0x7U
+#define SGTL5000_I2S_MASTER             0x0080U
+#define SGTL5000_I2S_SLAVE              0x0000U
+#define SGTL5000_I2S_SCLK_INV_CLR_MASK  0xFFBFU
+#define SGTL5000_I2S_SCLK_INV_GET_MASK  0x0040U
+#define SGTL5000_I2S_SCLK_INV_SHIFT     0x6U
+#define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U
+#define SGTL5000_I2S_VAILD_RISING_EDGE  0x0000U
+#define SGTL5000_I2S_DLEN_CLR_MASK      0xFFCFU
+#define SGTL5000_I2S_DLEN_GET_MASK      0x0030U
+#define SGTL5000_I2S_DLEN_SHIFT         0x4U
+#define SGTL5000_I2S_DLEN_32            0x0000U
+#define SGTL5000_I2S_DLEN_24            0x0010U
+#define SGTL5000_I2S_DLEN_20            0x0020U
+#define SGTL5000_I2S_DLEN_16            0x0030U
+#define SGTL5000_I2S_MODE_CLR_MASK      0xFFF3U
+#define SGTL5000_I2S_MODE_GET_MASK      0x000CU
+#define SGTL5000_I2S_MODE_SHIFT         0x2U
+#define SGTL5000_I2S_MODE_I2S_LJ        0x0000U
+#define SGTL5000_I2S_MODE_RJ            0x0004U
+#define SGTL5000_I2S_MODE_PCM           0x0008U
+#define SGTL5000_I2S_LRALIGN_CLR_MASK   0xFFFDU
+#define SGTL5000_I2S_LRALIGN_GET_MASK   0x0002U
+#define SGTL5000_I2S_LRALIGN_SHIFT      0x1U
+#define SGTL5000_I2S_ONE_BIT_DELAY      0x0000U
+#define SGTL5000_I2S_NO_DELAY           0x0002U
+#define SGTL5000_I2S_LRPOL_CLR_MASK     0xFFFEU
+#define SGTL5000_I2S_LRPOL_GET_MASK     0x0001U
+#define SGTL5000_I2S_LRPOL_SHIFT        0x0U
+#define SGTL5000_I2S_LEFT_FIRST         0x0000U
+#define SGTL5000_I2S_RIGHT_FIRST        0x0001U
+
+/*
+ * SGTL5000_CHIP_SSS_CTRL
+ */
+#define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU
+#define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U
+#define SGTL5000_DAP_MIX_LRSWAP_SHIFT    0xEU
+#define SGTL5000_DAP_LRSWAP_CLR_MASK     0xDFFFU
+#define SGTL5000_DAP_LRSWAP_GET_MASK     0x2000U
+#define SGTL5000_DAP_LRSWAP_SHIFT        0xDU
+#define SGTL5000_DAC_LRSWAP_CLR_MASK     0xEFFFU
+#define SGTL5000_DAC_LRSWAP_GET_MASK     0x1000U
+#define SGTL5000_DAC_LRSWAP_SHIFT        0xCU
+#define SGTL5000_I2S_LRSWAP_CLR_MASK     0xFBFFU
+#define SGTL5000_I2S_LRSWAP_GET_MASK     0x0400U
+#define SGTL5000_I2S_LRSWAP_SHIFT        0xAU
+#define SGTL5000_DAP_MIX_SEL_CLR_MASK    0xFCFFU
+#define SGTL5000_DAP_MIX_SEL_GET_MASK    0x0300U
+#define SGTL5000_DAP_MIX_SEL_SHIFT       0x8U
+#define SGTL5000_DAP_MIX_SEL_ADC         0x0000U
+#define SGTL5000_DAP_MIX_SEL_I2S_IN      0x0100U
+#define SGTL5000_DAP_SEL_CLR_MASK        0xFF3FU
+#define SGTL5000_DAP_SEL_GET_MASK        0x00C0U
+#define SGTL5000_DAP_SEL_SHIFT           0x6U
+#define SGTL5000_DAP_SEL_ADC             0x0000U
+#define SGTL5000_DAP_SEL_I2S_IN          0x0040U
+#define SGTL5000_DAC_SEL_CLR_MASK        0xFFCFU
+#define SGTL5000_DAC_SEL_GET_MASK        0x0030U
+#define SGTL5000_DAC_SEL_SHIFT           0x4U
+#define SGTL5000_DAC_SEL_ADC             0x0000U
+#define SGTL5000_DAC_SEL_I2S_IN          0x0010U
+#define SGTL5000_DAC_SEL_DAP             0x0030U
+#define SGTL5000_I2S_OUT_SEL_CLR_MASK    0xFFFCU
+#define SGTL5000_I2S_OUT_SEL_GET_MASK    0x0003U
+#define SGTL5000_I2S_OUT_SEL_SHIFT       0x0U
+#define SGTL5000_I2S_OUT_SEL_ADC         0x0000U
+#define SGTL5000_I2S_OUT_SEL_I2S_IN      0x0001U
+#define SGTL5000_I2S_OUT_SEL_DAP         0x0003U
+
+/*
+ * SGTL5000_CHIP_ADCDAC_CTRL
+ */
+#define SGTL5000_VOL_BUSY_DAC_RIGHT         0x2000U
+#define SGTL5000_VOL_BUSY_DAC_LEFT          0x1000U
+#define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK   0xFDFFU
+#define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK   0x0200U
+#define SGTL5000_DAC_VOL_RAMP_EN_SHIFT      0x9U
+#define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU
+#define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U
+#define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT    0x8U
+#define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK    0xFFF7U
+#define SGTL5000_DAC_MUTE_RIGHT_GET_MASK    0x0008U
+#define SGTL5000_DAC_MUTE_RIGHT_SHIFT       0x3U
+#define SGTL5000_DAC_MUTE_LEFT_CLR_MASK     0xFFFBU
+#define SGTL5000_DAC_MUTE_LEFT_GET_MASK     0x0004U
+#define SGTL5000_DAC_MUTE_LEFT_SHIFT        0x2U
+#define SGTL5000_ADC_HPF_FREEZE_CLR_MASK    0xFFFDU
+#define SGTL5000_ADC_HPF_FREEZE_GET_MASK    0x0002U
+#define SGTL5000_ADC_HPF_FREEZE_SHIFT       0x1U
+#define SGTL5000_ADC_HPF_BYPASS_CLR_MASK    0xFFFEU
+#define SGTL5000_ADC_HPF_BYPASS_GET_MASK    0x0001U
+#define SGTL5000_ADC_HPF_BYPASS_SHIFT       0x0U
+
+/*
+ * SGTL5000_CHIP_DAC_VOL
+ */
+#define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU
+#define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U
+#define SGTL5000_DAC_VOL_RIGHT_SHIFT    0x8U
+#define SGTL5000_DAC_VOL_LEFT_CLR_MASK  0xFF00U
+#define SGTL5000_DAC_VOL_LEFT_GET_MASK  0x00FFU
+#define SGTL5000_DAC_VOL_LEFT_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_PAD_STRENGTH
+ */
+#define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU
+#define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U
+#define SGTL5000_PAD_I2S_LRCLK_SHIFT    0x8U
+#define SGTL5000_PAD_I2S_SCLK_CLR_MASK  0xFF3FU
+#define SGTL5000_PAD_I2S_SCLK_GET_MASK  0x00C0U
+#define SGTL5000_PAD_I2S_SCLK_SHIFT     0x6U
+#define SGTL5000_PAD_I2S_DOUT_CLR_MASK  0xFFCFU
+#define SGTL5000_PAD_I2S_DOUT_GET_MASK  0x0030U
+#define SGTL5000_PAD_I2S_DOUT_SHIFT     0x4U
+#define SGTL5000_PAD_I2C_SDA_CLR_MASK   0xFFF3U
+#define SGTL5000_PAD_I2C_SDA_GET_MASK   0x000CU
+#define SGTL5000_PAD_I2C_SDA_SHIFT      0x2U
+#define SGTL5000_PAD_I2C_SCL_CLR_MASK   0xFFFCU
+#define SGTL5000_PAD_I2C_SCL_GET_MASK   0x0003U
+#define SGTL5000_PAD_I2C_SCL_SHIFT      0x0U
+
+/*
+ * SGTL5000_CHIP_ANA_ADC_CTRL
+ */
+#define SGTL5000_ADC_VOL_M6DB_CLR_MASK  0xFEFFU
+#define SGTL5000_ADC_VOL_M6DB_GET_MASK  0x0100U
+#define SGTL5000_ADC_VOL_M6DB_SHIFT     0x8U
+#define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU
+#define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U
+#define SGTL5000_ADC_VOL_RIGHT_SHIFT    0x4U
+#define SGTL5000_ADC_VOL_LEFT_CLR_MASK  0xFFF0U
+#define SGTL5000_ADC_VOL_LEFT_GET_MASK  0x000FU
+#define SGTL5000_ADC_VOL_LEFT_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_ANA_HP_CTRL
+ */
+#define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU
+#define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U
+#define SGTL5000_HP_VOL_RIGHT_SHIFT    0x8U
+#define SGTL5000_HP_VOL_LEFT_CLR_MASK  0xFF80U
+#define SGTL5000_HP_VOL_LEFT_GET_MASK  0x007FU
+#define SGTL5000_HP_VOL_LEFT_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_ANA_CTRL
+ */
+#define SGTL5000_MUTE_LO_GET_MASK    0x0100U
+#define SGTL5000_MUTE_LO_CLR_MASK    0xFEFFU
+#define SGTL5000_MUTE_LO_SHIFT       0x8U
+#define SGTL5000_SEL_HP_GET_MASK     0x0040U
+#define SGTL5000_SEL_HP_CLR_MASK     0xFFBFU
+#define SGTL5000_SEL_HP_SHIFT        0x6U
+#define SGTL5000_SEL_HP_DAC          0x0000U
+#define SGTL5000_SEL_HP_LINEIN       0x0040U
+#define SGTL5000_EN_ZCD_HP_GET_MASK  0x0020U
+#define SGTL5000_EN_ZCD_HP_CLR_MASK  0xFFDFU
+#define SGTL5000_EN_ZCD_HP_SHIFT     0x5U
+#define SGTL5000_MUTE_HP_GET_MASK    0x0010U
+#define SGTL5000_MUTE_HP_CLR_MASK    0xFFEFU
+#define SGTL5000_MUTE_HP_SHIFT       0x4U
+#define SGTL5000_SEL_ADC_GET_MASK    0x0004U
+#define SGTL5000_SEL_ADC_CLR_MASK    0xFFFBU
+#define SGTL5000_SEL_ADC_SHIFT       0x2U
+#define SGTL5000_SEL_ADC_MIC         0x0000U
+#define SGTL5000_SEL_ADC_LINEIN      0x0004U
+#define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U
+#define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU
+#define SGTL5000_EN_ZCD_ADC_SHIFT    0x1U
+#define SGTL5000_MUTE_ADC_GET_MASK   0x0001U
+#define SGTL5000_MUTE_ADC_CLR_MASK   0xFFFEU
+#define SGTL5000_MUTE_ADC_SHIFT      0x0U
+
+/*
+ * SGTL5000_CHIP_LINREG_CTRL
+ */
+#define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU
+#define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U
+#define SGTL5000_VDDC_MAN_ASSN_SHIFT    0x6U
+#define SGTL5000_VDDC_MAN_ASSN_VDDA     0x0000U
+#define SGTL5000_VDDC_MAN_ASSN_VDDIO    0x0040U
+#define SGTL5000_VDDC_ASSN_OVRD         0x0020U
+#define SGTL5000_LINREG_VDDD_CLR_MASK   0xFFF0U
+#define SGTL5000_LINREG_VDDD_GET_MASK   0x000FU
+#define SGTL5000_LINREG_VDDD_SHIFT      0x0U
+
+/*
+ * SGTL5000_CHIP_REF_CTRL
+ */
+#define SGTL5000_ANA_GND_MASK    0x01f0U
+#define SGTL5000_ANA_GND_SHIFT   0x4U
+#define SGTL5000_ANA_GND_WIDTH   0x5U
+#define SGTL5000_ANA_GND_BASE    0x320U /* mv */
+#define SGTL5000_ANA_GND_STP     0x19U  /*mv */
+#define SGTL5000_BIAS_CTRL_MASK  0x000eU
+#define SGTL5000_BIAS_CTRL_SHIFT 0x1U
+#define SGTL5000_BIAS_CTRL_WIDTH 0x3U
+#define SGTL5000_SMALL_POP       0x0001U
+
+/*
+ * SGTL5000_CHIP_MIC_CTRL
+ */
+#define SGTL5000_BIAS_R__CLR_MASK   0xFCFFU
+#define SGTL5000_BIAS_R_GET_MASK    0x0300U
+#define SGTL5000_BIAS_R_SHIFT       0x8U
+#define SGTL5000_BIAS_R_off         0x0000U
+#define SGTL5000_BIAS_R_2K          0x0100U
+#define SGTL5000_BIAS_R_4k          0x0200U
+#define SGTL5000_BIAS_R_8k          0x0300U
+#define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU
+#define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U
+#define SGTL5000_BIAS_VOLT_SHIFT    0x4U
+#define SGTL5000_MIC_GAIN_CLR_MASK  0xFFFCU
+#define SGTL5000_MIC_GAIN_GET_MASK  0x0003U
+#define SGTL5000_MIC_GAIN_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_LINE_OUT_CTRL
+ */
+#define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU
+#define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U
+#define SGTL5000_LINE_OUT_CURRENT_SHIFT    0x8U
+#define SGTL5000_LINE_OUT_CURRENT_180u     0x0000U
+#define SGTL5000_LINE_OUT_CURRENT_270u     0x0100U
+#define SGTL5000_LINE_OUT_CURRENT_360u     0x0300U
+#define SGTL5000_LINE_OUT_CURRENT_450u     0x0700U
+#define SGTL5000_LINE_OUT_CURRENT_540u     0x0F00U
+#define SGTL5000_LINE_OUT_GND_CLR_MASK     0xFFC0U
+#define SGTL5000_LINE_OUT_GND_GET_MASK     0x003FU
+#define SGTL5000_LINE_OUT_GND_SHIFT        0x0U
+#define SGTL5000_LINE_OUT_GND_BASE         0x320U /* mv */
+#define SGTL5000_LINE_OUT_GND_STP          0x19U
+#define SGTL5000_LINE_OUT_GND_MAX          0x23U
+
+/*
+ * SGTL5000_CHIP_LINE_OUT_VOL
+ */
+#define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU
+#define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U
+#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT    0x8U
+#define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK  0xFFE0U
+#define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK  0x001FU
+#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT     0x0U
+
+/*
+ * SGTL5000_CHIP_ANA_POWER
+ */
+#define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK         0x4000U
+#define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK         0xBFFFU
+#define SGTL5000_RIGHT_DAC_POWERUP_SHIFT            0xEU
+#define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK     0x2000U
+#define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK     0xDFFFU
+#define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT        0xDU
+#define SGTL5000_STARTUP_POWERUP_GET_MASK           0x1000U
+#define SGTL5000_STARTUP_POWERUP_CLR_MASK           0xEFFFU
+#define SGTL5000_STARTUP_POWERUP_SHIFT              0xCU
+#define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK      0x0800U
+#define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK      0xF7FFU
+#define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT         0xBU
+#define SGTL5000_PLL_POWERUP_GET_MASK               0x0400U
+#define SGTL5000_PLL_POWERUP_CLR_MASK               0xFBFFU
+#define SGTL5000_PLL_POWERUP_SHIFT                  0xAU
+#define SGTL5000_LINREG_D_POWERUP_GET_MASK          0x0200U
+#define SGTL5000_LINREG_D_POWERUP_CLR_MASK          0xFDFFU
+#define SGTL5000_LINREG_D_POWERUP_SHIFT             0x9U
+#define SGTL5000_VCOAMP_POWERUP_GET_MASK            0x0100U
+#define SGTL5000_VCOAMP_POWERUP_CLR_MASK            0xFEFFU
+#define SGTL5000_VCOAMP_POWERUP_SHIFT               0x8U
+#define SGTL5000_VAG_POWERUP_GET_MASK               0x0080U
+#define SGTL5000_VAG_POWERUP_CLR_MASK               0xFF7FU
+#define SGTL5000_VAG_POWERUP_SHIFT                  0x7U
+#define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK         0x0040U
+#define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK         0xFFBFU
+#define SGTL5000_RIGHT_ADC_POWERUP_SHIFT            0x6U
+#define SGTL5000_REFTOP_POWERUP_GET_MASK            0x0020U
+#define SGTL5000_REFTOP_POWERUP_CLR_MASK            0xFFDFU
+#define SGTL5000_REFTOP_POWERUP_SHIFT               0x5U
+#define SGTL5000_HEADPHONE_POWERUP_GET_MASK         0x0010U
+#define SGTL5000_HEADPHONE_POWERUP_CLR_MASK         0xFFEFU
+#define SGTL5000_HEADPHONE_POWERUP_SHIFT            0x4U
+#define SGTL5000_DAC_POWERUP_GET_MASK               0x0008U
+#define SGTL5000_DAC_POWERUP_CLR_MASK               0xFFF7U
+#define SGTL5000_DAC_POWERUP_SHIFT                  0x3U
+#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U
+#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU
+#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT    0x2U
+#define SGTL5000_ADC_POWERUP_GET_MASK               0x0002U
+#define SGTL5000_ADC_POWERUP_CLR_MASK               0xFFFDU
+#define SGTL5000_ADC_POWERUP_SHIFT                  0x1U
+#define SGTL5000_LINEOUT_POWERUP_GET_MASK           0x0001U
+#define SGTL5000_LINEOUT_POWERUP_CLR_MASK           0xFFFEU
+#define SGTL5000_LINEOUT_POWERUP_SHIFT              0x0U
+
+/*
+ * SGTL5000_CHIP_PLL_CTRL
+ */
+#define SGTL5000_PLL_INT_DIV_CLR_MASK  0x07FFU
+#define SGTL5000_PLL_INT_DIV_GET_MASK  0xF800U
+#define SGTL5000_PLL_INT_DIV_SHIFT     0xBU
+#define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU
+#define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U
+#define SGTL5000_PLL_FRAC_DIV_SHIFT    0x0U
+
+/*
+ * SGTL5000_CHIP_CLK_TOP_CTRL
+ */
+#define SGTL5000_ENABLE_INT_OSC_GET_MASK  0x0800U
+#define SGTL5000_ENABLE_INT_OSC_CLR_MASK  0xF7FFU
+#define SGTL5000_ENABLE_INT_OSC_SHIFT     0xBU
+#define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U
+#define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U
+#define SGTL5000_INPUT_FREQ_DIV2_SHIFT    0x3U
+
+/*
+ * SGTL5000_CHIP_ANA_STATUS
+ */
+#define SGTL5000_HP_LRSHORT    0x0200U
+#define SGTL5000_CAPLESS_SHORT 0x0100U
+#define SGTL5000_PLL_LOCKED    0x0010U
+
+/*
+ * SGTL5000_CHIP_SHORT_CTRL
+ */
+#define SGTL5000_LVLADJR_CLR_MASK      0x8FFFU
+#define SGTL5000_LVLADJR_GET_MASK      0x7000U
+#define SGTL5000_LVLADJR_SHIFT         0xCU
+#define SGTL5000_LVLADJL_CLR_MASK      0xF8FFU
+#define SGTL5000_LVLADJL_GET_MASK      0x0700U
+#define SGTL5000_LVLADJL_SHIFT         0x8U
+#define SGTL5000_LVLADJC_CLR_MASK      0xFF8FU
+#define SGTL5000_LVLADJC_GET_MASK      0x0070U
+#define SGTL5000_LVLADJC_SHIFT         0x4U
+#define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U
+#define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU
+#define SGTL5000_LR_SHORT_MOD_SHIFT    0x2U
+#define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU
+#define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U
+#define SGTL5000_CM_SHORT_MOD_SHIFT    0x0U
+
+/* DAP control register */
+#define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U
+#define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU
+#define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT    0x4U
+#define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U
+#define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU
+#define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT    0x0U
+
+/*
+ * DAP_PEQ_REG
+ */
+#define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U
+#define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U
+#define SGTL5000_DAP_PEQ_EN_SHIFT    0x0U
+
+/*
+ * DAP_BASS_ENHANCE_REG
+ */
+#define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK       0xC000U
+#define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK       0x3FFFU
+#define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT          0xEU
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT    0x9U
+#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U
+#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU
+#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT    0x8U
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK     0x0070U
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK     0xFF8FU
+#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT        0x4U
+#define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK         0x0001U
+#define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK         0xFFFEU
+#define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT            0x0U
+
+/*
+ * DAP_BASS_ENHANCE_CTRL_REG
+ */
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK   0x3F00U
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK   0xC0FFU
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT      0x8U
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U
+#define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU
+#define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT    0x0U
+
+/*
+ * DAP_SGTL_SURROUND_REG
+ */
+#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U
+#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU
+#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT    0x4U
+#define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK           0x0003U
+#define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK           0xFFFCU
+#define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT              0x0U
+
+/*
+ * DAP_FILTER_COEF_ACCESS_REG
+ */
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT    0xCU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK    0x0200U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK    0xFDFFU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT       0x9U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK    0x0100U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK    0xFEFFU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT       0x8U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U
+#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT    0x0U
+
+/*
+ *  DAP_COEF_WR_B0_MSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT    0xFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT    0xEU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT    0xDU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT    0xCU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT    0xBU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT    0xAU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT    0x9U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT    0x8U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT    0x7U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT    0x6U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK  0x0020U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK  0xFFDFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT     0x5U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK  0x0010U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK  0xFFEFU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT     0x4U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK  0x0008U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK  0xFFF7U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT     0x3U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK  0x0004U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK  0xFFFBU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT     0x2U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK  0x0002U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK  0xFFFDU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT     0x1U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK  0x0001U
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK  0xFFFEU
+#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT     0x0U
+
+/*
+ * DAP_COEF_WR_B0_LSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT    0x3U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT    0x2U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT    0x1U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU
+#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_BASS_BAND0_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU
+#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_BAND1_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU
+#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_BAND2_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU
+#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_BAND3_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU
+#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT    0x0U
+
+/*
+ * DAP_AUDIO_EQ_TREBLE_BAND4_REG
+ */
+#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU
+#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U
+#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT    0x0U
+
+/*
+ * DAP_MAIN_CHAN_REG
+ */
+#define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU
+#define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U
+#define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT    0x0U
+
+/*
+ * DAP_MIX_CHAN_REG
+ */
+#define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU
+#define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U
+#define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT    0x0U
+
+/*
+ * DAP_AVC_CTRL_REG
+ */
+#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK   0x4000U
+#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK   0xBFFFU
+#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT      0xEU
+#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK      0x3000U
+#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK      0xCFFFU
+#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT         0xCU
+#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK  0x0300U
+#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK  0xFCFFU
+#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT     0x8U
+#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U
+#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU
+#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT    0x5U
+#define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK          0x0004U
+#define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT             0x2U
+#define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK       0x0002U
+#define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT          0x1U
+#define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK            0x0001U
+#define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK            0xFFFEU
+#define SGTL5000_DAP_AVC_CTRL_EN_SHIFT               0x0U
+
+/*
+ * DAP_AVC_ATTACK_REG
+ */
+#define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU
+#define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U
+#define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT    0x0U
+
+/*
+ * DAP_AVC_DECAY_REG
+ */
+#define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU
+#define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U
+#define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT    0x0U
+
+/*
+ * DAP_COEF_WR_B1_LSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU
+#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U
+#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT    0x0U
+
+/*
+ * DAP_COEF_WR_B2_LSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU
+#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U
+#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT    0x0U
+
+/*
+ * DAP_COEF_WR_A1_LSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU
+#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U
+#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT    0x0U
+
+/*
+ * DAP_COEF_WR_A2_LSB_REG
+ */
+#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU
+#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U
+#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT    0x0U
+
+/*! @brief SGTL5000 volume setting range */
+#define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU
+#define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U
+#define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE  0x1FU
+#define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE  0U
+#define SGTL5000_ADC_MAX_VOLUME_VALUE       0xFU
+#define SGTL5000_ADC_MIN_VOLUME_VALUE       0U
+#define SGTL5000_DAC_MAX_VOLUME_VALUE       0xF0U
+#define SGTL5000_DAC_MIN_VOLUME_VALUE       0x3CU
+
+/*! @brief SGTL5000 I2C address. */
+#define SGTL5000_I2C_ADDR 0x0A
+
+/*! @brief sgtl i2c baudrate */
+#define SGTL_I2C_BITRATE 100000U
+
+/*! @brief Modules in Sgtl5000 board. */
+typedef enum _sgtl5000_module
+{
+    sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */
+    sgtl_module_dac,       /*!< DAC module in SGTL5000 */
+    sgtl_module_dap,       /*!< DAP module in SGTL5000 */
+    sgtl_module_hp,        /*!< Headphone module in SGTL5000 */
+    sgtl_module_i2sin,     /*!< I2S-IN module in SGTL5000 */
+    sgtl_module_i2sout,    /*!< I2S-OUT module in SGTL5000 */
+    sgtl_module_linein,    /*!< Line-in moudle in SGTL5000 */
+    sgtl_module_lineout,   /*!< Line-out module in SGTL5000 */
+    sgtl_module_micin      /*!< Micphone module in SGTL5000 */
+} sgtl_module_t;
+
+/*!
+ * @brief Sgtl5000 data route.
+ * @note Only provide some typical data route, not all route listed.
+ * Users cannot combine any routes, once a new route is set, the precios one would be replaced.
+ */
+typedef enum _sgtl_route
+{
+    sgtl_route_bypass = 0x0,             /*!< LINEIN->Headphone. */
+    sgtl_route_playback,                 /*!< I2SIN->DAC->Headphone. */
+    sgtl_route_playback_record,        /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */
+    sgtl_route_playback_with_dap,          /*!< I2SIN->DAP->DAC->Headphone. */
+    sgtl_route_playback_with_dap_record, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */
+    sgtl_route_record                    /*!< LINEIN->ADC->I2SOUT. */
+} sgtl_route_t;
+
+/*!
+ * @brief The audio data transfer protocol choice.
+ * Sgtl5000 only supports I2S format and PCM format.
+ */
+typedef enum _sgtl_protocol
+{
+    sgtl_bus_i2s = 0x0,      /*!< I2S Type */
+    sgtl_bus_left_justified,  /*!< Left justified */
+    sgtl_bus_right_justified, /*!< Right Justified */
+    sgtl_bus_pcma,           /*!< PCMA */
+    sgtl_bus_pcmb            /*!< PCMB */
+} sgtl_protocol_t;
+
+/*! @brief sgtl play channel
+ * @anchor _sgtl_play_channel
+ */
+enum
+{
+    sgtl_headphone_left  = 0, /*!< headphone left channel */
+    sgtl_headphone_right = 1, /*!< headphone right channel */
+    sgtl_lineout_left    = 2, /*!< lineout left channel */
+    sgtl_lineout_right   = 3, /*!< lineout right channel */
+};
+
+/*! @brief sgtl record source
+ * _sgtl_record_source
+ */
+enum
+{
+    sgtl_record_source_linein = 0U, /*!< record source line in */
+    sgtl_record_source_mic    = 1U, /*!< record source single end */
+};
+
+/*! @brief sgtl play source
+ * _stgl_play_source
+ */
+enum
+{
+    sgtl_play_source_linein = 0U, /*!< play source line in */
+    sgtl_play_source_dac    = 1U, /*!< play source line in */
+};
+
+/*! @brief SGTL SCLK valid edge */
+typedef enum _sgtl_sclk_edge
+{
+    sgtl_sclk_valid_edge_rising   = 0U, /*!< SCLK valid edge */
+    sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */
+} sgtl_sclk_edge_t;
+
+/*! @brief Audio format configuration. */
+typedef struct _sgtl_audio_format
+{
+    uint32_t mclk_hz;          /*!< master clock */
+    uint32_t sample_rate;       /*!< Sample rate */
+    uint32_t bit_width;         /*!< Bit width */
+    sgtl_sclk_edge_t sclk_edge; /*!< sclk valid edge */
+} sgtl_audio_format_t;
+
+/*! @brief Initailize structure of sgtl5000 */
+typedef struct _sgtl_config
+{
+    sgtl_route_t route;         /*!< Audio data route.*/
+    sgtl_protocol_t bus;        /*!< Audio transfer protocol */
+    bool master;          /*!< Master or slave. True means master, false means slave. */
+    sgtl_audio_format_t format; /*!< audio format */
+} sgtl_config_t;
+
+typedef struct
+{
+    struct rt_i2c_bus_device *i2c_bus;  /* I2C bus device */
+    uint8_t slave_address;              /*!< code device slave address */
+} sgtl_context_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief sgtl5000 initialize function.
+ *
+ * In this function, some configurations are fixed.
+ * The second parameter can be NULL. If users want to change the SGTL5000 settings,
+ * a configure structure should be prepared.
+ * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings.
+ * The default setting:
+ * @code
+ * sgtl_init_t codec_config
+ * codec_config.route = sgtl_route_playback_record
+ * codec_config.bus = sgtl_bus_i2s
+ * codec_config.master = slave
+ * @endcode
+ *
+ * @param context Sgtl5000 context structure.
+ * @param config sgtl5000 configuration structure. If this pointer equals to NULL,
+ * it means using the default configuration.
+ * @return Initialization status
+ */
+hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config);
+
+/*!
+ * @brief Set audio data route in sgtl5000.
+ *
+ * This function would set the data route according to route. The route cannot be combined,
+ * as all route would enable different modules.
+ *
+ * @note If a new route is set, the previous route would not work.
+ * @param context Sgtl5000 context structure.
+ * @param route Audio data route in sgtl5000.
+ */
+hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route);
+
+/*!
+ * @brief Set the audio transfer protocol.
+ *
+ * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format.
+ * @param context Sgtl5000 context structure.
+ * @param protocol Audio data transfer protocol.
+ */
+hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol);
+
+/*!
+ * @brief Set sgtl5000 as master or slave.
+ *
+ * @param context Sgtl5000 context structure.
+ * @param master 1 represent master, 0 represent slave.
+ */
+void sgtl_set_master_mode(sgtl_context_t *context, bool master);
+
+/*!
+ * @brief Set the volume of different modules in sgtl5000.
+ *
+ * This function would set the volume of sgtl5000 modules. This interface set module volume.
+ * The function assume that left channel and right channel has the same volume.
+ *
+ * sgtl_module_adc volume range:      0 - 0xF,     0dB - 22.5dB
+ * sgtl_module_dac volume range:      0x3C - 0xF0, 0dB - -90dB
+ * sgtl_module_hp volume range:       0 - 0x7F,    12dB - -51.5dB
+ * sgtl_module_lineout volume range:  0 - 0x1F,    0.5dB steps
+ *
+ * @param context Sgtl5000 context structure.
+ * @param module Sgtl5000 module, such as DAC, ADC and etc.
+ * @param volume Volume value need to be set. The value is the exact value in register.
+ */
+hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume);
+
+/*!
+ * @brief Get the volume of different modules in sgtl5000.
+ *
+ * This function gets the volume of sgtl5000 modules. This interface get DAC module volume.
+ * The function assume that left channel and right channel has the same volume.
+ * @param context Sgtl5000 context structure.
+ * @param module Sgtl5000 module, such as DAC, ADC and etc.
+ * @return Module value, the value is exact value in register.
+ */
+uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module);
+
+/*!
+ * @brief Mute/unmute modules in sgtl5000.
+ *
+ * @param context Sgtl5000 context structure.
+ * @param module Sgtl5000 module, such as DAC, ADC and etc.
+ * @param mute True means mute, and false means unmute.
+ */
+hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute);
+
+/*!
+ * @brief Enable expected devices.
+ * @param context Sgtl5000 context structure.
+ * @param module Module expected to enable.
+ */
+hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module);
+
+/*!
+ * @brief Disable expected devices.
+ * @param context Sgtl5000 context structure.
+ * @param module Module expected to enable.
+ */
+hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module);
+
+/*!
+ * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules.
+ * @param context Sgtl5000 context structure pointer.
+ */
+hpm_stat_t sgtl_deint(sgtl_context_t *context);
+
+/*!
+ * @brief Configure the data format of audio data.
+ *
+ * This function would configure the registers about the sample rate, bit depths.
+ * @param context Sgtl5000 context structure pointer.
+ * @param mclk Master clock frequency of I2S.
+ * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now
+ * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate.
+ * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit
+ * and 32 bit in HW).
+ */
+hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits);
+
+/*!
+ * @brief select SGTL codec play source.
+ *
+ * @param context Sgtl5000 context structure pointer.
+ * @param playSource play source value, reference _sgtl_play_source.
+ *
+ * @return kStatus_Success, else failed.
+ */
+hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource);
+
+/*!
+ * @brief select SGTL codec record source.
+ *
+ * @param context Sgtl5000 context structure pointer.
+ * @param recordSource record source value, reference _sgtl_record_source.
+ *
+ * @return kStatus_Success, else failed.
+ */
+hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource);
+
+/*!
+ * @brief Write register to sgtl using I2C.
+ * @param context Sgtl5000 context structure.
+ * @param reg The register address in sgtl.
+ * @param val Value needs to write into the register.
+ */
+hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val);
+
+/*!
+ * @brief Read register from sgtl using I2C.
+ * @param context Sgtl5000 context structure.
+ * @param reg The register address in sgtl.
+ * @param val Value written to.
+ */
+hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val);
+
+/*!
+ * @brief Modify some bits in the register using I2C.
+ * @param context Sgtl5000 context structure.
+ * @param reg The register address in sgtl.
+ * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0.
+ * @param val Value needs to write into the register.
+ */
+hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _HPM_SGTL5000_H_ */

bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld

@@ -0,0 +1,255 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > SDRAM
+    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
+
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > SDRAM_NONCACHEABLE
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > SDRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > SDRAM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > AXI_SRAM
+
+    __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE);
+}

bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld

@@ -0,0 +1,256 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > SDRAM
+    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
+
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > AXI_SRAM_NONCACHEABLE
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > SDRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > SDRAM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > AXI_SRAM
+
+    __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE);
+}

bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld

@@ -0,0 +1,214 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    /* It's alias address of core0 ILM+DLM, but accessing via system bus */
+    CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K
+    /* It's alias address of core1 ILM+DLM, but accessing via system bus */
+    CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+}
+
+SECTIONS
+{
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_execpt_table))
+        KEEP(*(.gcc_execpt_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+    
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE);
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > DLM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > SDRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > SDRAM
+}

bsp/hpmicro/hpm6750evk/board/pinmux.c

@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+
+void init_uart_pins(UART_Type *ptr)
+{
+    if (ptr == HPM_UART0) {
+        HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
+        HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+    } else if (ptr == HPM_UART2) {
+        HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD;
+        HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD;
+    } else if (ptr == HPM_UART13) {
+        HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD;
+        HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD;
+        HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08;
+        HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09;
+    }
+}
+
+void init_lcd_pins(LCDC_Type *ptr)
+{
+    HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0;
+    HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1;
+    HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2;
+    HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3;
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4;
+    HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5;
+    HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6;
+    HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7;
+    HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0;
+    HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1;
+    HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2;
+    HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3;
+    HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4;
+    HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5;
+    HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6;
+    HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7;
+    HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0;
+    HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1;
+    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2;
+    HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3;
+    HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4;
+    HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5;
+    HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6;
+    HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7;
+    HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK;
+    HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN;
+    HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC;
+    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC;
+
+    /* PWM */
+    HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10;
+    /* RST */
+    HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_GPIO_B_16;
+}
+
+void init_cap_pins(void)
+{
+    /* CAP_INT */
+    HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
+    HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08;
+    /* CAP_RST */
+    HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
+    HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09;
+}
+
+void init_trgmux_pins(uint32_t pin)
+{
+    /* all trgmux pin ALT_SELECT fixed to 16*/
+    HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16);
+}
+
+void init_i2c_pins_as_gpio(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        /* I2C0 */
+        HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11;
+        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
+        HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10;
+        HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
+    } else {
+        while(1);
+    }
+}
+
+void init_i2c_pins(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
+        HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
+        HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+        HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+    } else {
+        while(1);
+    }
+}
+
+void init_sdram_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+
+    HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+
+    HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+
+    HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+    HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+    HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12);
+}
+
+void init_gpio_pins(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
+    HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
+
+#ifdef USING_GPIO0_FOR_GPIOZ
+    HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02;
+    HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl;
+    HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02;
+#endif
+}
+
+void init_spi_pins(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI2) {
+        HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_SPI2_CSN;
+        HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO;
+        HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    }
+}
+
+void init_pins(void)
+{
+    init_uart_pins(BOARD_CONSOLE_BASE);
+    init_sdram_pins();
+}
+
+void init_gptmr_pins(GPTMR_Type *ptr)
+{
+    if (ptr == HPM_GPTMR3) {
+        /* TMR3 compare 1 */
+        HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1;
+    }
+    if (ptr == HPM_GPTMR4) {
+        /* TMR4 capture 1 */
+        HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1;
+    }
+}
+
+void init_hall_trgm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06;
+    HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07;
+    HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_TRGM2_P_08;
+}
+
+void init_qei_trgm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09;
+    HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10;
+}
+
+void init_i2s_pins(I2S_Type *ptr)
+{
+    if (ptr == HPM_I2S0) {
+        HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_I2S0_RXD_2;
+        HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK;
+        HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_I2S0_TXD_2;
+        HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK;
+        HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK;
+    }
+}
+
+void init_dao_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P;
+    HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08;
+    HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N;
+    HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09;
+}
+
+void init_pdm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK;
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
+    HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0;
+    HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11;
+}
+
+void init_vad_pins(void)
+{
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK;
+    HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT;
+}
+
+void init_cam_pins(void)
+{
+#ifdef CAMREA_RESET_PWDN_CONFIGURABLE
+    HPM_IOC->PAD[IOC_PAD_PX08].FUNC_CTL = IOC_PX08_FUNC_CTL_GPIO_X_08;
+    HPM_IOC->PAD[IOC_PAD_PX09].FUNC_CTL = IOC_PX09_FUNC_CTL_GPIO_X_09;
+#endif
+
+    HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK;
+    HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK;
+    HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC;
+    HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC;
+    HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2;
+    HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3;
+    HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4;
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5;
+    HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6;
+    HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7;
+    HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8;
+    HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9;
+}
+
+void init_butn_pins(void)
+{
+    HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN;
+    HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN;
+    HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED;
+    HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED;
+}
+
+void init_acmp_pins(void)
+{
+    /* configure to ACMP_COMP_1(ALT16) function */
+    HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1;
+    /* configure to CMP1_INP7 function */
+    HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* configure to CMP1_INN6 function */
+    HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_enet_pins(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_GPIO_F_00;
+
+        HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_MDC;
+        HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_MDIO;
+
+        HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_RXD_0;
+        HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_ETH0_RXD_1;
+        HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ETH0_RXD_2;
+        HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_ETH0_RXD_3;
+        HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ETH0_RXCK;
+        HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_ETH0_RXDV;
+
+        HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ETH0_TXD_0;
+        HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_ETH0_TXD_1;
+        HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ETH0_TXD_2;
+        HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_ETH0_TXD_3;
+        HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_ETH0_TXCK;
+        HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_ETH0_TXEN;
+    } else if (ptr == HPM_ENET1) {
+        HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPIO_E_26;
+
+        HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC;
+        HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO;
+
+        HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0;
+        HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1;
+        HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV;
+
+        HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0;
+        HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1;
+        HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN;
+
+        HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK;
+    }
+}
+
+void init_pwm_pins(PWM_Type *ptr)
+{
+    if (ptr == HPM_PWM3) {
+        HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_PWM3_P_6;
+        HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_PWM3_P_7;
+    } else if (ptr == HPM_PWM2) {
+        HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PWM2_P_5;
+        HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PWM2_P_4;
+        HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PWM2_P_1;
+        HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PWM2_P_0;
+        HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PWM2_P_3;
+        HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM2_P_2;
+    }
+}
+
+void init_adc12_pins(void)
+{
+    /* ADC0/1/2.VIN7 */
+    HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* ADC0/1/2.VIN10 */
+    HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* ADC0/1/2.VIN11 */
+    HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_adc16_pins(void)
+{
+    /* ADC3.INA2 */
+    HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_adc_bldc_pins(void)
+{
+   HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+   HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+   HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_usb_pins(void)
+{
+    /* USB0_ID */
+    HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10;
+    HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+
+    /* USB0_OC */
+    HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08;
+    HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+
+    /* USB1_ID */
+    HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07;
+    HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+
+    /* USB1_OC */
+    HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05;
+    HPM_IOC->PAD[IOC_PAD_PF05].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+}
+
+void init_can_pins(CAN_Type *ptr)
+{
+    if (ptr == HPM_CAN0) {
+        HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_CAN0_TXD;
+        HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAN0_RXD;
+    }
+}
+
+void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8)
+{
+    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);;
+    uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17);
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) |
+                       IOC_PAD_PAD_CTL_PS_SET(1);
+
+    if (ptr == HPM_SDXC0) {
+    } else if (ptr == HPM_SDXC1) {
+        /* CLK */
+        HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl;
+
+        /* CMD */
+        HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl;
+
+        /* DATA0 */
+        HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl;
+        /* DATA1 */
+        HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl;
+        /* DATA2 */
+        HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl;
+        /* DATA3 */
+        HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl;
+
+        /* CDN */
+        HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
+        HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl;
+        HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN;
+
+    }
+}
+
+void init_clk_obs_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0;
+}
+
+void init_rgb_pwm_pins(void)
+{
+    /* Red */
+    HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_TRGM1_P_01;
+    /* Green */
+    HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TRGM0_P_06;
+    /* BLUE */
+    HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TRGM1_P_03;
+}
+
+void init_led_pins_as_gpio(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+
+    HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
+    HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
+    HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
+    HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
+}

bsp/hpmicro/hpm6750evk/board/pinmux.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef HPM_PINMUX_H
+#define HPM_PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void init_uart_pins(UART_Type *ptr);
+void init_lcd_pins(LCDC_Type *ptr);
+void init_i2c_pins(I2C_Type *ptr);
+void init_cap_pins(void);
+void init_sdram_pins(void);
+void init_gpio_pins(void);
+void init_spi_pins(SPI_Type *ptr);
+void init_pins(void);
+void init_gptmr_pins(GPTMR_Type *ptr);
+void init_hall_trgm_pins(void);
+void init_qei_trgm_pins(void);
+void init_i2s_pins(I2S_Type *ptr);
+void init_dao_pins(void);
+void init_pdm_pins(void);
+void init_vad_pins(void);
+void init_cam_pins(void);
+void init_butn_pins(void);
+void init_acmp_pins(void);
+void init_enet_pins(ENET_Type *ptr);
+void init_pwm_pins(PWM_Type *ptr);
+void init_adc12_pins(void);
+void init_adc16_pins(void);
+void init_usb_pins(void);
+void init_can_pins(CAN_Type *ptr);
+void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8);
+void init_adc_bldc_pins(void);
+void init_rgb_pwm_pins(void);
+void init_i2c_pins_as_gpio(I2C_Type *ptr);
+void init_led_pins_as_gpio(void);
+void init_trgmux_pins(uint32_t pin);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* HPM_PINMUX_H */

bsp/hpmicro/hpm6750evk/board/rtt_board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
+    gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN);
+    gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN);
+
+    gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF);
+    gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF);
+    gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state);
+        break;
+    case 1:
+        gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state);
+        break;
+    case 2:
+        gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);

bsp/hpmicro/hpm6750evk/board/rtt_board.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+
+/* gpio section */
+#define APP_LED0_GPIO_CTRL HPM_GPIO0
+#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED0_GPIO_PIN 11
+#define APP_LED1_GPIO_CTRL HPM_GPIO0
+#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED1_GPIO_PIN 12
+#define APP_LED2_GPIO_CTRL HPM_GPIO0
+#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED2_GPIO_PIN 13
+#define APP_LED_ON (0)
+#define APP_LED_OFF (1)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* SPI WIFI section */
+#define RW007_RST_PIN                         (IOC_PAD_PE02)
+#define RW007_INT_BUSY_PIN                    (IOC_PAD_PE01)
+#define RW007_CS_PIN                          (IOC_PAD_PE03)
+#define RW007_CS_GPIO                         (HPM_GPIO0)
+#define RW007_SPI_BUS_NAME                    "spi1"
+
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can0"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */

bsp/hpmicro/hpm6750evk/makefile.targets

@@ -0,0 +1,6 @@
+clean2:
+	-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+	-$(RM) $(OBJS) *.elf
+	-@echo ' '
+
+*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld)

bsp/hpmicro/hpm6750evk/rtconfig.h

@@ -0,0 +1,207 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_LEGACY
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Sensor libraries */
+
+
+/* Display libraries */
+
+
+/* Timing libraries */
+
+
+/* Project libraries */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_HPM6000
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_USING_RTC
+#define BSP_USING_DRAM
+#define INIT_EXT_RAM_FOR_DATA
+
+#endif

bsp/hpmicro/hpm6750evk/rtconfig.py

@@ -0,0 +1,94 @@
+# Copyright 2021-2022 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+
+CHIP_NAME='HPM6750'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compilercute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    DEVICE = ' -std=gnu11 -DUSE_NONVECTOR_MODE=1'
+    ARCH_ABI = '   -mcmodel=medlow '
+    CFLAGS = DEVICE + ARCH_ABI + ' -ffunction-sections -fdata-sections -fno-common'
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -static-libgcc'

bsp/hpmicro/hpm6750evk/rtconfig_preinc.h

@@ -0,0 +1,16 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define D45
+#define HAVE_CCONFIG_H
+#define HPM6750
+#define RT_USING_NEWLIB
+#define _POSIX_C_SOURCE 1
+#define _REENT_SMALL
+#define __RTTHREAD__
+
+#endif /*RTCONFIG_PREINC_H__*/

bsp/hpmicro/hpm6750evk/startup/HPM6360/SConscript

@@ -0,0 +1,21 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the startup files
+
+src = Split('''
+   startup.c
+   trap.c
+''')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', rtconfig.CHIP_NAME]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ *
+ */
+
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_l1c_drv.h"
+#include <rtthread.h>
+
+void system_init(void);
+
+extern int entry(void);
+
+extern void __libc_init_array(void);
+extern void __libc_fini_array(void);
+
+void system_init(void)
+{
+    disable_global_irq(CSR_MSTATUS_MIE_MASK);
+    disable_irq_from_intc();
+    enable_irq_from_intc();
+    enable_global_irq(CSR_MSTATUS_MIE_MASK);
+#ifndef CONFIG_NOT_ENABLE_ICACHE
+    l1c_ic_enable();
+#endif
+#ifndef CONFIG_NOT_ENABLE_DCACHE
+    l1c_dc_enable();
+#endif
+}
+
+__attribute__((weak)) void c_startup(void)
+{
+    uint32_t i, size;
+#ifdef FLASH_XIP
+    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+    size = __vector_ram_end__ - __vector_ram_start__;
+    for (i = 0; i < size; i++) {
+        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+    }
+#endif
+
+    extern uint8_t __etext[];
+    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __data_start__[], __data_end__[];
+    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+
+    /* bss section */
+    size = __bss_end__ - __bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__bss_start__ + i) = 0;
+    }
+
+    /* noncacheable bss section */
+    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_bss_start__ + i) = 0;
+    }
+
+    /* data section LMA: etext */
+    size = __data_end__ - __data_start__;
+    for (i = 0; i < size; i++) {
+        *(__data_start__ + i) = *(__etext + i);
+    }
+
+    /* ramfunc section LMA: etext + data length */
+    size = __ramfunc_end__ - __ramfunc_start__;
+    for (i = 0; i < size; i++) {
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+    }
+
+    /* noncacheable init section LMA: etext + data length + ramfunc length */
+    size = __noncacheable_init_end__ - __noncacheable_init_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+    }
+}
+
+__attribute__((weak)) int main(void)
+{
+    while(1);
+}
+
+void reset_handler(void)
+{
+    /**
+     * Disable preemptive interrupt
+     */
+    HPM_PLIC->FEATURE = 0;
+    /*
+     * Initialize LMA/VMA sections.
+     * Relocation for any sections that need to be copied from LMA to VMA.
+     */
+    c_startup();
+
+    /* Call platform specific hardware initialization */
+    system_init();
+
+    /* Do global constructors */
+    __libc_init_array();
+
+
+
+    /* Entry function */
+    entry();
+}
+
+
+__attribute__((weak)) void _init()
+{
+}

bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+ #include <rtconfig.h>
+ #include "hpm_csr_regs.h"
+    .section .start, "ax"
+
+    .global _start
+    .type _start,@function
+
+_start:
+    /* Initialize global pointer */
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop
+
+#ifdef INIT_EXT_RAM_FOR_DATA
+    la t0, _stack_in_dlm
+    mv sp, t0
+    call _init_ext_ram
+#endif
+
+    /* Initialize stack pointer */
+    la t0, _stack
+    mv sp, t0
+
+#ifdef __nds_execit
+    /* Initialize EXEC.IT table */
+    la t0, _ITB_BASE_
+    csrw uitb, t0
+#endif
+
+#ifdef __riscv_flen
+    /* Enable FPU */
+    li t0, CSR_MSTATUS_FS_MASK
+    csrrs t0, mstatus, t0
+
+    /* Initialize FCSR */
+    fscsr zero
+#endif
+    /* Disable Vector mode */
+    csrci CSR_MMISC_CTL, 2
+
+    /* Initialize trap_entry base */
+    la t0, irq_handler_trap
+    csrw mtvec, t0
+
+
+    /* System reset handler */
+    call reset_handler
+
+    /* Infinite loop, if returned accidently */
+1:    j 1b
+
+    .weak nmi_handler
+nmi_handler:
+1:    j 1b
+
+    .global default_irq_handler
+    .weak default_irq_handler
+    .align 2
+default_irq_handler:
+1:    j 1b
+
+    .macro IRQ_HANDLER irq
+    .weak default_isr_\irq
+    .set default_isr_\irq, default_irq_handler
+    .long default_isr_\irq
+    .endm
+
+#include "vectors.S"

bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021-2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .vector_table, "a"
+.global __vector_table
+.align 9
+
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, irq_handler_trap
+    .long default_isr_trap
+    IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
+    IRQ_HANDLER 8 /* ADC0 IRQ handler */
+    IRQ_HANDLER 9 /* ADC1 IRQ handler */
+    IRQ_HANDLER 10 /* ADC2 IRQ handler */
+    IRQ_HANDLER 11 /* DAC IRQ handler */
+    IRQ_HANDLER 12 /* ACMP[0] IRQ handler */
+    IRQ_HANDLER 13 /* ACMP[1] IRQ handler */
+    IRQ_HANDLER 14 /* SPI0 IRQ handler */
+    IRQ_HANDLER 15 /* SPI1 IRQ handler */
+    IRQ_HANDLER 16 /* SPI2 IRQ handler */
+    IRQ_HANDLER 17 /* SPI3 IRQ handler */
+    IRQ_HANDLER 18 /* UART0 IRQ handler */
+    IRQ_HANDLER 19 /* UART1 IRQ handler */
+    IRQ_HANDLER 20 /* UART2 IRQ handler */
+    IRQ_HANDLER 21 /* UART3 IRQ handler */
+    IRQ_HANDLER 22 /* UART4 IRQ handler */
+    IRQ_HANDLER 23 /* UART5 IRQ handler */
+    IRQ_HANDLER 24 /* UART6 IRQ handler */
+    IRQ_HANDLER 25 /* UART7 IRQ handler */
+    IRQ_HANDLER 26 /* CAN0 IRQ handler */
+    IRQ_HANDLER 27 /* CAN1 IRQ handler */
+    IRQ_HANDLER 28 /* PTPC IRQ handler */
+    IRQ_HANDLER 29 /* WDG0 IRQ handler */
+    IRQ_HANDLER 30 /* WDG1 IRQ handler */
+    IRQ_HANDLER 31 /* TSNS IRQ handler */
+    IRQ_HANDLER 32 /* MBX0A IRQ handler */
+    IRQ_HANDLER 33 /* MBX0B IRQ handler */
+    IRQ_HANDLER 34 /* GPTMR0 IRQ handler */
+    IRQ_HANDLER 35 /* GPTMR1 IRQ handler */
+    IRQ_HANDLER 36 /* GPTMR2 IRQ handler */
+    IRQ_HANDLER 37 /* GPTMR3 IRQ handler */
+    IRQ_HANDLER 38 /* I2C0 IRQ handler */
+    IRQ_HANDLER 39 /* I2C1 IRQ handler */
+    IRQ_HANDLER 40 /* I2C2 IRQ handler */
+    IRQ_HANDLER 41 /* I2C3 IRQ handler */
+    IRQ_HANDLER 42 /* PWM0 IRQ handler */
+    IRQ_HANDLER 43 /* HALL0 IRQ handler */
+    IRQ_HANDLER 44 /* QEI0 IRQ handler */
+    IRQ_HANDLER 45 /* PWM1 IRQ handler */
+    IRQ_HANDLER 46 /* HALL1 IRQ handler */
+    IRQ_HANDLER 47 /* QEI1 IRQ handler */
+    IRQ_HANDLER 48 /* SDP IRQ handler */
+    IRQ_HANDLER 49 /* XPI0 IRQ handler */
+    IRQ_HANDLER 50 /* XPI1 IRQ handler */
+    IRQ_HANDLER 51 /* XDMA IRQ handler */
+    IRQ_HANDLER 52 /* HDMA IRQ handler */
+    IRQ_HANDLER 53 /* DRAM IRQ handler */
+    IRQ_HANDLER 54 /* RNG IRQ handler */
+    IRQ_HANDLER 55 /* I2S0 IRQ handler */
+    IRQ_HANDLER 56 /* I2S1 IRQ handler */
+    IRQ_HANDLER 57 /* DAO IRQ handler */
+    IRQ_HANDLER 58 /* PDM IRQ handler */
+    IRQ_HANDLER 59 /* FFA IRQ handler */
+    IRQ_HANDLER 60 /* NTMR0 IRQ handler */
+    IRQ_HANDLER 61 /* USB0 IRQ handler */
+    IRQ_HANDLER 62 /* ENET0 IRQ handler */
+    IRQ_HANDLER 63 /* SDXC0 IRQ handler */
+    IRQ_HANDLER 64 /* PSEC IRQ handler */
+    IRQ_HANDLER 65 /* PGPIO IRQ handler */
+    IRQ_HANDLER 66 /* PWDG IRQ handler */
+    IRQ_HANDLER 67 /* PTMR IRQ handler */
+    IRQ_HANDLER 68 /* PUART IRQ handler */
+    IRQ_HANDLER 69 /* FUSE IRQ handler */
+    IRQ_HANDLER 70 /* SECMON IRQ handler */
+    IRQ_HANDLER 71 /* RTC IRQ handler */
+    IRQ_HANDLER 72 /* BUTN IRQ handler */
+    IRQ_HANDLER 73 /* BGPIO IRQ handler */
+    IRQ_HANDLER 74 /* BVIO IRQ handler */
+    IRQ_HANDLER 75 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 76 /* SYSCTL IRQ handler */
+    IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */
+    IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */

bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <rtthread.h>
+#include "riscv-stackframe.h"
+
+#define MCAUSE_INSTR_ADDR_MISALIGNED (0U)       //!< Instruction Address misaligned
+#define MCAUSE_INSTR_ACCESS_FAULT (1U)          //!< Instruction access fault
+#define MCAUSE_ILLEGAL_INSTR (2U)               //!< Illegal instruction
+#define MCAUSE_BREAKPOINT (3U)                  //!< Breakpoint
+#define MCAUSE_LOAD_ADDR_MISALIGNED (4U)        //!< Load address misaligned
+#define MCAUSE_LOAD_ACCESS_FAULT (5U)           //!< Load access fault
+#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U)   //!< Store/AMO address misaligned
+#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U)      //!< Store/AMO access fault
+#define MCAUSE_ECALL_FROM_USER_MODE (8U)        //!< Environment call from User mode
+#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U)  //!< Environment call from Supervisor mode
+#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U)    //!< Environment call from machine mode
+#define MCAUSE_INSTR_PAGE_FAULT (12U)           //!< Instruction page fault
+#define MCAUSE_LOAD_PAGE_FAULT (13)             //!< Load page fault
+#define MCAUSE_STORE_AMO_PAGE_FAULT (15U)       //!< Store/AMO page fault
+
+#define IRQ_S_SOFT              1
+#define IRQ_H_SOFT              2
+#define IRQ_M_SOFT              3
+#define IRQ_S_TIMER             5
+#define IRQ_H_TIMER             6
+#define IRQ_M_TIMER             7
+#define IRQ_S_EXT               9
+#define IRQ_H_EXT               10
+#define IRQ_M_EXT               11
+#define IRQ_COP                 12
+#define IRQ_HOST                13
+
+typedef void (*isr_func_t)(void);
+
+static volatile rt_hw_stack_frame_t *s_stack_frame;
+
+static void rt_show_stack_frame(void);
+
+__attribute((weak)) void mchtmr_isr(void)
+{
+}
+
+__attribute__((weak)) void mswi_isr(void)
+{
+}
+
+__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
+{
+}
+
+uint32_t exception_handler(uint32_t cause, uint32_t epc)
+{
+    /* Unhandled Trap */
+    uint32_t mdcause = read_csr(CSR_MDCAUSE);
+    uint32_t mtval = read_csr(CSR_MTVAL);
+    switch (cause)
+    {
+    case MCAUSE_INSTR_ADDR_MISALIGNED:
+        rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_INSTR_ACCESS_FAULT:
+        rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_ILLEGAL_INSTR:
+        rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        switch (mdcause & 0x07)
+        {
+        case 0:
+            rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            break;
+        case 1:
+            rt_kprintf("mdcause: FP disabled exception \r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: ACE disabled exception \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_BREAKPOINT:
+        rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ADDR_MISALIGNED:
+        rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ACCESS_FAULT:
+        rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
+        rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc);
+        break;
+    case MCAUSE_STORE_AMO_ACCESS_FAULT:
+        rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        case 7:
+            rt_kprintf("mdcause: PMA NAMO exception \r\n");
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    default:
+        rt_kprintf("Unknown exception happened, cause=%d\n", cause);
+        break;
+    }
+
+    rt_show_stack_frame();
+    while (1)
+    {
+    }
+}
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame);
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame)
+{
+    uint32_t mcause = read_csr(CSR_MCAUSE);
+    uint32_t mepc = read_csr(CSR_MEPC);
+    uint32_t mstatus = read_csr(CSR_MSTATUS);
+
+    s_stack_frame = stack_frame;
+
+#if SUPPORT_PFT_ARCH
+    uint32_t mxstatus = read_csr(CSR_MXSTATUS);
+#endif
+#ifdef __riscv_dsp
+    int ucode = read_csr(CSR_UCODE);
+#endif
+#ifdef __riscv_flen
+    int fcsr = read_fcsr();
+#endif
+
+    /* clobbers list for ecall */
+#ifdef __riscv_32e
+    __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
+#else
+    __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
+#endif
+
+    /* Do your trap handling */
+    uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
+    uint32_t irq_index;
+    if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
+    {
+        switch (cause_type)
+        {
+        /* Machine timer interrupt */
+        case IRQ_M_TIMER:
+            mchtmr_isr();
+            break;
+            /* Machine EXT interrupt */
+        case IRQ_M_EXT:
+            /* Claim interrupt */
+            irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
+            /* Execute EXT interrupt handler */
+            if (irq_index > 0)
+            {
+                ((isr_func_t) __vector_table[irq_index])();
+                /* Complete interrupt */
+                __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
+            }
+            break;
+            /* Machine SWI interrupt */
+        case IRQ_M_SOFT:
+            mswi_isr();
+            intc_m_complete_swi();
+            break;
+        }
+    }
+    else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
+    {
+        /* Machine Syscal call */
+        __asm volatile(
+                "mv a4, a3\n"
+                "mv a3, a2\n"
+                "mv a2, a1\n"
+                "mv a1, a0\n"
+#ifdef __riscv_32e
+                "mv a0, t0\n"
+#else
+                "mv a0, a7\n"
+#endif
+                "call syscall_handler\n"
+                : : : "a4"
+        );
+        mepc += 4;
+    }
+    else
+    {
+        mepc = exception_handler(mcause, mepc);
+    }
+
+    /* Restore CSR */
+    write_csr(CSR_MSTATUS, mstatus);
+    write_csr(CSR_MEPC, mepc);
+#if SUPPORT_PFT_ARCH
+    write_csr(CSR_MXSTATUS, mxstatus);
+#endif
+#ifdef __riscv_dsp
+    write_csr(CSR_UCODE, ucode);
+#endif
+#ifdef __riscv_flen
+    write_fcsr(fcsr);
+#endif
+}
+
+static void rt_show_stack_frame(void)
+{
+    rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
+    rt_kprintf("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS));
+    rt_kprintf("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    rt_kprintf("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    rt_kprintf("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    rt_kprintf("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    rt_kprintf("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    rt_kprintf("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+    rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+}

bsp/hpmicro/hpm6750evk/startup/HPM6750/SConscript

@@ -0,0 +1,21 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the startup files
+
+src = Split('''
+   startup.c
+   trap.c
+''')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', rtconfig.CHIP_NAME]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ *
+ */
+
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_l1c_drv.h"
+#include <rtthread.h>
+
+void system_init(void);
+
+extern int entry(void);
+
+extern void __libc_init_array(void);
+extern void __libc_fini_array(void);
+
+void system_init(void)
+{
+    disable_global_irq(CSR_MSTATUS_MIE_MASK);
+    disable_irq_from_intc();
+    enable_irq_from_intc();
+    enable_global_irq(CSR_MSTATUS_MIE_MASK);
+#ifndef CONFIG_NOT_ENABLE_ICACHE
+    l1c_ic_enable();
+#endif
+#ifndef CONFIG_NOT_ENABLE_DCACHE
+    l1c_dc_enable();
+#endif
+}
+
+__attribute__((weak)) void c_startup(void)
+{
+    uint32_t i, size;
+#ifdef FLASH_XIP
+    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+    size = __vector_ram_end__ - __vector_ram_start__;
+    for (i = 0; i < size; i++) {
+        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+    }
+#endif
+
+    extern uint8_t __etext[];
+    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __data_start__[], __data_end__[];
+    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+
+    /* bss section */
+    size = __bss_end__ - __bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__bss_start__ + i) = 0;
+    }
+
+    /* noncacheable bss section */
+    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_bss_start__ + i) = 0;
+    }
+
+    /* data section LMA: etext */
+    size = __data_end__ - __data_start__;
+    for (i = 0; i < size; i++) {
+        *(__data_start__ + i) = *(__etext + i);
+    }
+
+    /* ramfunc section LMA: etext + data length */
+    size = __ramfunc_end__ - __ramfunc_start__;
+    for (i = 0; i < size; i++) {
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+    }
+
+    /* noncacheable init section LMA: etext + data length + ramfunc length */
+    size = __noncacheable_init_end__ - __noncacheable_init_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+    }
+}
+
+__attribute__((weak)) int main(void)
+{
+    while(1);
+}
+
+void reset_handler(void)
+{
+    /**
+     * Disable preemptive interrupt
+     */
+    HPM_PLIC->FEATURE = 0;
+    /*
+     * Initialize LMA/VMA sections.
+     * Relocation for any sections that need to be copied from LMA to VMA.
+     */
+    c_startup();
+
+    /* Call platform specific hardware initialization */
+    system_init();
+
+    /* Do global constructors */
+    __libc_init_array();
+
+
+
+    /* Entry function */
+    entry();
+}
+
+
+__attribute__((weak)) void _init()
+{
+}

bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+ #include <rtconfig.h>
+ #include "hpm_csr_regs.h"
+    .section .start, "ax"
+
+    .global _start
+    .type _start,@function
+
+_start:
+    /* Initialize global pointer */
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop
+
+#ifdef INIT_EXT_RAM_FOR_DATA
+    la t0, _stack_in_dlm
+    mv sp, t0
+    call _init_ext_ram
+#endif
+
+    /* Initialize stack pointer */
+    la t0, _stack
+    mv sp, t0
+
+#ifdef __nds_execit
+    /* Initialize EXEC.IT table */
+    la t0, _ITB_BASE_
+    csrw uitb, t0
+#endif
+
+#ifdef __riscv_flen
+    /* Enable FPU */
+    li t0, CSR_MSTATUS_FS_MASK
+    csrrs t0, mstatus, t0
+
+    /* Initialize FCSR */
+    fscsr zero
+#endif
+    /* Disable Vector mode */
+    csrci CSR_MMISC_CTL, 2
+    /* Initialize trap_entry base */
+    la t0, irq_handler_trap
+    csrw mtvec, t0
+
+
+    /* System reset handler */
+    call reset_handler
+
+    /* Infinite loop, if returned accidently */
+1:    j 1b
+
+    .weak nmi_handler
+nmi_handler:
+1:    j 1b
+
+    .global default_irq_handler
+    .weak default_irq_handler
+    .align 2
+default_irq_handler:
+1:    j 1b
+
+    .macro IRQ_HANDLER irq
+    .weak default_isr_\irq
+    .set default_isr_\irq, default_irq_handler
+    .long default_isr_\irq
+    .endm
+
+#include "vectors.S"

bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+    .section .vector_table, "a"
+    .global __vector_table
+    .align 9
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, irq_handler_trap
+    .long default_isr_trap
+    IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_E IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_F IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */
+    IRQ_HANDLER 10 /* GPIO1_A IRQ handler */
+    IRQ_HANDLER 11 /* GPIO1_B IRQ handler */
+    IRQ_HANDLER 12 /* GPIO1_C IRQ handler */
+    IRQ_HANDLER 13 /* GPIO1_D IRQ handler */
+    IRQ_HANDLER 14 /* GPIO1_E IRQ handler */
+    IRQ_HANDLER 15 /* GPIO1_F IRQ handler */
+    IRQ_HANDLER 16 /* GPIO1_X IRQ handler */
+    IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */
+    IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */
+    IRQ_HANDLER 19 /* ADC0 IRQ handler */
+    IRQ_HANDLER 20 /* ADC1 IRQ handler */
+    IRQ_HANDLER 21 /* ADC2 IRQ handler */
+    IRQ_HANDLER 22 /* ADC3 IRQ handler */
+    IRQ_HANDLER 23 /* ACMP[0] IRQ handler */
+    IRQ_HANDLER 24 /* ACMP[1] IRQ handler */
+    IRQ_HANDLER 25 /* ACMP[2] IRQ handler */
+    IRQ_HANDLER 26 /* ACMP[3] IRQ handler */
+    IRQ_HANDLER 27 /* SPI0 IRQ handler */
+    IRQ_HANDLER 28 /* SPI1 IRQ handler */
+    IRQ_HANDLER 29 /* SPI2 IRQ handler */
+    IRQ_HANDLER 30 /* SPI3 IRQ handler */
+    IRQ_HANDLER 31 /* UART0 IRQ handler */
+    IRQ_HANDLER 32 /* UART1 IRQ handler */
+    IRQ_HANDLER 33 /* UART2 IRQ handler */
+    IRQ_HANDLER 34 /* UART3 IRQ handler */
+    IRQ_HANDLER 35 /* UART4 IRQ handler */
+    IRQ_HANDLER 36 /* UART5 IRQ handler */
+    IRQ_HANDLER 37 /* UART6 IRQ handler */
+    IRQ_HANDLER 38 /* UART7 IRQ handler */
+    IRQ_HANDLER 39 /* UART8 IRQ handler */
+    IRQ_HANDLER 40 /* UART9 IRQ handler */
+    IRQ_HANDLER 41 /* UART10 IRQ handler */
+    IRQ_HANDLER 42 /* UART11 IRQ handler */
+    IRQ_HANDLER 43 /* UART12 IRQ handler */
+    IRQ_HANDLER 44 /* UART13 IRQ handler */
+    IRQ_HANDLER 45 /* UART14 IRQ handler */
+    IRQ_HANDLER 46 /* UART15 IRQ handler */
+    IRQ_HANDLER 47 /* CAN0 IRQ handler */
+    IRQ_HANDLER 48 /* CAN1 IRQ handler */
+    IRQ_HANDLER 49 /* CAN2 IRQ handler */
+    IRQ_HANDLER 50 /* CAN3 IRQ handler */
+    IRQ_HANDLER 51 /* PTPC IRQ handler */
+    IRQ_HANDLER 52 /* WDG0 IRQ handler */
+    IRQ_HANDLER 53 /* WDG1 IRQ handler */
+    IRQ_HANDLER 54 /* WDG2 IRQ handler */
+    IRQ_HANDLER 55 /* WDG3 IRQ handler */
+    IRQ_HANDLER 56 /* MBX0_CA IRQ handler */
+    IRQ_HANDLER 57 /* MBX0_CB IRQ handler */
+    IRQ_HANDLER 58 /* MBX1_CA IRQ handler */
+    IRQ_HANDLER 59 /* MBX1_CB IRQ handler */
+    IRQ_HANDLER 60 /* TMR0 IRQ handler */
+    IRQ_HANDLER 61 /* TMR1 IRQ handler */
+    IRQ_HANDLER 62 /* TMR2 IRQ handler */
+    IRQ_HANDLER 63 /* TMR3 IRQ handler */
+    IRQ_HANDLER 64 /* TMR4 IRQ handler */
+    IRQ_HANDLER 65 /* TMR5 IRQ handler */
+    IRQ_HANDLER 66 /* TMR6 IRQ handler */
+    IRQ_HANDLER 67 /* TMR7 IRQ handler */
+    IRQ_HANDLER 68 /* I2C0 IRQ handler */
+    IRQ_HANDLER 69 /* I2C1 IRQ handler */
+    IRQ_HANDLER 70 /* I2C2 IRQ handler */
+    IRQ_HANDLER 71 /* I2C3 IRQ handler */
+    IRQ_HANDLER 72 /* PWM0 IRQ handler */
+    IRQ_HANDLER 73 /* HAL0 IRQ handler */
+    IRQ_HANDLER 74 /* ENC0 IRQ handler */
+    IRQ_HANDLER 75 /* PWM1 IRQ handler */
+    IRQ_HANDLER 76 /* HAL1 IRQ handler */
+    IRQ_HANDLER 77 /* ENC1 IRQ handler */
+    IRQ_HANDLER 78 /* PWM2 IRQ handler */
+    IRQ_HANDLER 79 /* HAL2 IRQ handler */
+    IRQ_HANDLER 80 /* ENC2 IRQ handler */
+    IRQ_HANDLER 81 /* PWM3 IRQ handler */
+    IRQ_HANDLER 82 /* HAL3 IRQ handler */
+    IRQ_HANDLER 83 /* ENC3 IRQ handler */
+    IRQ_HANDLER 84 /* SDP IRQ handler */
+    IRQ_HANDLER 85 /* XPI0 IRQ handler */
+    IRQ_HANDLER 86 /* XPI1 IRQ handler */
+    IRQ_HANDLER 87 /* XDMA IRQ handler */
+    IRQ_HANDLER 88 /* HDMA IRQ handler */
+    IRQ_HANDLER 89 /* DRAM IRQ handler */
+    IRQ_HANDLER 90 /* RNG IRQ handler */
+    IRQ_HANDLER 91 /* I2S0 IRQ handler */
+    IRQ_HANDLER 92 /* I2S1 IRQ handler */
+    IRQ_HANDLER 93 /* I2S2 IRQ handler */
+    IRQ_HANDLER 94 /* I2S3 IRQ handler */
+    IRQ_HANDLER 95 /* I2SCLASSD IRQ handler */
+    IRQ_HANDLER 96 /* I2SPDM IRQ handler */
+    IRQ_HANDLER 97 /* CAM0 IRQ handler */
+    IRQ_HANDLER 98 /* CAM1 IRQ handler */
+    IRQ_HANDLER 99 /* LCD_D0 IRQ handler */
+    IRQ_HANDLER 100 /* LCD_D1 IRQ handler */
+    IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */
+    IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */
+    IRQ_HANDLER 103 /* JPEG IRQ handler */
+    IRQ_HANDLER 104 /* NTM0 IRQ handler */
+    IRQ_HANDLER 105 /* NTM1 IRQ handler */
+    IRQ_HANDLER 106 /* USB0 IRQ handler */
+    IRQ_HANDLER 107 /* USB1 IRQ handler */
+    IRQ_HANDLER 108 /* ENET0 IRQ handler */
+    IRQ_HANDLER 109 /* ENET1 IRQ handler */
+    IRQ_HANDLER 110 /* SDXC0 IRQ handler */
+    IRQ_HANDLER 111 /* SDXC1 IRQ handler */
+    IRQ_HANDLER 112 /* SEC_EVENT IRQ handler */
+    IRQ_HANDLER 113 /* PMIC_GPIO IRQ handler */
+    IRQ_HANDLER 114 /* PMIC_WDG IRQ handler */
+    IRQ_HANDLER 115 /* PMIC_TMR IRQ handler */
+    IRQ_HANDLER 116 /* PMIC_UART IRQ handler */
+    IRQ_HANDLER 117 /* VAD IRQ handler */
+    IRQ_HANDLER 118 /* FUSE IRQ handler */
+    IRQ_HANDLER 119 /* SECMON IRQ handler */
+    IRQ_HANDLER 120 /* BATT_RTC IRQ handler */
+    IRQ_HANDLER 121 /* BUTTON IRQ handler */
+    IRQ_HANDLER 122 /* BATT_GPIO IRQ handler */
+    IRQ_HANDLER 123 /* VIOLATION IRQ handler */
+    IRQ_HANDLER 124 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 125 /* CLK_FAIL IRQ handler */
+    IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */
+    IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */

bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <rtthread.h>
+#include "riscv-stackframe.h"
+
+#define MCAUSE_INSTR_ADDR_MISALIGNED (0U)       //!< Instruction Address misaligned
+#define MCAUSE_INSTR_ACCESS_FAULT (1U)          //!< Instruction access fault
+#define MCAUSE_ILLEGAL_INSTR (2U)               //!< Illegal instruction
+#define MCAUSE_BREAKPOINT (3U)                  //!< Breakpoint
+#define MCAUSE_LOAD_ADDR_MISALIGNED (4U)        //!< Load address misaligned
+#define MCAUSE_LOAD_ACCESS_FAULT (5U)           //!< Load access fault
+#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U)   //!< Store/AMO address misaligned
+#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U)      //!< Store/AMO access fault
+#define MCAUSE_ECALL_FROM_USER_MODE (8U)        //!< Environment call from User mode
+#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U)  //!< Environment call from Supervisor mode
+#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U)    //!< Environment call from machine mode
+#define MCAUSE_INSTR_PAGE_FAULT (12U)           //!< Instruction page fault
+#define MCAUSE_LOAD_PAGE_FAULT (13)             //!< Load page fault
+#define MCAUSE_STORE_AMO_PAGE_FAULT (15U)       //!< Store/AMO page fault
+
+#define IRQ_S_SOFT              1
+#define IRQ_H_SOFT              2
+#define IRQ_M_SOFT              3
+#define IRQ_S_TIMER             5
+#define IRQ_H_TIMER             6
+#define IRQ_M_TIMER             7
+#define IRQ_S_EXT               9
+#define IRQ_H_EXT               10
+#define IRQ_M_EXT               11
+#define IRQ_COP                 12
+#define IRQ_HOST                13
+
+typedef void (*isr_func_t)(void);
+
+static volatile rt_hw_stack_frame_t *s_stack_frame;
+
+static void rt_show_stack_frame(void);
+
+__attribute((weak)) void mchtmr_isr(void)
+{
+}
+
+__attribute__((weak)) void mswi_isr(void)
+{
+}
+
+__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
+{
+}
+
+uint32_t exception_handler(uint32_t cause, uint32_t epc)
+{
+    /* Unhandled Trap */
+    uint32_t mdcause = read_csr(CSR_MDCAUSE);
+    uint32_t mtval = read_csr(CSR_MTVAL);
+    switch (cause)
+    {
+    case MCAUSE_INSTR_ADDR_MISALIGNED:
+        rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_INSTR_ACCESS_FAULT:
+        rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_ILLEGAL_INSTR:
+        rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        switch (mdcause & 0x07)
+        {
+        case 0:
+            rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            break;
+        case 1:
+            rt_kprintf("mdcause: FP disabled exception \r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: ACE disabled exception \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_BREAKPOINT:
+        rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ADDR_MISALIGNED:
+        rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ACCESS_FAULT:
+        rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
+        rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc);
+        break;
+    case MCAUSE_STORE_AMO_ACCESS_FAULT:
+        rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        case 7:
+            rt_kprintf("mdcause: PMA NAMO exception \r\n");
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    default:
+        rt_kprintf("Unknown exception happened, cause=%d\n", cause);
+        break;
+    }
+
+    rt_show_stack_frame();
+    while (1)
+    {
+    }
+}
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame);
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame)
+{
+    uint32_t mcause = read_csr(CSR_MCAUSE);
+    uint32_t mepc = read_csr(CSR_MEPC);
+    uint32_t mstatus = read_csr(CSR_MSTATUS);
+
+    s_stack_frame = stack_frame;
+
+#if SUPPORT_PFT_ARCH
+    uint32_t mxstatus = read_csr(CSR_MXSTATUS);
+#endif
+#ifdef __riscv_dsp
+    int ucode = read_csr(CSR_UCODE);
+#endif
+#ifdef __riscv_flen
+    int fcsr = read_fcsr();
+#endif
+
+    /* clobbers list for ecall */
+#ifdef __riscv_32e
+    __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
+#else
+    __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
+#endif
+
+    /* Do your trap handling */
+    uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
+    uint32_t irq_index;
+    if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
+    {
+        switch (cause_type)
+        {
+        /* Machine timer interrupt */
+        case IRQ_M_TIMER:
+            mchtmr_isr();
+            break;
+            /* Machine EXT interrupt */
+        case IRQ_M_EXT:
+            /* Claim interrupt */
+            irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
+            /* Execute EXT interrupt handler */
+            if (irq_index > 0)
+            {
+                ((isr_func_t) __vector_table[irq_index])();
+                /* Complete interrupt */
+                __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
+            }
+            break;
+            /* Machine SWI interrupt */
+        case IRQ_M_SOFT:
+            mswi_isr();
+            intc_m_complete_swi();
+            break;
+        }
+    }
+    else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
+    {
+        /* Machine Syscal call */
+        __asm volatile(
+                "mv a4, a3\n"
+                "mv a3, a2\n"
+                "mv a2, a1\n"
+                "mv a1, a0\n"
+#ifdef __riscv_32e
+                "mv a0, t0\n"
+#else
+                "mv a0, a7\n"
+#endif
+                "call syscall_handler\n"
+                : : : "a4"
+        );
+        mepc += 4;
+    }
+    else
+    {
+        mepc = exception_handler(mcause, mepc);
+    }
+
+    /* Restore CSR */
+    write_csr(CSR_MSTATUS, mstatus);
+    write_csr(CSR_MEPC, mepc);
+#if SUPPORT_PFT_ARCH
+    write_csr(CSR_MXSTATUS, mxstatus);
+#endif
+#ifdef __riscv_dsp
+    write_csr(CSR_UCODE, ucode);
+#endif
+#ifdef __riscv_flen
+    write_fcsr(fcsr);
+#endif
+}
+
+static void rt_show_stack_frame(void)
+{
+    rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
+    rt_kprintf("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS));
+    rt_kprintf("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    rt_kprintf("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    rt_kprintf("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    rt_kprintf("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    rt_kprintf("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    rt_kprintf("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+    rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+}

bsp/hpmicro/hpm6750evk/startup/SConscript

@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')

bsp/hpmicro/hpm6750evkmini/.config

@@ -0,0 +1,717 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+CONFIG_RT_USING_LEGACY=y
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Sensor libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display libraries
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HPM6000=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_RW007_USING_BLE is not set
+# CONFIG_RW007_USING_WIFI is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART13 is not set
+# CONFIG_BSP_USING_UART14 is not set
+# CONFIG_BSP_USING_SPI is not set
+CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SDXC is not set
+# CONFIG_BSP_USING_TOUCH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_GPTMR is not set
+# CONFIG_BSP_USING_I2C is not set
+CONFIG_BSP_USING_DRAM=y
+CONFIG_INIT_EXT_RAM_FOR_DATA=y
+# CONFIG_BSP_USING_XPI_FLASH is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_DAO is not set
+# CONFIG_BSP_USING_PDM is not set
+# CONFIG_BSP_USING_I2S is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_WDG is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_ADC is not set

bsp/hpmicro/hpm6750evkmini/.settings/blink_led.OpenOCD.Debug.rttlaunch

@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-hpmicro_debugger_relative_path}/bin/openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f ${project_loc}/board/debug_scripts/openocd/probes/ft2232.cfg&#13;&#10;-f ${project_loc}/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg&#13;&#10;-f ${project_loc}/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${toolchain_install_path}/${risc-v-gcc-rv32_relative_path}/bin/${cross_prefix}gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${config_name}/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="blink_led"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/blink_led"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

bsp/hpmicro/hpm6750evkmini/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.512258282=${toolchain_install_path}/RISC-V/RISC-V-GCC-RV32/2022-04-12/bin

bsp/hpmicro/hpm6750evkmini/.settings/language.settings.xml

@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.576542909" name="flash_debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1420929001440872898" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.576542909.2015579467" name="ram_debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1472663581447918959" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8

bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini

@@ -0,0 +1,19 @@
+#RT-Thread Studio Project Configuration
+#Thu Feb 17 15:17:36 CST 2022
+cfg_version=v3.0
+board_name=HPM6750EVKMINI
+example_name=blink_led
+hardware_adapter=FT2232
+project_type=rt-thread
+board_base_nano_proj=False
+chip_name=HPM6750
+selected_rtt_version=4.0.5
+bsp_version=0.3.0
+os_branch=full
+output_project_path=C\:/DevTools/RT-ThreadStudio/workspace
+is_base_example_project=True
+is_use_scons_build=True
+project_base_bsp=true
+project_name=blink_led
+os_version=4.0.5
+bsp_path=repo/Local/Board_Support_Packages/HPMicro/HPM6750EVKMINI/0.3.0(offline)/hpm6750-rtt-bsp

bsp/hpmicro/hpm6750evkmini/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hpmicro/hpm6750evkmini/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hpmicro/hpm6750evkmini/SConstruct

@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hpmicro/hpm6750evkmini/applications/SConscript

@@ -0,0 +1,14 @@
+import rtconfig
+
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('*.c')
+
+CPPDEFINES=[]
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evkmini/applications/main.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+
+void thread_entry(void *arg);
+
+
+
+int main(void)
+{
+
+    app_init_led_pins();
+
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    while(1){
+        app_led_write(0, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(0, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}

bsp/hpmicro/hpm6750evkmini/board/Kconfig

@@ -0,0 +1,417 @@
+menu "Hardware Drivers Config"
+
+config SOC_HPM6000
+    bool
+    select SOC_SERIES_HPM6000
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+        
+    config RW007_USING_BLE
+    	bool "Enable RW007 BLE"
+    	default n
+    	select RT_USING_SPI if RW007_USING_BLE
+    	select BSP_USING_SPI1 if RW007_USING_BLE
+    	
+    config RW007_USING_WIFI
+    	bool "Enable RW007 WIFI"
+    	select RT_USING_SPI if RW007_USING_BLE
+    	select BSP_USING_SPI1 if RW007_USING_BLE
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART0
+                bool "Enable UART0 (Debugger)"
+                default y
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_USING_DMA
+                        bool "Enable UART0 RX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_TX_USING_DMA
+                        bool "Enable UART0 TX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_RX_DMA_CHANNEL
+                        int "Set UART0 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART0_TX_DMA_CHANNEL
+                        int "Set UART0 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART0_RX_BUFSIZE
+                        int "Set UART0 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART0_TX_BUFSIZE
+                        int "Set UART0 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_USING_DMA
+                        bool "Enable UART6 RX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_TX_USING_DMA
+                        bool "Enable UART6 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_RX_DMA_CHANNEL
+                        int "Set UART6 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART6_TX_DMA_CHANNEL
+                        int "Set UART6 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART13
+                bool "Enable UART13"
+                default n
+                if BSP_USING_UART13
+                    config BSP_UART13_RX_USING_DMA
+                        bool "Enable UART13 RX DMA"
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART13_TX_USING_DMA
+                        bool "Enable UART13 TX DMA"
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART13_RX_DMA_CHANNEL
+                        int "Set UART13 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART13_TX_DMA_CHANNEL
+                        int "Set UART13 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART13_RX_BUFSIZE
+                        int "Set UART13 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART13_TX_BUFSIZE
+                        int "Set UART13 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART14
+                bool "Enable UART14"
+                default n
+                if BSP_USING_UART14
+                    config BSP_UART14_RX_USING_DMA
+                        bool "Enable UART14 RX DMA"
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART14_TX_USING_DMA
+                        bool "Enable UART14 TX DMA"
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART14_RX_DMA_CHANNEL
+                        int "Set UART14 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART14_TX_DMA_CHANNEL
+                        int "Set UART14 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART14_RX_BUFSIZE
+                        int "Set UART14 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART14_TX_BUFSIZE
+                        int "Set UART14 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+
+
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                    default y
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                    default n
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_RTC
+       bool "Enable RTC"
+       default n
+
+    menuconfig BSP_USING_ETH
+       bool "Enable Ethernet"
+       default n
+       select RT_USING_ETH
+        if BSP_USING_ETH
+            config BSP_USING_ETH1
+                bool "Enable ETH1"
+                    default n
+        endif
+
+    menuconfig BSP_USING_SDXC
+        bool "Enable SDXC"
+        default n
+        select RT_USING_SDIO if BSP_USING_SDXC
+        if BSP_USING_SDXC
+            config BSP_USING_SDXC0
+                bool "Enable SDXC0"
+                    default n
+
+            config BSP_USING_SDXC1
+                bool "Enable SDXC1"
+                    default y
+        endif
+
+    menuconfig BSP_USING_TOUCH
+       bool "Enable touch"
+       default n
+        if BSP_USING_TOUCH
+            config BSP_USING_TOUCH_GT911
+                bool "Enable GT911"
+                    default y
+
+            config BSP_USING_TOUCH_FT5406
+                bool "Enable FT5406"
+                    default n
+        endif
+
+    menuconfig BSP_USING_LCD
+    	bool "Enable LCD"
+    	default n
+
+    menuconfig BSP_USING_LVGL
+        bool "Enable LVGL"
+        default n
+        select PKG_USING_LVGL if BSP_USING_LVGL
+
+    menuconfig BSP_USING_GPTMR
+	   	bool "Enable GPTMR"
+	   	default n
+	   	select RT_USING_HWTIMER if BSP_USING_GPTMR
+	   	if BSP_USING_GPTMR
+	   		config BSP_USING_GPTMR1
+	   			bool "Enable GPTMR1"
+	   			default n
+	   		config BSP_USING_GPTMR2
+	   			bool "Enable GPTMR2"
+	   			default n
+	   		config BSP_USING_GPTMR3
+	   			bool "Enable GPTMR3"
+	   			default n
+	   		config BSP_USING_GPTMR4
+	   			bool "Enable GPTMR4"
+	   			default n
+	   		config BSP_USING_GPTMR5
+	   			bool "Enable GPTMR5"
+	   			default n
+	   		config BSP_USING_GPTMR6
+	   			bool "Enable GPTMR6"
+	   			default n
+	   		config BSP_USING_GPTMR7
+	   			bool "Enable GPTMR7"
+	   			default n
+        endif
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                    default y
+
+            config BSP_USING_I2C3
+                bool "Enable I2C3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_DRAM
+       bool "Enable DRAM"
+       default y
+    menuconfig INIT_EXT_RAM_FOR_DATA
+        bool "INIT_EXT_RAM_FOR_DATA"
+        default y
+
+
+    menuconfig BSP_USING_XPI_FLASH
+    	bool "Enable XPI FLASH"
+	default n
+    	select PKG_USING_FAL if BSP_USING_XPI_FLASH
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+	default n
+
+    menuconfig BSP_USING_DAO
+        bool "Enable Audio DAO play"
+        default n
+        select RT_USING_AUDIO if BSP_USING_DAO
+
+    menuconfig BSP_USING_PDM
+        bool "Enable Audio PDM record"
+        default n
+        select RT_USING_AUDIO if BSP_USING_PDM
+
+    menuconfig BSP_USING_I2S
+        bool "Enable Audio I2S device"
+        default n
+        select RT_USING_AUDIO if BSP_USING_I2S
+        if BSP_USING_I2S
+            config BSP_USING_I2S0
+                bool "Enable I2S0"
+                    default y
+        endif
+
+    menuconfig BSP_USING_USB
+       bool "Enable USB"
+       default n
+       if BSP_USING_USB
+       		config BSP_USING_USB_DEVICE
+                bool "Enable USB Device"
+                    default n
+            config BSP_USING_USB_HOST
+                bool "Enable USB HOST"
+                    default n
+       endif
+
+
+     menuconfig BSP_USING_WDG
+     	bool "Enable Watchdog"
+     	default n
+     	select RT_USING_WDT if BSP_USING_WDG
+     	if BSP_USING_WDG
+     		config BSP_USING_WDG0
+     			bool "Enable WDG0"
+     			default n
+     		config BSP_USING_WDG1
+     			bool "Enable WDG1"
+     			default n
+     		config BSP_USING_WDG2
+     			bool "Enable WDG2"
+     			default n
+     		config BSP_USING_WDG3
+     			bool "Enable WDG3"
+     			default n
+     	endif
+
+     menuconfig BSP_USING_CAN
+     	bool "Enable CAN"
+     	default n
+     	select RT_USING_CAN if BSP_USING_CAN
+     	if BSP_USING_CAN
+     		config BSP_USING_CAN0
+     			bool "Enable CAN0"
+     			default n
+     		config BSP_USING_CAN1
+     			bool "Enable CAN1"
+     			default n
+     		config BSP_USING_CAN2
+     			bool "Enable CAN2"
+     			default n
+     		config BSP_USING_CAN3
+     			bool "Enable CAN3"
+     			default n
+     	endif
+
+     menuconfig BSP_USING_ADC
+     	bool "Enable ADC"
+     	default n
+     	select RT_USING_ADC if BSP_USING_ADC
+     	if BSP_USING_ADC
+     		menuconfig BSP_USING_ADC12
+     		bool "Enable ADC12"
+     		default n
+     			if BSP_USING_ADC12
+		     		config BSP_USING_ADC0
+		     			bool "Enable ADC0"
+		     			default n
+		     		config BSP_USING_ADC1
+		     			bool "Enable ADC1"
+		     			default n
+		     		config BSP_USING_ADC2
+		     			bool "Enable ADC2"
+		     			default n
+		     	endif
+	     	if !BSP_USING_ADC12
+		     	menuconfig BSP_USING_ADC16
+	     		bool "Enable ADC16"
+	     		default n
+	     			if BSP_USING_ADC16
+			     		config BSP_USING_ADC3
+			     			bool "Enable ADC3"
+			     			default n
+		     		endif
+	     	endif
+         endif
+endmenu
+
+
+
+endmenu

bsp/hpmicro/hpm6750evkmini/board/SConscript

@@ -0,0 +1,20 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    rw007_port.c
+    eth_phy_port.c
+    fal_flash_port.c 
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6750']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evkmini/board/board.c

@@ -0,0 +1,969 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gptmr_drv.h"
+#include "hpm_lcdc_drv.h"
+#include "hpm_i2c_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_debug_console.h"
+#include "hpm_dram_drv.h"
+#include "pinmux.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include "hpm_sdxc_drv.h"
+#include "hpm_sdxc_soc_drv.h"
+#include "hpm_pllctl_drv.h"
+
+static board_timer_cb timer_cb;
+
+/**
+ * @brief FLASH configuration option definitions:
+ * option[0]:
+ *    [31:16] 0xfcf9 - FLASH configuration option tag
+ *    [15:4]  0 - Reserved
+ *    [3:0]   option words (exclude option[0])
+ * option[1]:
+ *    [31:28] Flash probe type
+ *      0 - SFDP SDR / 1 - SFDP DDR
+ *      2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+ *      4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+ *      6 - OctaBus DDR (SPI -> OPI DDR)
+ *      8 - Xccela DDR (SPI -> OPI DDR)
+ *      10 - EcoXiP DDR (SPI -> OPI DDR)
+ *    [27:24] Command Pads after Power-on Reset
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [23:20] Command Pads after Configuring FLASH
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+ *      0 - Not needed
+ *      1 - QE bit is at bit 6 in Status Register 1
+ *      2 - QE bit is at bit1 in Status Register 2
+ *      3 - QE bit is at bit7 in Status Register 2
+ *      4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+ *    [15:8] Dummy cycles
+ *      0 - Auto-probed / detected / default value
+ *      Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+ *    [7:4] Misc.
+ *      0 - Not used
+ *      1 - SPI mode
+ *      2 - Internal loopback
+ *      3 - External DQS
+ *    [3:0] Frequency option
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+ *
+ * option[2] (Effective only if the bit[3:0] in option[0] > 1)
+ *    [31:20]  Reserved
+ *    [19:16] IO voltage
+ *      0 - 3V / 1 - 1.8V
+ *    [15:12] Pin group
+ *      0 - 1st group / 1 - 2nd group
+ *    [11:8] Connection selection
+ *      0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+ *    [7:0] Drive Strength
+ *      0 - Default value
+ * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
+ *              JESD216)
+ *    [31:16] reserved
+ *    [15:12] Sector Erase Command Option, not required here
+ *    [11:8]  Sector Size Option, not required here
+ *    [7:0] Flash Size Option
+ *      0 - 4MB / 1 - 8MB / 2 - 16MB
+ */
+#if defined(FLASH_XIP) && FLASH_XIP
+__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0};
+#endif
+
+void board_init_console(void)
+{
+#if BOARD_CONSOLE_TYPE == console_type_uart
+    console_config_t cfg;
+
+    /* Configure the UART clock to 24MHz */
+    clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
+
+    cfg.type = BOARD_CONSOLE_TYPE;
+    cfg.base = (uint32_t) BOARD_CONSOLE_BASE;
+    cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
+    cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
+
+    init_uart_pins((UART_Type *) cfg.base);
+
+    console_init(&cfg);
+#else
+    while(1);
+#endif
+}
+
+void board_print_clock_freq(void)
+{
+    printf("==============================\n");
+    printf(" %s clock summary\n", BOARD_NAME);
+    printf("==============================\n");
+    printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
+    printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
+    printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0));
+    printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1));
+    printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2));
+    printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
+    printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
+    printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
+    printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
+    printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
+    printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram));
+    printf("display:\t %luHz\n", clock_get_frequency(clock_display));
+    printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0));
+    printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1));
+    printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg));
+    printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma));
+    printf("==============================\n");
+}
+
+void board_init_uart(UART_Type *ptr)
+{
+    init_uart_pins(ptr);
+}
+
+void board_init_ahb(void)
+{
+    clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/
+}
+
+void board_print_banner(void)
+{
+    const uint8_t banner[] = {"\n\
+----------------------------------------------------------------------\n\
+$$\\   $$\\ $$$$$$$\\  $$\\      $$\\ $$\\\n\
+$$ |  $$ |$$  __$$\\ $$$\\    $$$ |\\__|\n\
+$$ |  $$ |$$ |  $$ |$$$$\\  $$$$ |$$\\  $$$$$$$\\  $$$$$$\\   $$$$$$\\\n\
+$$$$$$$$ |$$$$$$$  |$$\\$$\\$$ $$ |$$ |$$  _____|$$  __$$\\ $$  __$$\\\n\
+$$  __$$ |$$  ____/ $$ \\$$$  $$ |$$ |$$ /      $$ |  \\__|$$ /  $$ |\n\
+$$ |  $$ |$$ |      $$ |\\$  /$$ |$$ |$$ |      $$ |      $$ |  $$ |\n\
+$$ |  $$ |$$ |      $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ |      \\$$$$$$  |\n\
+\\__|  \\__|\\__|      \\__|     \\__|\\__| \\_______|\\__|       \\______/\n\
+----------------------------------------------------------------------\n"};
+    printf("%s", banner);
+}
+
+static void board_turnoff_rgb_led(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18;
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19;
+    HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20;
+
+    HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl;
+}
+
+void board_init(void)
+{
+    board_turnoff_rgb_led();
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+    board_init_ahb();
+#if BOARD_SHOW_CLOCK
+    board_print_clock_freq();
+#endif
+#if BOARD_SHOW_BANNER
+    board_print_banner();
+#endif
+}
+
+void board_init_sdram_pins(void)
+{
+    init_sdram_pins();
+}
+
+uint32_t board_init_dram_clock(void)
+{
+    clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */
+    return clock_get_frequency(clock_dram);
+}
+
+void board_power_cycle_lcd(void)
+{
+    /* turn off backlight */
+    gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN);
+    gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0);
+
+    board_delay_ms(150);
+    /* power recycle */
+    gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN);
+    gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0);
+    board_delay_ms(20);
+    gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1);
+    board_delay_ms(150);
+
+    /* turn on backlight */
+    gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1);
+
+}
+
+void board_init_lcd(void)
+{
+    board_init_lcd_clock();
+    init_lcd_pins(BOARD_LCD_BASE);
+
+    board_power_cycle_lcd();
+
+    board_delay_ms(10);
+    board_power_cycle_lcd();
+}
+
+void board_delay_ms(uint32_t ms)
+{
+    clock_cpu_delay_ms(ms);
+}
+
+void board_timer_isr(void)
+{
+    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
+        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
+        timer_cb();
+    }
+}
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
+
+void board_timer_create(uint32_t ms, void *cb)
+{
+    uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    timer_cb = (board_timer_cb)cb;
+    gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
+
+    clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
+    gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
+
+    config.reload = gptmr_freq / 1000 * ms;
+    gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
+    gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
+    intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
+
+    gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
+}
+
+void board_i2c_bus_clear(I2C_Type *ptr)
+{
+    init_i2c_pins_as_gpio(ptr);
+    if (ptr == BOARD_CAP_I2C_BASE) {
+        gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN);
+        gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
+        if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) {
+            printf("CLK is low, please power cycle the board\n");
+            while (1) {}
+        }
+        if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) {
+            printf("SDA is low, try to issue I2C bus clear\n");
+        } else {
+            printf("I2C bus is ready\n");
+            return;
+        }
+
+        gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
+        for (uint8_t i = 0; i < 3; i++) {
+            for (uint32_t j = 0; j < 9; j++) {
+                gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1);
+                board_delay_ms(10);
+                gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0);
+                board_delay_ms(10);
+            }
+            board_delay_ms(100);
+        }
+        printf("I2C bus is cleared\n");
+    }
+}
+
+void board_init_i2c(I2C_Type *ptr)
+{
+    hpm_stat_t stat;
+    uint32_t freq;
+    i2c_config_t config;
+
+    board_i2c_bus_clear(ptr);
+
+    init_i2c_pins(ptr);
+    clock_add_to_group(clock_i2c0, 0);
+    clock_add_to_group(clock_i2c1, 0);
+    clock_add_to_group(clock_i2c2, 0);
+    clock_add_to_group(clock_i2c3, 0);
+    /* Configure the I2C clock to 24MHz */
+    clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U);
+
+    config.i2c_mode = i2c_mode_normal;
+    config.is_10bit_addressing = false;
+    freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME);
+    stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config);
+    if (stat != status_success) {
+        printf("failed to initialize i2c 0x%lx\n", BOARD_CAP_I2C_BASE);
+        while (1) {}
+    }
+}
+
+uint32_t board_init_uart_clock(UART_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_UART0) {
+        clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart0);
+    }
+    else if (ptr == HPM_UART1) {
+        clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart1);
+    }
+    else if (ptr == HPM_UART2) {
+        clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart2);
+    }
+ else if (ptr == HPM_UART3) {
+        clock_set_source_divider(clock_uart3, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart3);
+    }
+    else if (ptr == HPM_UART4) {
+        clock_set_source_divider(clock_uart4, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart4);
+    }
+    else if (ptr == HPM_UART5) {
+        clock_set_source_divider(clock_uart5, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart5);
+    }
+    else if (ptr == HPM_UART6) {
+        clock_set_source_divider(clock_uart6, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart6);
+    }
+    else if (ptr == HPM_UART7) {
+        clock_set_source_divider(clock_uart7, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart7);
+    }
+    else if (ptr == HPM_UART8) {
+        clock_set_source_divider(clock_uart8, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart8);
+    }
+    else if (ptr == HPM_UART9) {
+        clock_set_source_divider(clock_uart9, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart9);
+    }
+    else if (ptr == HPM_UART10) {
+        clock_set_source_divider(clock_uart10, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart10);
+    }
+    else if (ptr == HPM_UART11) {
+        clock_set_source_divider(clock_uart11, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart11);
+    }
+    else if (ptr == HPM_UART12) {
+        clock_set_source_divider(clock_uart12, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart12);
+    }
+    else if (ptr == HPM_UART13) {
+        clock_set_source_divider(clock_uart13, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart13);
+    }
+    else if (ptr == HPM_UART14) {
+        clock_set_source_divider(clock_uart14, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart14);
+    }
+    else if (ptr == HPM_UART15) {
+        clock_set_source_divider(clock_uart15, clk_src_osc24m, 1);
+        freq = clock_get_frequency(clock_uart15);
+    }
+    else {
+        /* Unsupported instance */
+    }
+
+    return freq;
+}
+
+
+uint32_t board_init_spi_clock(SPI_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_SPI0) {
+        /* SPI0 clock configure */
+        clock_add_to_group(clock_spi0, 0);
+        clock_set_source_divider(clock_spi0, clk_src_pll1_clk1, 5U);
+
+        freq = clock_get_frequency(clock_spi0);
+    }
+    else if (ptr == HPM_SPI1) {
+        /* SPI1 clock configure */
+        clock_add_to_group(clock_spi1, 0);
+        clock_set_source_divider(clock_spi1, clk_src_pll1_clk1, 5U);
+
+        freq = clock_get_frequency(clock_spi1);
+    }
+    else if (ptr == HPM_SPI2) {
+        /* SPI2 clock configure */
+        clock_add_to_group(clock_spi2, 0);
+        clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U);
+
+        freq = clock_get_frequency(clock_spi2);
+    }
+    else if (ptr == HPM_SPI3) {
+        /* SPI3 clock configure */
+        clock_add_to_group(clock_spi3, 0);
+        clock_set_source_divider(clock_spi3, clk_src_pll1_clk1, 5U);
+
+        freq = clock_get_frequency(clock_spi3);
+    }
+    else {
+        /* Invalid instance */
+    }
+    return freq;
+}
+
+void board_init_cap_touch(void)
+{
+    init_cap_pins();
+    gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
+    gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
+
+    board_delay_ms(1);
+    gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1);
+    board_delay_ms(10);
+    gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
+
+    gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
+    board_init_i2c(BOARD_CAP_I2C_BASE);
+}
+
+
+void board_init_gpio_pins(void)
+{
+    init_gpio_pins();
+}
+
+void board_init_spi_pins(SPI_Type *ptr)
+{
+    init_spi_pins(ptr);
+}
+
+void board_init_led_pins(void)
+{
+    init_led_pins_as_gpio();
+    gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+    gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+    gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void board_led_toggle(void)
+{
+    static uint8_t i;
+    gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN);
+    i++;
+    i = i % 3;
+}
+
+void board_led_write(bool state)
+{
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state ? BOARD_LED_ON_LEVEL : BOARD_LED_OFF_LEVEL);
+}
+
+void board_init_cam_pins(void)
+{
+    init_cam_pins(HPM_CAM0);
+}
+
+void board_init_usb_pins(void)
+{
+    /* set pull-up for USBx OC pins */
+    init_usb_pins(HPM_USB0);
+
+    /* configure USBx OC Flag pins as input function */
+    gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN);
+}
+
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
+{
+}
+
+void board_init_pmp(void)
+{
+    extern uint32_t __noncacheable_start__[];
+    extern uint32_t __noncacheable_end__[];
+
+    uint32_t start_addr = (uint32_t) __noncacheable_start__;
+    uint32_t end_addr = (uint32_t) __noncacheable_end__;
+    uint32_t length = end_addr - start_addr;
+
+    if (length == 0) {
+        return;
+    }
+
+    /* Ensure the address and the length are power of 2 aligned */
+    assert((length & (length - 1U)) == 0U);
+    assert((start_addr & (length - 1U)) == 0U);
+
+    pmp_entry_t pmp_entry[1];
+    pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
+    pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
+    pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
+    pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
+
+    pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry));
+}
+
+void board_init_clock(void)
+{
+    uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
+    hpm_core_clock = cpu0_freq;
+    if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
+        /* Configure the External OSC ramp-up time: ~9ms */
+        HPM_PLLCTL->XTAL = PLLCTL_XTAL_RAMP_TIME_SET(32UL * 1000UL * 9U);
+
+        /* Select clock setting preset1 */
+        sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
+    }
+
+    /* Add most Clocks to group 0 */
+    clock_add_to_group(clock_cpu0, 0);
+    clock_add_to_group(clock_mchtmr0, 0);
+    clock_add_to_group(clock_axi0, 0);
+    clock_add_to_group(clock_axi1, 0);
+    clock_add_to_group(clock_axi2, 0);
+    clock_add_to_group(clock_ahb, 0);
+    clock_add_to_group(clock_dram, 0);
+    clock_add_to_group(clock_xpi0, 0);
+    clock_add_to_group(clock_xpi1, 0);
+    clock_add_to_group(clock_gptmr0, 0);
+    clock_add_to_group(clock_gptmr1, 0);
+    clock_add_to_group(clock_gptmr2, 0);
+    clock_add_to_group(clock_gptmr3, 0);
+    clock_add_to_group(clock_gptmr4, 0);
+    clock_add_to_group(clock_gptmr5, 0);
+    clock_add_to_group(clock_gptmr6, 0);
+    clock_add_to_group(clock_gptmr7, 0);
+    clock_add_to_group(clock_uart0, 0);
+    clock_add_to_group(clock_uart1, 0);
+    clock_add_to_group(clock_uart2, 0);
+    clock_add_to_group(clock_uart3, 0);
+    clock_add_to_group(clock_uart6, 0);
+    clock_add_to_group(clock_uart13, 0);
+    clock_add_to_group(clock_uart14, 0);
+    clock_add_to_group(clock_i2c0, 0);
+    clock_add_to_group(clock_i2c1, 0);
+    clock_add_to_group(clock_i2c2, 0);
+    clock_add_to_group(clock_i2c3, 0);
+    clock_add_to_group(clock_spi0, 0);
+    clock_add_to_group(clock_spi1, 0);
+    clock_add_to_group(clock_spi2, 0);
+    clock_add_to_group(clock_spi3, 0);
+    clock_add_to_group(clock_can0, 0);
+    clock_add_to_group(clock_can1, 0);
+    clock_add_to_group(clock_can2, 0);
+    clock_add_to_group(clock_can3, 0);
+    clock_add_to_group(clock_display, 0);
+    clock_add_to_group(clock_sdxc0, 0);
+    clock_add_to_group(clock_sdxc1, 0);
+    clock_add_to_group(clock_camera0, 0);
+    clock_add_to_group(clock_camera1, 0);
+    clock_add_to_group(clock_ptpc, 0);
+    clock_add_to_group(clock_ref0, 0);
+    clock_add_to_group(clock_ref1, 0);
+    clock_add_to_group(clock_watchdog0, 0);
+    clock_add_to_group(clock_eth0, 0);
+    clock_add_to_group(clock_eth1, 0);
+    clock_add_to_group(clock_sdp, 0);
+    clock_add_to_group(clock_xdma, 0);
+    clock_add_to_group(clock_ram0, 0);
+    clock_add_to_group(clock_ram1, 0);
+    clock_add_to_group(clock_usb0, 0);
+    clock_add_to_group(clock_usb1, 0);
+    clock_add_to_group(clock_jpeg, 0);
+    clock_add_to_group(clock_pdma, 0);
+    clock_add_to_group(clock_kman, 0);
+    clock_add_to_group(clock_gpio, 0);
+    clock_add_to_group(clock_mbx0, 0);
+    clock_add_to_group(clock_hdma, 0);
+    clock_add_to_group(clock_rng, 0);
+    clock_add_to_group(clock_mot0, 0);
+    clock_add_to_group(clock_mot1, 0);
+    clock_add_to_group(clock_mot2, 0);
+    clock_add_to_group(clock_mot3, 0);
+    clock_add_to_group(clock_acmp, 0);
+    clock_add_to_group(clock_dao, 0);
+    clock_add_to_group(clock_msyn, 0);
+    clock_add_to_group(clock_lmm0, 0);
+    clock_add_to_group(clock_lmm1, 0);
+
+    clock_add_to_group(clock_adc0, 0);
+    clock_add_to_group(clock_adc1, 0);
+    clock_add_to_group(clock_adc2, 0);
+    clock_add_to_group(clock_adc3, 0);
+
+    clock_add_to_group(clock_i2s0, 0);
+    clock_add_to_group(clock_i2s1, 0);
+    clock_add_to_group(clock_i2s2, 0);
+    clock_add_to_group(clock_i2s3, 0);
+
+    /* Add the CPU1 clock to Group1 */
+    clock_add_to_group(clock_mchtmr1, 1);
+    clock_add_to_group(clock_mbx1, 1);
+
+    /* Connect Group0 to CPU0 */
+    clock_connect_group_to_cpu(0, 0);
+
+    if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
+        printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ);
+        while(1);
+    }
+
+    clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
+    clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
+    /* Connect Group1 to CPU1 */
+    clock_connect_group_to_cpu(1, 1);
+}
+
+uint32_t board_init_cam_clock(CAM_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_CAM0) {
+        /* Configure camera clock to 24MHz */
+        clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U);
+        freq = clock_get_frequency(clock_camera0);
+    } else if (ptr == HPM_CAM1) {
+        /* Configure camera clock to 24MHz */
+        clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U);
+        freq = clock_get_frequency(clock_camera1);
+    } else {
+        /* Invalid camera instance */
+    }
+    return freq;
+}
+
+uint32_t board_init_lcd_clock(void)
+{
+    uint32_t freq;
+    clock_add_to_group(clock_display, 0);
+    /* Configure LCDC clock to 29.7MHz */
+    clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U);
+    freq = clock_get_frequency(clock_display);
+    return freq;
+}
+
+uint32_t board_init_adc12_clock(ADC12_Type *ptr)
+{
+    uint32_t freq = 0;
+    switch ((uint32_t) ptr) {
+    case HPM_ADC0_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc0);
+        break;
+    case HPM_ADC1_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc1, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc1);
+        break;
+    case HPM_ADC2_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc2, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc2);
+        break;
+    default:
+        /* Invalid ADC instance */
+        break;
+    }
+
+    return freq;
+}
+
+uint32_t board_init_dao_clock(void)
+{
+    clock_add_to_group(clock_dao, 0);
+
+    sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+    sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk);
+
+    return clock_get_frequency(clock_dao);
+}
+
+uint32_t board_init_pdm_clock(void)
+{
+    clock_add_to_group(clock_pdm, 0);
+
+    sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+    sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
+
+    return clock_get_frequency(clock_pdm);
+}
+
+uint32_t board_init_i2s_clock(I2S_Type *ptr)
+{
+    if (ptr == HPM_I2S0) {
+        clock_add_to_group(clock_i2s0, 0);
+
+        sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
+        sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
+
+        return clock_get_frequency(clock_i2s0);
+    } else {
+        return 0;
+    }
+}
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_ADC3) {
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc3, clk_adc_src_ana1);
+        clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc3);
+    }
+
+    return freq;
+}
+
+void board_init_can(CAN_Type *ptr)
+{
+    init_can_pins(ptr);
+}
+
+uint32_t board_init_can_clock(CAN_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_CAN0) {
+        /* Set the CAN0 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can0);
+    } else if (ptr == HPM_CAN1) {
+        /* Set the CAN1 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can1);
+    } else if (ptr == HPM_CAN2) {
+        /* Set the CAN2 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can2);
+    } else if (ptr == HPM_CAN3) {
+        /* Set the CAN3 peripheral clock to 80MHz */
+        clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5);
+        freq = clock_get_frequency(clock_can3);
+    } else {
+        /* Invalid CAN instance */
+    }
+    return freq;
+}
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, 0);
+        clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr0);
+    }
+    else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, 0);
+        clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr1);
+    }
+    else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, 0);
+        clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr2);
+    }
+    else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, 0);
+        clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr3);
+    }
+    else if (ptr == HPM_GPTMR4) {
+        clock_add_to_group(clock_gptmr4, 0);
+        clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr4);
+    }
+    else if (ptr == HPM_GPTMR5) {
+        clock_add_to_group(clock_gptmr5, 0);
+        clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr5);
+    }
+    else if (ptr == HPM_GPTMR6) {
+        clock_add_to_group(clock_gptmr6, 0);
+        clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr6);
+    }
+    else if (ptr == HPM_GPTMR7) {
+        clock_add_to_group(clock_gptmr7, 0);
+        clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr7);
+    }
+    else {
+        /* Invalid instance */
+    }
+}
+
+/*
+ * this function will be called during startup to initialize external memory for data use
+ */
+void _init_ext_ram(void)
+{
+    uint32_t dram_clk_in_hz;
+    board_init_sdram_pins();
+    dram_clk_in_hz = board_init_dram_clock();
+
+    dram_config_t config = {0};
+    dram_sdram_config_t sdram_config = {0};
+
+    dram_default_config(HPM_DRAM, &config);
+    config.dqs = DRAM_DQS_INTERNAL;
+    dram_init(HPM_DRAM, &config);
+
+    sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4;
+    sdram_config.prescaler = 0x3;
+    sdram_config.burst_len_in_byte = 8;
+    sdram_config.auto_refresh_count_in_one_burst = 1;
+    sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS;
+    sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3;
+
+    sdram_config.precharge_to_act_in_ns = 18;   /* Trp */
+    sdram_config.act_to_rw_in_ns = 18;          /* Trcd */
+    sdram_config.refresh_recover_in_ns = 70;     /* Trfc/Trc */
+    sdram_config.write_recover_in_ns = 12;      /* Twr/Tdpl */
+    sdram_config.cke_off_in_ns = 42;             /* Trcd */
+    sdram_config.act_to_precharge_in_ns = 42;   /* Tras */
+
+    sdram_config.self_refresh_recover_in_ns = 66;   /* Txsr */
+    sdram_config.refresh_to_refresh_in_ns = 66;     /* Trfc/Trc */
+    sdram_config.act_to_act_in_ns = 12;             /* Trrd */
+    sdram_config.idle_timeout_in_ns = 6;
+    sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED;
+
+    sdram_config.cs = BOARD_SDRAM_CS;
+    sdram_config.base_address = BOARD_SDRAM_ADDRESS;
+    sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
+    sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
+    sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
+    sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
+    sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
+    sdram_config.delay_cell_value = 29;
+
+    dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config);
+}
+
+void board_init_sd_pins(SDXC_Type *ptr)
+{
+    if (ptr == HPM_SDXC1) {
+        init_sdxc_pins(ptr, false);
+    } else {
+        while (1) {
+
+        }
+    }
+}
+
+uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
+{
+    uint32_t actual_freq = 0;
+    do {
+        if (ptr != HPM_SDXC1) {
+            break;
+        }
+        clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
+        sdxc_enable_inverse_clock(ptr, false);
+        sdxc_enable_sd_clock(ptr, false);
+        /* Configure the clock below 400KHz for the identification state */
+        if (freq <= 400000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63);
+        }
+            /* configure the clock to 24MHz for the SDR12/Default speed */
+        else if (freq <= 25000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
+        }
+            /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
+        else if (freq <= 50000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8);
+        }
+            /* Configure the clock to 100MHz for the SDR50 */
+        else if (freq <= 100000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
+        }
+            /* Configure the clock to 166MHz for SDR104/HS200/HS400  */
+        else if (freq <= 208000000UL) {
+            clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
+        }
+            /* For other unsupported clock ranges, configure the clock to 24MHz */
+        else {
+            clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
+        }
+        sdxc_enable_inverse_clock(ptr, true);
+        sdxc_enable_sd_clock(ptr, true);
+        actual_freq = clock_get_frequency(sdxc_clk);
+    } while (false);
+
+    return actual_freq;
+}
+
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
+{
+    if (internal == false) {
+        return status_success;
+    }
+
+    /* Configure Enet clock to output reference clock */
+    if (ptr == HPM_ENET0) {
+        /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */
+        clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5);
+    } else if (ptr == HPM_ENET1) {
+        /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */
+        clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */
+    } else {
+        return status_invalid_argument;
+    }
+    return status_success;
+}
+
+void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
+{
+    sdxc_switch_to_1v8_signal(ptr, true);
+    init_sdxc_pins(ptr, true);
+}
+
+bool board_sd_detect_card(SDXC_Type *ptr)
+{
+    return sdxc_is_card_inserted(ptr);
+}
+
+void board_init_rgb_pwm_pins(void)
+{
+    init_led_pins_as_pwm();
+}
+
+void board_init_beep_pwm_pins(void)
+{
+    init_beep_pwm_pins();
+}
+
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
+{
+    init_enet_pins(ptr);
+
+    if (ptr == HPM_ENET1) {
+        gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+void board_reset_enet_phy(ENET_Type *ptr)
+{
+    gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0);
+    board_delay_ms(BOARD_ENET1_PHY_RST_TIME);
+    gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1);
+}

bsp/hpmicro/hpm6750evkmini/board/board.h

@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _HPM_BOARD_H
+#define _HPM_BOARD_H
+#include <stdio.h>
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_soc_feature.h"
+#include "hpm_clock_drv.h"
+#include "hpm_enet_drv.h"
+#include "pinmux.h"
+
+#define BOARD_NAME "hpm6750evkmini"
+
+/* uart section */
+#ifndef BOARD_RUNNING_CORE
+#define BOARD_RUNNING_CORE HPM_CORE0
+#endif
+#ifndef BOARD_APP_UART_BASE
+#define BOARD_APP_UART_BASE HPM_UART0
+#define BOARD_APP_UART_IRQ  IRQn_UART0
+#else
+#ifndef BOARD_APP_UART_IRQ
+#warning no IRQ specified for applicaiton uart
+#endif
+#endif
+
+#define BOARD_APP_UART_BAUDRATE (115200UL)
+#define BOARD_APP_UART_CLK_NAME clock_uart0
+
+#ifndef BOARD_CONSOLE_TYPE
+#define BOARD_CONSOLE_TYPE console_type_uart
+#endif
+
+#if BOARD_CONSOLE_TYPE == console_type_uart
+#define BOARD_CONSOLE_BASE HPM_UART0
+#define BOARD_CONSOLE_CLK_NAME clock_uart0
+#define BOARD_CONSOLE_BAUDRATE (115200UL)
+#endif
+
+#define BOARD_FREEMASTER_UART_BASE HPM_UART0
+#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0
+#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0
+
+/* sdram section */
+#define BOARD_SDRAM_ADDRESS  (0x40000000UL)
+#define BOARD_SDRAM_SIZE     (16*SIZE_1MB)
+#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS
+#define BOARD_SDRAM_REFRESH_COUNT (4096UL)
+#define BOARD_SDRAM_REFRESH_IN_MS (64UL)
+#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL)
+
+/* lcd section */
+#define BOARD_LCD_BASE HPM_LCDC
+#define BOARD_LCD_IRQ  IRQn_LCDC_D0
+#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0
+#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB
+#define BOARD_LCD_POWER_GPIO_PIN 12
+#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0
+#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB
+#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23
+
+/* i2c section */
+#define BOARD_APP_I2C_BASE HPM_I2C0
+#define BOARD_APP_I2C_IRQ IRQn_I2C0
+#define BOARD_APP_I2C_CLK_NAME clock_i2c0
+
+#define BOARD_APP_I2C_SLAVE_BASE HPM_I2C3
+#define BOARD_APP_I2C_SLAVE_IRQ IRQn_I2C3
+#define BOARD_APP_I2C_SLAVE_CLK_NAME clock_i2c3
+
+#define BOARD_CAM_I2C_BASE HPM_I2C0
+#define BOARD_CAM_I2C_CLK_NAME clock_i2c0
+
+#define BOARD_CAP_I2C_BASE (HPM_I2C0)
+#define BOARD_CAP_I2C_CLK_NAME clock_i2c0
+#define BOARD_CAP_RST_GPIO (HPM_GPIO0)
+#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_RST_GPIO_PIN (9)
+#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B)
+#define BOARD_CAP_INTR_GPIO (HPM_GPIO0)
+#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_INTR_GPIO_PIN (8)
+#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B)
+#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_I2C_SDA_GPIO_PIN (10)
+#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOB)
+#define BOARD_CAP_I2C_CLK_GPIO_PIN (11)
+
+/* dma section */
+#define BOARD_APP_XDMA_IRQ IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ IRQn_HDMA
+
+/* gpio section */
+#define BOARD_R_GPIO_CTRL HPM_GPIO0
+#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_R_GPIO_PIN 19
+#define BOARD_G_GPIO_CTRL HPM_GPIO0
+#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_G_GPIO_PIN 18
+#define BOARD_B_GPIO_CTRL HPM_GPIO0
+#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_B_GPIO_PIN 20
+
+#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL
+#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX
+#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN
+
+#define BOARD_LED_OFF_LEVEL 1
+#define BOARD_LED_ON_LEVEL 0
+
+#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ
+#define BOARD_APP_GPIO_PIN 2
+
+/* pinmux section */
+#define USING_GPIO0_FOR_GPIOZ
+#ifndef USING_GPIO0_FOR_GPIOZ
+#define BOARD_APP_GPIO_CTRL HPM_BGPIO
+#define BOARD_APP_GPIO_IRQ IRQn_BGPIO
+#else
+#define BOARD_APP_GPIO_CTRL HPM_GPIO0
+#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z
+#endif
+
+/* gpiom section */
+#define BOARD_APP_GPIOM_BASE            HPM_GPIOM
+#define BOARD_APP_GPIOM_USING_CTRL      HPM_FGPIO
+#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
+
+/* spi section */
+#define BOARD_APP_SPI_BASE HPM_SPI2
+#define BOARD_APP_SPI_CLK_SRC_FREQ      (24000000UL)
+#define BOARD_APP_SPI_SCLK_FREQ         (1562500UL)
+#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
+#define BOARD_APP_SPI_DATA_LEN_IN_BITS  (8U)
+
+/* Flash section */
+#define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
+#define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90001U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000007U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00000000U)
+
+/* lcd section */
+#ifndef BOARD_LCD_WIDTH
+#define BOARD_LCD_WIDTH (800)
+#endif
+#ifndef BOARD_LCD_HEIGHT
+#define BOARD_LCD_HEIGHT (480)
+#endif
+
+/* pdma section */
+#define BOARD_PDMA_BASE HPM_PDMA
+
+/* enet section */
+#define BOARD_ENET1_RST_GPIO        HPM_GPIO0
+#define BOARD_ENET1_RST_GPIO_INDEX  GPIO_DO_GPIOD
+#define BOARD_ENET1_RST_GPIO_PIN    (15U)
+#define BOARD_ENET1_INF             enet_inf_rmii
+#define BOARD_ENET1_INT_REF_CLK     (0U)
+#define BOARD_ENET1_PHY_RST_TIME    (30)
+#define BOARD_ENET1_PTP_CLOCK       (clock_ptp1)
+/* adc section */
+#define BOARD_APP_ADC12_BASE HPM_ADC0
+#define BOARD_APP_ADC16_BASE HPM_ADC3
+#define BOARD_APP_ADC12_IRQn IRQn_ADC0
+#define BOARD_APP_ADC16_IRQn IRQn_ADC3
+#define BOARD_APP_ADC_CH                         (0U)
+#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES     (1024U)
+#define BOARD_APP_ADC_PREEMPT_DMA_SIZE_IN_4BYTES (192U)
+#define BOARD_APP_ADC_PREEMPT_TRIG_LEN           (1U)
+#define BOARD_APP_ADC_SINGLE_CONV_CNT            (6)
+#define BOARD_APP_ADC_TRIG_PWMT0                 HPM_PWM0
+#define BOARD_APP_ADC_TRIG_PWMT1                 HPM_PWM1
+#define BOARD_APP_ADC_TRIG_TRGM0                 HPM_TRGM0
+#define BOARD_APP_ADC_TRIG_TRGM1                 HPM_TRGM1
+#define BOARD_APP_ADC_TRIG_PWM_SYNC              HPM_SYNT
+
+/*
+ * timer for board delay
+ */
+#define BOARD_DELAY_TIMER (HPM_GPTMR0)
+#define BOARD_DELAY_TIMER_CH 0
+#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr0)
+
+#define BOARD_CALLBACK_TIMER (HPM_GPTMR0)
+#define BOARD_CALLBACK_TIMER_CH 1
+#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0
+#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0)
+
+/* SDXC section */
+#define BOARD_APP_SDCARD_SDXC_BASE            (HPM_SDXC1)
+#define BOARD_APP_SDCARD_SUPPORT_1V8          (0)
+
+/* USB section */
+#define BOARD_USB0_VBUS_PORT       (HPM_GPIO0)
+#define BOARD_USB0_VBUS_GPIO_INDEX (GPIO_DO_GPIOF)
+#define BOARD_USB0_VBUS_GPIO_PIN   (9)
+
+#define BOARD_USB0_OC_PORT         (HPM_GPIO0)
+#define BOARD_USB0_OC_GPIO_INDEX   (GPIO_DI_GPIOF)
+#define BOARD_USB0_OC_GPIO_PIN     (8)
+
+/* APP PWM */
+#define BOARD_APP_PWM HPM_PWM0
+#define BOARD_APP_PWM_CLOCK_NAME clock_mot0
+#define BOARD_APP_PWM_OUT1 4
+#define BOARD_APP_PWM_OUT2 5
+#define BOARD_APP_TRGM HPM_TRGM0
+
+/* RGB LED Section */
+#define BOARD_RED_PWM_IRQ IRQn_PWM1
+#define BOARD_RED_PWM HPM_PWM1
+#define BOARD_RED_PWM_OUT 0
+#define BOARD_RED_PWM_CMP 0
+#define BOARD_RED_PWM_CMP_INITIAL_ZERO true
+#define BOARD_RED_PWM_CLOCK_NAME clock_mot1
+
+#define BOARD_GREEN_PWM_IRQ IRQn_PWM1
+#define BOARD_GREEN_PWM HPM_PWM1
+#define BOARD_GREEN_PWM_OUT 1
+#define BOARD_GREEN_PWM_CMP 1
+#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true
+#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1
+
+#define BOARD_BLUE_PWM_IRQ IRQn_PWM0
+#define BOARD_BLUE_PWM HPM_PWM0
+#define BOARD_BLUE_PWM_OUT 7
+#define BOARD_BLUE_PWM_CMP 0
+#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true
+#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0
+
+
+/* Beep Section */
+#define BOARD_BEEP_PWM HPM_PWM3
+#define BOARD_BEEP_PWM_OUT 4
+#define BOARD_BEEP_PWM_CLOCK_NAME clock_mot3
+
+#define BOARD_CPU_FREQ (816000000UL)
+
+#ifndef BOARD_SHOW_CLOCK
+#define BOARD_SHOW_CLOCK 1
+#endif
+#ifndef BOARD_SHOW_BANNER
+#define BOARD_SHOW_BANNER 1
+#endif
+
+#ifndef BOARD_RUNNING_CORE
+#define BOARD_RUNNING_CORE 0
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void (*board_timer_cb)(void);
+
+void board_init(void);
+void board_init_console(void);
+
+void board_init_uart(UART_Type *ptr);
+void board_init_i2c(I2C_Type *ptr);
+void board_init_lcd(void);
+
+void board_init_can(CAN_Type *ptr);
+
+uint32_t board_init_dram_clock(void);
+
+void board_init_sdram_pins(void);
+void board_init_gpio_pins(void);
+void board_init_spi_pins(SPI_Type *ptr);
+void board_init_led_pins(void);
+
+/* cap touch */
+void board_init_cap_touch(void);
+
+void board_led_write(bool state);
+void board_led_toggle(void);
+
+void board_fpga_power_enable(void);
+
+void board_init_cam_pins(void);
+
+/* Initialize SoC overall clocks */
+void board_init_clock(void);
+
+/* Initialize the CAM(camera) dot clock */
+uint32_t board_init_cam_clock(CAM_Type *ptr);
+
+/* Initialize the LCD pixel clock */
+uint32_t board_init_lcd_clock(void);
+
+uint32_t board_init_uart_clock(UART_Type *ptr);
+
+uint32_t board_init_spi_clock(SPI_Type *ptr);
+
+uint32_t board_init_adc12_clock(ADC12_Type *ptr);
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr);
+
+uint32_t board_init_can_clock(CAN_Type *ptr);
+
+uint32_t board_init_i2s_clock(I2S_Type *ptr);
+uint32_t board_init_pdm_clock(void);
+uint32_t board_init_dao_clock(void);
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
+
+void board_init_sd_pins(SDXC_Type *ptr);
+uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
+void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
+bool board_sd_detect_card(SDXC_Type *ptr);
+
+void board_init_usb_pins(void);
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
+
+/*
+ * @brief Initialize PMP and PMA for but not limited to the following purposes:
+ *      -- non-cacheable memory initialization
+ */
+void board_init_pmp(void);
+
+void board_delay_ms(uint32_t ms);
+
+void board_init_beep_pwm_pins(void);
+void board_init_rgb_pwm_pins(void);
+
+void board_timer_create(uint32_t ms, void *cb);
+
+/* Initialize enet pins */
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
+
+/* Initialize enet reference clock in RMII mode */
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
+
+/* Reset an enet PHY */
+void board_reset_enet_phy(ENET_Type *ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _HPM_BOARD_H */

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg

@@ -0,0 +1,299 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# openocd flash driver argument:
+#   - ARG7:
+#       [31:28] Flash probe type
+#         0 - SFDP SDR / 1 - SFDP DDR
+#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+#         6 - OctaBus DDR (SPI -> OPI DDR)
+#         8 - Xccela DDR (SPI -> OPI DDR)
+#         10 - EcoXiP DDR (SPI -> OPI DDR)
+#       [27:24] Command Pads after Power-on Reset
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [23:20] Command Pads after Configuring FLASH
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+#         0 - Not needed
+#         1 - QE bit is at bit 6 in Status Register 1
+#         2 - QE bit is at bit1 in Status Register 2
+#         3 - QE bit is at bit7 in Status Register 2
+#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+#       [15:8] Dummy cycles
+#         0 - Auto-probed / detected / default value
+#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+#       [7:4] Misc.
+#         0 - Not used
+#         1 - SPI mode
+#         2 - Internal loopback
+#         3 - External DQS
+#       [3:0] Frequency option
+#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+#   - ARG8:
+#       [31:20]  Reserved
+#       [19:16] IO voltage
+#         0 - 3V / 1 - 1.8V
+#       [15:12] Pin group
+#         0 - 1st group / 1 - 2nd group
+#       [11:8] Connection selection
+#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+#       [7:0] Drive Strength
+#         0 - Default value
+
+# xpi0 configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3040000
+#   - base address:     0x80000000
+#   - flash size:       0x1000000
+#   - flash option0:    0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+    echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure dram frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+    #$::_TARGET0 riscv dmi_write 0x39 0xF4001820
+    $::_TARGET0 riscv dmi_write 0x3C 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+    $::_TARGET0 riscv dmi_write 0x39 0xF4001820
+    $::_TARGET0 riscv dmi_write 0x3C 0x401
+
+    # PD13
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040368
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD12
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040360
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD10
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040350
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD09
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040348
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD08
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040340
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD07
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040338
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD06
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040330
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD05
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040328
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD04
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040320
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD03
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040318
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD02
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040310
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD01
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040308
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PD00
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040300
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC29
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402E8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC28
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402E0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC27
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402D8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # PC22
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402B0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC21
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402A8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC17
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040288
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC15
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040278
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC12
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040260
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC11
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040258
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC10
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040250
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC09
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040248
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC08
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040240
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC07
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040238
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC06
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040230
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC05
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040228
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC04
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040220
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # PC14
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040270
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC13
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040268
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC16
+    # $::_TARGET0 riscv dmi_write 0x39 0xF4040280
+    $::_TARGET0 riscv dmi_write 0x3C 0x1000C
+    # PC26
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402D0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC25
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402C8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC19
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040298
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC18
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040290
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC23
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402B8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC24
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402C0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC30
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402F0
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC31
+    $::_TARGET0 riscv dmi_write 0x39 0xF40402F8
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC02
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040210
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+    # PC03
+    $::_TARGET0 riscv dmi_write 0x39 0xF4040218
+    $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+    # dramc configuration
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+    sleep 10
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050008
+    $::_TARGET0 riscv dmi_write 0x3C 0x30524
+    $::_TARGET0 riscv dmi_write 0x39 0xF305000C
+    $::_TARGET0 riscv dmi_write 0x3C 0x6030524
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+    $::_TARGET0 riscv dmi_write 0x3C 0x10000000
+
+    # 16MB
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050010
+    $::_TARGET0 riscv dmi_write 0x3C 0x40000019
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050014
+    $::_TARGET0 riscv dmi_write 0x3C 0
+    # 16-bit
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050040
+    $::_TARGET0 riscv dmi_write 0x3C 0xf31
+
+    # 133Mhz configuration
+    #$::_TARGET0 riscv dmi_write 0x39 0xF3050044
+    $::_TARGET0 riscv dmi_write 0x3C 0x884e22
+    # 166Mhz configuration
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050044
+    $::_TARGET0 riscv dmi_write 0x3C 0x884e33
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+    $::_TARGET0 riscv dmi_write 0x3C 0x2020300
+
+    # config delay cell
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+    $::_TARGET0 riscv dmi_write 0x3C 0x3b
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+    $::_TARGET0 riscv dmi_write 0x3C 0x203b
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050094
+    $::_TARGET0 riscv dmi_write 0x3C 0
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050098
+    $::_TARGET0 riscv dmi_write 0x3C 0
+
+    # precharge all
+    $::_TARGET0 riscv dmi_write 0x39 0xF3050090
+    $::_TARGET0 riscv dmi_write 0x3C 0x40000000
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+    # auto refresh
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+    # set mode
+    $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
+    $::_TARGET0 riscv dmi_write 0x3C 0x33
+    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
+    sleep 500
+    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+    $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+    $::_TARGET0 riscv dmi_write 0x3C 0x2020301
+    echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+    init_clock
+    init_sdram
+}
+
+$_TARGET0 configure -event gdb-attach {
+    reset halt
+}

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg

@@ -0,0 +1,15 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
+

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6014
+
+ftdi_layout_init 0x0018 0x001b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/jlink.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+reset_config srst_only
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x010b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg

@@ -0,0 +1 @@
+riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg

@@ -0,0 +1,38 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+
+proc release_core1 {} {
+    # set start point for core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C08
+    $::_TARGET0 riscv dmi_write 0x3C 0x20016284
+
+    # set boot flag for core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C
+    $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9
+
+    # release core1
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002C00
+    $::_TARGET0 riscv dmi_write 0x3C 0x1000
+}
+
+$_TARGET1 configure -event reset-deassert-pre release_core1
+$_TARGET1 configure -event examine-start release_core1
+$_TARGET1 configure -event examine-end {
+    $::_TARGET1 arp_examine
+}
+
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0

bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg

@@ -0,0 +1,13 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0

bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-01-11   hpmicro     First version
+ */
+
+#include "rtthread.h"
+
+#ifdef RT_USING_PHY
+#include <rtdevice.h>
+#include <rtdbg.h>
+#include "hpm_enet_drv.h"
+#include "eth_phy_port.h"
+#include "hpm_soc.h"
+#include "netif/ethernetif.h"
+#include "board.h"
+
+typedef struct
+{
+    char *mdio_name;
+    ENET_Type *instance;
+    struct eth_device *eth_dev;
+    phy_device_t *phy_dev;
+    struct rt_mdio_bus *mdio_bus;
+} eth_phy_handle_t;
+
+typedef struct
+{
+    uint8_t phy_handle_cnt;
+    eth_phy_handle_t **phy_handle;
+} eth_phy_monitor_handle_t;
+
+#ifdef BSP_USING_ETH0
+extern struct eth_device eth0_dev;
+static struct rt_mdio_bus mdio0_bus;
+static phy_device_t phy0_dev;
+static uint8_t phy0_reg_list[]= {PHY0_REG_LIST};
+
+static eth_phy_handle_t eth0_phy_handle =
+{
+    .instance  = HPM_ENET0,
+    .eth_dev   = &eth0_dev,
+    .phy_dev   = &phy0_dev,
+    .mdio_name = "MDIO0",
+    .mdio_bus  = &mdio0_bus,
+};
+#endif
+
+#ifdef BSP_USING_ETH1
+extern struct eth_device eth1_dev;
+static struct rt_mdio_bus mdio1_bus;
+static phy_device_t phy1_dev;
+static uint8_t phy1_reg_list[]= {PHY1_REG_LIST};
+
+static eth_phy_handle_t eth1_phy_handle =
+{
+    .instance     = HPM_ENET1,
+    .eth_dev      = &eth1_dev,
+    .phy_dev      = &phy1_dev,
+    .mdio_name    = "MDIO1",
+    .mdio_bus     = &mdio1_bus,
+};
+#endif
+
+static eth_phy_handle_t *s_gphys[] =
+{
+#ifdef BSP_USING_ETH0
+&eth0_phy_handle,
+#endif
+
+#ifdef BSP_USING_ETH1
+&eth1_phy_handle
+#endif
+};
+
+static uint8_t *s_gphy_reg_list[] =
+{
+#ifdef BSP_USING_ETH0
+phy0_reg_list,
+#endif
+
+#ifdef BSP_USING_ETH1
+phy1_reg_list,
+#endif
+};
+
+eth_phy_monitor_handle_t phy_monitor_handle =
+{
+    .phy_handle_cnt = ARRAY_SIZE(s_gphys),
+    .phy_handle     = s_gphys
+};
+
+static struct rt_phy_ops phy_ops;
+
+static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
+{
+    return PHY_STATUS_OK;
+}
+
+static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg);
+
+    return size;
+}
+
+static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg,  *(uint16_t *)data);
+
+    return size;
+}
+
+static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]);
+
+    #if PHY_AUTO_NEGO
+        reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+
+    #else
+        reg_status &= PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+    #endif
+
+    return PHY_STATUS_OK;
+}
+
+static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]);
+
+    *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M;
+    *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX;
+
+    return PHY_STATUS_OK;
+}
+
+static void phy_poll_status(void *parameter)
+{
+    int ret;
+    phy_info_t phy_info;
+    rt_uint32_t status;
+    rt_device_t dev;
+    rt_phy_msg_t msg;
+    rt_uint32_t speed, duplex;
+    phy_device_t *phy_dev;
+    struct eth_device* eth_dev;
+    char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"};
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev;
+        phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev;
+
+        phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status);
+
+        if (status)
+        {
+            phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex);
+
+            ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            if (ret != 0)
+            {
+                memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            }
+        }
+
+        if (phy_dev->phy_link != status)
+        {
+            phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN;
+            eth_device_linkchange(eth_dev, status);
+            LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n");
+            if (status == PHY_LINK_UP)
+            {
+                LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]);
+                LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex");
+            }
+        }
+    }
+}
+
+static void phy_detection(void *parameter)
+{
+    uint8_t detected_count = 0;
+    struct rt_phy_msg msg = {0, 0};
+    phy_device_t *phy_dev = (phy_device_t *)parameter;
+    rt_uint32_t i;
+
+    msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX];
+    phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ);
+
+    while(phy_dev->phy.addr == 0xffff)
+    {
+        /* Search a PHY */
+        for (i = 0; i <= 0x1f; i++)
+        {
+            ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i;
+            phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1);
+
+            if (msg.value == PHY_ID1)
+            {
+                phy_dev->phy.addr = i;
+                LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr);
+                return;
+            }
+        }
+
+        phy_dev->phy.addr = 0xffff;
+        detected_count++;
+        rt_thread_mdelay(1000);
+
+        if (detected_count > 3)
+        {
+            LOG_E("No any PHY device is detected! Please check your hardware!\n");
+            return;
+        }
+    }
+}
+
+static void phy_monitor_thread_entry(void *args)
+{
+    rt_timer_t phy_status_timer;
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        LOG_D("Detect a PHY%d\n", i);
+        phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev);
+    }
+
+    phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER);
+
+    if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK)
+    {
+        LOG_E("Failed to start link change detection timer\n");
+    }
+}
+
+int phy_device_register(void)
+{
+    rt_err_t err = RT_ERROR;
+    rt_thread_t thread_phy_monitor;
+
+    /* Set ops for PHY */
+    phy_ops.init = phy_init;
+    phy_ops.get_link_status = phy_get_link_status;
+    phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex;
+
+    for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++)
+    {
+        /* Set PHY address */
+        s_gphys[i]->phy_dev->phy.addr = 0xffff;
+
+        /* Set MIDO bus */
+        s_gphys[i]->mdio_bus->hw_obj     = s_gphys[i]->instance;
+        s_gphys[i]->mdio_bus->name       = s_gphys[i]->mdio_name;
+        s_gphys[i]->mdio_bus->ops->read  = phy_read;
+        s_gphys[i]->mdio_bus->ops->write = phy_write;
+        s_gphys[i]->phy_dev->phy.bus     = s_gphys[i]->mdio_bus;
+        s_gphys[i]->phy_dev->phy.ops     = &phy_ops;
+
+        /* Set PHY register list */
+        s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i];
+
+        rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME);
+    }
+
+    /* Start PHY monitor */
+    thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2);
+
+    if (thread_phy_monitor != RT_NULL)
+    {
+        rt_thread_startup(thread_phy_monitor);
+    }
+    else
+    {
+        err = RT_ERROR;
+    }
+
+    return err;
+}
+INIT_PREV_EXPORT(phy_device_register);
+#endif /* RT_USING_PHY */

bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef ETH_PHY_PORT_H
+#define ETH_PHY_PORT_H
+
+#include "hpm_ioc_regs.h"
+#include <rtdevice.h>
+
+#ifndef PHY_AUTO_NEGO
+#define PHY_AUTO_NEGO  (1U)
+#endif
+
+#ifndef PHY_MDIO_CSR_CLK_FREQ
+#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
+#endif
+
+enum phy_link_status
+{
+   PHY_LINK_DOWN = 0U,
+   PHY_LINK_UP
+};
+
+typedef struct {
+    rt_uint32_t phy_speed;
+    rt_uint32_t phy_duplex;
+} phy_info_t;
+
+typedef struct {
+    rt_uint32_t phy_link;
+    rt_phy_t phy;
+    phy_info_t phy_info;
+} phy_device_t;
+
+/** @note PHY: LAN8720A */
+
+#define PHY_NAME    ("LAN8720A")
+#define PHY_ID1     (7U)
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG       (0x00U)
+#define PHY_RESET_MASK              (1U << 15)
+#define PHY_AUTO_NEGOTIATION_MASK   (1U << 12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG        (0x01U)
+#define PHY_LINKED_STATUS_MASK      (1U << 2)
+#define PHY_AUTONEGO_COMPLETE_MASK  (1U << 5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG                 (0x02U)
+
+/* The PHY ID two register */
+#define PHY_ID2_REG                 (0x03U)
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG   (0x04U)
+
+/* The PHY SPECIAL MODES REGISTER */
+#define PHY_SPECIAL_MODES_REG       (0x12U)
+
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      (0x1dU)
+
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      (0x1eU)
+#define PHY_LINK_DOWN_MASK          (1 << 4)
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1 << 6)
+
+/*  The PHY status register. */
+#define PHY_STATUS_REG              (0x1fU)
+#define PHY_10M_MASK                (1 << 2)
+#define PHY_100M_MASK               (1 << 3)
+#define PHY_FULL_DUPLEX_MASK        (1 << 4)
+#define PHY_STATUS_SPEED_10M(SR)    ((SR) & PHY_10M_MASK)
+#define PHY_STATUS_SPEED_100M(SR)   ((SR) & PHY_100M_MASK)
+#define PHY_STATUS_FULL_DUPLEX(SR)  ((SR) & PHY_FULL_DUPLEX_MASK)
+
+/* PHY0 register list */
+#define PHY0_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                       PHY_BASIC_STATUS_REG,\
+                       PHY_ID1_REG,\
+                       PHY_ID2_REG,\
+                       PHY_SPECIAL_MODES_REG,\
+                       PHY_INTERRUPT_FLAG_REG,\
+                       PHY_INTERRUPT_MASK_REG,\
+                       PHY_STATUS_REG
+
+/* PHY0 register index */
+#define PHY0_BASIC_STATUS_REG_IDX (1U)
+#define PHY0_ID1_REG_IDX          (2U)
+#define PHY0_STATUS_REG_IDX       (7U)
+
+/* PHY1 register list */
+#define PHY1_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                       PHY_BASIC_STATUS_REG,\
+                       PHY_ID1_REG,\
+                       PHY_ID2_REG,\
+                       PHY_SPECIAL_MODES_REG,\
+                       PHY_INTERRUPT_FLAG_REG,\
+                       PHY_INTERRUPT_MASK_REG,\
+                       PHY_STATUS_REG
+
+/* PHY1 register index */
+#define PHY_BASIC_STATUS_REG_IDX (1U)
+#define PHY_ID1_REG_IDX          (2U)
+#define PHY_STATUS_REG_IDX       (7U)
+
+#endif

bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev stm32f2_onchip_flash;
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 1*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* PKG_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */

bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c

@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-03-09   hpmicro     First implementation
+ * 2022-08-01   hpmicro     Fixed random crashing during kvdb_init
+ * 2022-08-03   hpmicro     Improved erase speed
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_FAL
+#include "fal.h"
+#include "hpm_romapi.h"
+#include "board.h"
+#include "hpm_l1c_drv.h"
+
+#if defined(FLASH_XIP) && (FLASH_XIP == 1)
+
+#define FAL_ENTER_CRITICAL() do {\
+        rt_enter_critical();\
+        disable_irq_from_intc();\
+        fencei();\
+    }while(0)
+
+#define FAL_EXIT_CRITICAL() do {\
+        ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
+        fencei();\
+        rt_exit_critical();\
+        enable_irq_from_intc();\
+    }while(0)
+
+#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
+
+#else
+#define FAL_ENTER_CRITICAL()
+
+#define FAL_EXIT_CRITICAL()
+
+#define FAL_RAMFUNC
+
+#endif
+
+/***************************************************************************************************
+ *      FAL Porting Guide
+ *
+ *      1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
+ *         must be placed at RAM or ROM code
+ *      2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
+ *         interrupt related codes to RAM
+ *
+ ***************************************************************************************************/
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static xpi_nor_config_t s_flashcfg;
+
+/**
+ * @brief FAL Flash device context
+ */
+struct fal_flash_dev nor_flash0 =
+    {
+            .name = NOR_FLASH_DEV_NAME,
+            /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
+            .addr = NOR_FLASH_MEM_BASE,
+            .len = 8 * 1024 * 1024,
+            .blk_size = 4096,
+            .ops = { .init = init, .read = read, .write = write, .erase = erase },
+            .write_gran = 1
+    };
+
+/**
+ * @brief FAL initialization
+ *        This function probes the FLASH using the ROM API
+ */
+FAL_RAMFUNC static int init(void)
+{
+    int ret = RT_EOK;
+    xpi_nor_config_option_t cfg_option;
+    cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
+    cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
+    cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
+
+    FAL_ENTER_CRITICAL();
+    hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
+    FAL_EXIT_CRITICAL();
+    if (status != status_success)
+    {
+        ret = -RT_ERROR;
+    }
+    else
+    {
+        /* update the flash chip information */
+        uint32_t sector_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+        uint32_t flash_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
+        nor_flash0.blk_size = sector_size;
+        nor_flash0.len = flash_size;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief FAL read function
+ *        Read data from FLASH
+ * @param offset FLASH offset
+ * @param buf Buffer to hold data read by this API
+ * @param size Size of data to be read
+ * @return actual read bytes
+ */
+FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size)
+{
+    uint32_t flash_addr = nor_flash0.addr + offset;
+    uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
+    uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
+    uint32_t aligned_size = aligned_end - aligned_start;
+    rt_base_t level = rt_hw_interrupt_disable();
+    l1c_dc_invalidate(aligned_start, aligned_size);
+    rt_hw_interrupt_enable(level);
+
+    (void) rt_memcpy(buf, (void*) flash_addr, size);
+
+    return size;
+}
+
+/**
+ * @brief Write unaligned data to the page
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size)
+{
+    hpm_stat_t status;
+
+    FAL_ENTER_CRITICAL();
+    status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
+    FAL_EXIT_CRITICAL();
+
+    if (status != status_success)
+    {
+        return -RT_ERROR;
+        rt_kprintf("write failed, status=%d\n", status);
+    }
+
+    return size;
+}
+
+/**
+ * @brief FAL write function
+ *        Write data to specified FLASH address
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size)
+{
+    uint32_t *src = NULL;
+    uint32_t buf_32[64];
+    uint32_t write_size;
+    size_t remaining_size = size;
+    int ret = (int)size;
+
+    uint32_t page_size;
+    rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
+    uint32_t offset_in_page = offset % page_size;
+    if (offset_in_page != 0)
+    {
+        uint32_t write_size_in_page = page_size - offset_in_page;
+        uint32_t write_page_size = MIN(write_size_in_page, size);
+        (void) rt_memcpy(buf_32, buf, write_page_size);
+        write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
+        if (write_size < 0)
+        {
+            ret = -RT_ERROR;
+            goto write_quit;
+        }
+
+        remaining_size -= write_page_size;
+        offset += write_page_size;
+        buf += write_page_size;
+    }
+
+    while (remaining_size > 0)
+    {
+        write_size = MIN(remaining_size, sizeof(buf_32));
+        rt_memcpy(buf_32, buf, write_size);
+        src = &buf_32[0];
+
+        FAL_ENTER_CRITICAL();
+        hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
+                offset, write_size);
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            rt_kprintf("write failed, status=%d\n", status);
+            break;
+        }
+
+        remaining_size -= write_size;
+        buf += write_size;
+        offset += write_size;
+    }
+
+write_quit:
+    return ret;
+}
+
+/**
+ * @brief FAL erase function
+ *        Erase specified FLASH region
+ * @param offset the start FLASH address to be erased
+ * @param size size of the region to be erased
+ * @ret RT_EOK Erase operation is successful
+ * @retval -RT_ERROR Erase operation failed
+ */
+FAL_RAMFUNC static int erase(long offset, size_t size)
+{
+    uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
+    hpm_stat_t status;
+    int ret = (int)size;
+
+    uint32_t block_size;
+    uint32_t sector_size;
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
+    uint32_t erase_unit;
+    while (aligned_size > 0)
+    {
+        FAL_ENTER_CRITICAL();
+        if ((offset % block_size == 0) && (aligned_size >= block_size))
+        {
+            erase_unit = block_size;
+            status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        else
+        {
+            erase_unit = sector_size;
+            status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        offset += erase_unit;
+        aligned_size -= erase_unit;
+    }
+
+    return ret;
+}
+#endif /* RT_USING_FAL */

bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld

@@ -0,0 +1,255 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > SDRAM
+    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
+
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > SDRAM_NONCACHEABLE
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > SDRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > SDRAM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > AXI_SRAM
+
+    __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE);
+}

bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld

@@ -0,0 +1,256 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > SDRAM
+    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
+
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > AXI_SRAM_NONCACHEABLE
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > SDRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > SDRAM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > AXI_SRAM
+
+    __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE);
+}

bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld

@@ -0,0 +1,214 @@
+/*
+ * Copyright 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    /* It's alias address of core0 ILM+DLM, but accessing via system bus */
+    CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K
+    /* It's alias address of core1 ILM+DLM, but accessing via system bus */
+    CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+}
+
+SECTIONS
+{
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+
+    .data : AT(etext) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        *(.tdata)
+        *(.tdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_execpt_table))
+        KEEP(*(.gcc_execpt_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+
+    .fast : AT(etext + __data_end__ - __data_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+    
+    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE);
+
+    .bss : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.tbss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.tcommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    .stack : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+    } > DLM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > SDRAM
+
+    .heap : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > SDRAM
+}

bsp/hpmicro/hpm6750evkmini/board/pinmux.c

@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+
+void init_uart_pins(UART_Type *ptr)
+{
+    if (ptr == HPM_UART0) {
+        HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
+        HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+    } else if (ptr == HPM_UART6) {
+        HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD;
+        HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD;
+    } else if (ptr == HPM_UART13) {
+        HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD;
+        HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD;
+        HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08;
+        HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09;
+    } else if (ptr == HPM_UART14) {
+        HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_UART14_RXD;
+        HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_UART14_TXD;
+        HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10;
+        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11;
+    }
+}
+
+void init_lcd_pins(LCDC_Type *ptr)
+{
+    HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0;
+    HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1;
+    HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2;
+    HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3;
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4;
+    HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5;
+    HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6;
+    HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7;
+    HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0;
+    HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1;
+    HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2;
+    HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3;
+    HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4;
+    HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5;
+    HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6;
+    HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7;
+    HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0;
+    HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1;
+    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2;
+    HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3;
+    HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4;
+    HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5;
+    HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6;
+    HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7;
+    HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK;
+    HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN;
+    HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC;
+    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC;
+
+    /* PWM */
+    HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23;
+    /* PWR */
+    HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
+}
+
+void init_cap_pins(void)
+{
+    /* CAP_INT */
+    HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
+    HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08;
+    /* CAP_RST */
+    HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
+    HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09;
+}
+
+void init_i2c_pins_as_gpio(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        /* I2C0 */
+        HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
+        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10;
+    } else {
+        while(1);
+    }
+}
+
+void init_i2c_pins(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+    } else if (ptr == HPM_I2C3) {
+        HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_I2C3_SCL
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SDA
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+    } else {
+        while(1);
+    }
+}
+
+void init_sdram_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14;
+    HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15;
+    HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12;
+    HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13;
+    HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00;
+    HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10;
+    HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11;
+    HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01;
+    HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08;
+    HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09;
+    HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04;
+    HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03;
+    HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02;
+    HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07;
+    HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06;
+    HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05;
+
+    HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11;
+    HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09;
+    HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10;
+    HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08;
+    HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07;
+    HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06;
+    HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01;
+    HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00;
+    HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05;
+    HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04;
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03;
+    HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02;
+
+    HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1;
+    HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0;
+    HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+    HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK;
+    HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE;
+    HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0;
+    HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS;
+    HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS;
+    HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE;
+    HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0;
+    HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1;
+}
+
+void init_gpio_pins(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+
+    /* Green LED*/
+    HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18;
+    HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl;
+
+#ifdef USING_GPIO0_FOR_GPIOZ
+    HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02;
+    HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl;
+    HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02;
+#endif
+}
+
+void init_spi_pins(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03;
+        HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO;
+        HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    } else if (ptr == HPM_SPI2) {
+        HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_SPI2_CSN;
+        HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO;
+        HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    } else if (ptr == HPM_SPI3) {
+        HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_SPI3_CSN;
+        HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO;
+        HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    }
+}
+
+void init_pins(void)
+{
+    init_uart_pins(BOARD_CONSOLE_BASE);
+    init_sdram_pins();
+}
+
+void init_gptmr_pins(GPTMR_Type *ptr)
+{
+    if (ptr == HPM_GPTMR4) {
+        /* TMR4 capture 1 */
+        HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1;
+    } else if (ptr == HPM_GPTMR5) {
+        /* TMR5 compare 0 */
+        HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_GPTMR5_COMP_0;
+    }
+}
+
+void init_i2s_pins(I2S_Type *ptr)
+{
+    if (ptr == HPM_I2S0) {
+        HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK;
+        HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK;
+        HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK;
+        HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_I2S0_RXD_1;
+        HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_I2S0_TXD_1;
+    }
+}
+
+void init_dao_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_DAOR_P;
+    HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_DAOR_N;
+}
+
+void init_pdm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK;
+    HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0;
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
+    HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11;
+}
+
+void init_vad_pins(void)
+{
+    HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK;
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT;
+}
+
+void init_cam_pins(CAM_Type *ptr)
+{
+    if (ptr == HPM_CAM0) {
+        HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK;
+        HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK;
+        HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC;
+        HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC;
+        HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2;
+        HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3;
+        HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4;
+        HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5;
+        HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6;
+        HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7;
+        HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8;
+        HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9;
+    }
+}
+
+void init_butn_pins(void)
+{
+    HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN;
+    HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN;
+    HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED;
+    HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED;
+}
+
+void init_acmp_pins(void)
+{
+}
+
+void init_enet_pins(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET1) {
+        /* RST */
+        HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
+
+        HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC;
+        HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO;
+        HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN;
+        HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV;
+        HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_ETH1_REFCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1;
+        HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1;
+        HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0;
+        HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0;
+    }
+}
+
+void init_pwm_pins(PWM_Type *ptr)
+{
+    if (ptr == HPM_PWM0) {
+        HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7;
+        HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_PWM0_P_6;
+        HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PWM0_P_5;
+        HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PWM0_P_4;
+    } else if (ptr == HPM_PWM1) {
+        HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1;
+        HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0;
+    } else if (ptr == HPM_PWM3) {
+        HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4;
+    }
+}
+
+void init_adc_pins(void)
+{
+    /* ADC0/1/2/.VINP7 */
+    HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* ADC0/1/2/.VINP8 */
+    HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* ADC0/1/2/.VINP9 */
+    HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* ADC0/1/2/.VINP10 */
+    HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_usb_pins(USB_Type *ptr)
+{
+    if (ptr == HPM_USB0) {
+        /* USB0 ID */
+        HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10;
+        /* USB0 OC */
+        HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08;
+    }
+}
+
+void init_can_pins(CAN_Type *ptr)
+{
+    if (ptr == HPM_CAN1) {
+        HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_CAN1_TXD;
+        HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_CAN1_RXD;
+    }
+}
+
+void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
+{
+    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17);
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) |
+                       IOC_PAD_PAD_CTL_PS_SET(1);
+
+    if (ptr == HPM_SDXC1) {
+        /* SDXC1.CLK */
+        HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl;
+
+        /* SDXC1.CMD */
+        HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl;
+
+        /* SDXC1.DATA0 */
+        HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl;
+        /* SDXC1.DATA1 */
+        HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl;
+        /* SDXC1.DATA2 */
+        HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl;
+        /* SDXC1.DATA3 */
+        HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl;
+        HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl;
+
+        /* SDXC1.CDN */
+        HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN;
+        HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl;
+
+        /* SDXC1.VSEL */
+        HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL;
+        HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl;
+    }
+}
+
+void init_clk_obs_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0;
+}
+
+void init_wifi_pins(void)
+{
+    /* WiFi INT */
+    HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_GPIO_E_01;
+    HPM_IOC->PAD[IOC_PAD_PE01].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_PS_MASK;
+    /* WiFi RST */
+    HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_GPIO_E_02;
+
+    init_spi_pins(HPM_SPI0);
+}
+
+void init_beep_pwm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4;
+}
+
+void init_led_pins_as_pwm(void)
+{
+    /* Blue */
+    HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7;
+    /* Green */
+    HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1;
+    /* Red */
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0;
+}
+
+void init_led_pins_as_gpio(void)
+{
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+
+    HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18;
+    HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19;
+    HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl;
+    HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20;
+    HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl;
+}
+
+

bsp/hpmicro/hpm6750evkmini/board/pinmux.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef HPM_PINMUX_H
+#define HPM_PINMUX_H
+#include "hpm_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void init_uart_pins(UART_Type *ptr);
+void init_lcd_pins(LCDC_Type *ptr);
+void init_i2c_pins(I2C_Type *ptr);
+void init_cap_pins(void);
+void init_sdram_pins(void);
+void init_gpio_pins(void);
+void init_spi_pins(SPI_Type *ptr);
+void init_pins(void);
+void init_gptmr_pins(GPTMR_Type *ptr);
+void init_hall_trgm_pins(void);
+void init_qei_trgm_pins(void);
+void init_i2s_pins(I2S_Type *ptr);
+void init_dao_pins(void);
+void init_pdm_pins(void);
+void init_vad_pins(void);
+void init_cam_pins(CAM_Type *ptr);
+void init_fpga_power_pins(void);
+void init_butn_pins(void);
+void init_acmp_pins(void);
+void init_enet_pins(ENET_Type *ptr);
+void init_pwm_pins(PWM_Type *ptr);
+void init_adc_pins(void);
+void init_usb_pins(USB_Type *ptr);
+void init_can_pins(CAN_Type *ptr);
+void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8);
+void init_adc_bldc_pins(void);
+
+void init_i2c_pins_as_gpio(I2C_Type *ptr);
+
+void init_beep_pwm_pins(void);
+void init_led_pins_as_pwm(void);
+void init_led_pins_as_gpio(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* HPM_PINMUX_H */

bsp/hpmicro/hpm6750evkmini/board/rtt_board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
+    gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN);
+    gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN);
+
+    gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF);
+    gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF);
+    gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state);
+        break;
+    case 1:
+        gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state);
+        break;
+    case 2:
+        gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);

bsp/hpmicro/hpm6750evkmini/board/rtt_board.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+
+/* gpio section */
+#define APP_LED0_GPIO_CTRL HPM_GPIO0
+#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED0_GPIO_PIN 19
+#define APP_LED1_GPIO_CTRL HPM_GPIO0
+#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED1_GPIO_PIN 18
+#define APP_LED2_GPIO_CTRL HPM_GPIO0
+#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB
+#define APP_LED2_GPIO_PIN 20
+#define APP_LED_ON (0)
+#define APP_LED_OFF (1)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* SPI WIFI section */
+#define RW007_RST_PIN                         (IOC_PAD_PE02)
+#define RW007_INT_BUSY_PIN                    (IOC_PAD_PE01)
+#define RW007_CS_PIN                          (IOC_PAD_PE03)
+#define RW007_CS_GPIO                         (HPM_GPIO0)
+#define RW007_SPI_BUS_NAME                    "spi1"
+
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can1"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */

bsp/hpmicro/hpm6750evkmini/board/rw007_port.c

@@ -0,0 +1,121 @@
+
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <rtthread.h>
+
+#ifdef RT_USING_WIFI
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <rtt_board.h>
+#include <spi_wifi_rw007.h>
+
+#define RW007_AT_MODE   3
+#define RW007_SPI_MODE  1
+
+extern void spi_wifi_isr(int vector);
+
+
+static void rw007_spi_cs_control(uint32_t value)
+{
+    uint32_t gpio_index = RW007_CS_PIN / 32U;
+    uint32_t pin_index = RW007_CS_PIN % 32U;
+    if (value != 0)
+    {
+        RW007_CS_GPIO->DO[gpio_index].SET = (1UL << pin_index);
+    }
+    else
+    {
+        RW007_CS_GPIO->DO[gpio_index].CLEAR = (1UL << pin_index);
+    }
+}
+
+static void rw007_spi_cs_init(void)
+{
+    HPM_IOC->PAD[RW007_CS_PIN].FUNC_CTL = 0;
+    HPM_IOC->PAD[RW007_CS_PIN].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+
+    uint32_t gpio_index = RW007_CS_PIN / 32U;
+    uint32_t pin_index = RW007_CS_PIN % 32U;
+    RW007_CS_GPIO->DO[gpio_index].SET = (1UL << pin_index);
+    RW007_CS_GPIO->OE[gpio_index].SET = (1UL <<pin_index);
+}
+
+
+static void set_rw007_mode(int mode)
+{
+    /* Configure IO */
+    rt_pin_mode(RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while(!rt_pin_read(RW007_INT_BUSY_PIN))
+    {
+    }
+    rt_thread_delay(rt_tick_from_millisecond(100));
+}
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+
+    rw007_spi_cs_init();
+
+    set_rw007_mode(RW007_SPI_MODE);
+    rt_hw_spi_device_attach(RW007_SPI_BUS_NAME, "wspi", rw007_spi_cs_control);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rt_thread_mdelay(2000);
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static int rw007_update(void)
+{
+    rt_device_t device = rt_device_find(RW007_SPI_BUS_NAME);
+    struct stm32_spi *hspi = (struct stm32_spi *)device->user_data;
+    set_rw007_mode(RW007_AT_MODE);
+    return 0;
+}
+MSH_CMD_EXPORT(rw007_update, rw007_update);
+
+static void int_wifi_irq(void * p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+rt_bool_t spi_wifi_is_busy(void)
+{
+    return !rt_pin_read(RW007_INT_BUSY_PIN);
+}
+
+void spi_wifi_int_cmd(rt_bool_t cmd)
+{
+    rt_pin_irq_enable(RW007_INT_BUSY_PIN, cmd);
+}
+
+#endif /* RT_USING_WIFI */

bsp/hpmicro/hpm6750evkmini/makefile.targets

@@ -0,0 +1,6 @@
+clean2:
+	-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+	-$(RM) $(OBJS) *.elf
+	-@echo ' '
+
+*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld)

bsp/hpmicro/hpm6750evkmini/rtconfig.h

@@ -0,0 +1,207 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_LEGACY
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Sensor libraries */
+
+
+/* Display libraries */
+
+
+/* Timing libraries */
+
+
+/* Project libraries */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_HPM6000
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_USING_RTC
+#define BSP_USING_DRAM
+#define INIT_EXT_RAM_FOR_DATA
+
+#endif

bsp/hpmicro/hpm6750evkmini/rtconfig.py

@@ -0,0 +1,94 @@
+# Copyright 2021-2022 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+
+CHIP_NAME='HPM6750'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compilercute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    DEVICE = ' -std=gnu11 -DUSE_NONVECTOR_MODE=1'
+    ARCH_ABI = '   -mcmodel=medlow '
+    CFLAGS = DEVICE + ARCH_ABI + ' -ffunction-sections -fdata-sections -fno-common'
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -static-libgcc'

bsp/hpmicro/hpm6750evkmini/rtconfig_preinc.h

@@ -0,0 +1,16 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define D45
+#define HAVE_CCONFIG_H
+#define HPM6750
+#define RT_USING_NEWLIB
+#define _POSIX_C_SOURCE 1
+#define _REENT_SMALL
+#define __RTTHREAD__
+
+#endif /*RTCONFIG_PREINC_H__*/

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript

@@ -0,0 +1,21 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the startup files
+
+src = Split('''
+   startup.c
+   trap.c
+''')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', rtconfig.CHIP_NAME]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/startup.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ *
+ */
+
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_l1c_drv.h"
+#include <rtthread.h>
+
+void system_init(void);
+
+extern int entry(void);
+
+extern void __libc_init_array(void);
+extern void __libc_fini_array(void);
+
+void system_init(void)
+{
+    disable_global_irq(CSR_MSTATUS_MIE_MASK);
+    disable_irq_from_intc();
+    enable_irq_from_intc();
+    enable_global_irq(CSR_MSTATUS_MIE_MASK);
+#ifndef CONFIG_NOT_ENABLE_ICACHE
+    l1c_ic_enable();
+#endif
+#ifndef CONFIG_NOT_ENABLE_DCACHE
+    l1c_dc_enable();
+#endif
+}
+
+__attribute__((weak)) void c_startup(void)
+{
+    uint32_t i, size;
+#ifdef FLASH_XIP
+    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+    size = __vector_ram_end__ - __vector_ram_start__;
+    for (i = 0; i < size; i++) {
+        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+    }
+#endif
+
+    extern uint8_t __etext[];
+    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __data_start__[], __data_end__[];
+    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+
+    /* bss section */
+    size = __bss_end__ - __bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__bss_start__ + i) = 0;
+    }
+
+    /* noncacheable bss section */
+    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_bss_start__ + i) = 0;
+    }
+
+    /* data section LMA: etext */
+    size = __data_end__ - __data_start__;
+    for (i = 0; i < size; i++) {
+        *(__data_start__ + i) = *(__etext + i);
+    }
+
+    /* ramfunc section LMA: etext + data length */
+    size = __ramfunc_end__ - __ramfunc_start__;
+    for (i = 0; i < size; i++) {
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+    }
+
+    /* noncacheable init section LMA: etext + data length + ramfunc length */
+    size = __noncacheable_init_end__ - __noncacheable_init_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+    }
+}
+
+__attribute__((weak)) int main(void)
+{
+    while(1);
+}
+
+void reset_handler(void)
+{
+    /**
+     * Disable preemptive interrupt
+     */
+    HPM_PLIC->FEATURE = 0;
+    /*
+     * Initialize LMA/VMA sections.
+     * Relocation for any sections that need to be copied from LMA to VMA.
+     */
+    c_startup();
+
+    /* Call platform specific hardware initialization */
+    system_init();
+
+    /* Do global constructors */
+    __libc_init_array();
+
+
+
+    /* Entry function */
+    entry();
+}
+
+
+__attribute__((weak)) void _init()
+{
+}

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+ #include <rtconfig.h>
+ #include "hpm_csr_regs.h"
+    .section .start, "ax"
+
+    .global _start
+    .type _start,@function
+
+_start:
+    /* Initialize global pointer */
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop
+
+#ifdef INIT_EXT_RAM_FOR_DATA
+    la t0, _stack_in_dlm
+    mv sp, t0
+    call _init_ext_ram
+#endif
+
+    /* Initialize stack pointer */
+    la t0, _stack
+    mv sp, t0
+
+#ifdef __nds_execit
+    /* Initialize EXEC.IT table */
+    la t0, _ITB_BASE_
+    csrw uitb, t0
+#endif
+
+#ifdef __riscv_flen
+    /* Enable FPU */
+    li t0, CSR_MSTATUS_FS_MASK
+    csrrs t0, mstatus, t0
+
+    /* Initialize FCSR */
+    fscsr zero
+#endif
+    /* Disable Vector mode */
+    csrci CSR_MMISC_CTL, 2
+
+    /* Initialize trap_entry base */
+    la t0, irq_handler_trap
+    csrw mtvec, t0
+
+
+    /* System reset handler */
+    call reset_handler
+
+    /* Infinite loop, if returned accidently */
+1:    j 1b
+
+    .weak nmi_handler
+nmi_handler:
+1:    j 1b
+
+    .global default_irq_handler
+    .weak default_irq_handler
+    .align 2
+default_irq_handler:
+1:    j 1b
+
+    .macro IRQ_HANDLER irq
+    .weak default_isr_\irq
+    .set default_isr_\irq, default_irq_handler
+    .long default_isr_\irq
+    .endm
+
+#include "vectors.S"

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021-2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .vector_table, "a"
+.global __vector_table
+.align 9
+
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, irq_handler_trap
+    .long default_isr_trap
+    IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
+    IRQ_HANDLER 8 /* ADC0 IRQ handler */
+    IRQ_HANDLER 9 /* ADC1 IRQ handler */
+    IRQ_HANDLER 10 /* ADC2 IRQ handler */
+    IRQ_HANDLER 11 /* DAC IRQ handler */
+    IRQ_HANDLER 12 /* ACMP[0] IRQ handler */
+    IRQ_HANDLER 13 /* ACMP[1] IRQ handler */
+    IRQ_HANDLER 14 /* SPI0 IRQ handler */
+    IRQ_HANDLER 15 /* SPI1 IRQ handler */
+    IRQ_HANDLER 16 /* SPI2 IRQ handler */
+    IRQ_HANDLER 17 /* SPI3 IRQ handler */
+    IRQ_HANDLER 18 /* UART0 IRQ handler */
+    IRQ_HANDLER 19 /* UART1 IRQ handler */
+    IRQ_HANDLER 20 /* UART2 IRQ handler */
+    IRQ_HANDLER 21 /* UART3 IRQ handler */
+    IRQ_HANDLER 22 /* UART4 IRQ handler */
+    IRQ_HANDLER 23 /* UART5 IRQ handler */
+    IRQ_HANDLER 24 /* UART6 IRQ handler */
+    IRQ_HANDLER 25 /* UART7 IRQ handler */
+    IRQ_HANDLER 26 /* CAN0 IRQ handler */
+    IRQ_HANDLER 27 /* CAN1 IRQ handler */
+    IRQ_HANDLER 28 /* PTPC IRQ handler */
+    IRQ_HANDLER 29 /* WDG0 IRQ handler */
+    IRQ_HANDLER 30 /* WDG1 IRQ handler */
+    IRQ_HANDLER 31 /* TSNS IRQ handler */
+    IRQ_HANDLER 32 /* MBX0A IRQ handler */
+    IRQ_HANDLER 33 /* MBX0B IRQ handler */
+    IRQ_HANDLER 34 /* GPTMR0 IRQ handler */
+    IRQ_HANDLER 35 /* GPTMR1 IRQ handler */
+    IRQ_HANDLER 36 /* GPTMR2 IRQ handler */
+    IRQ_HANDLER 37 /* GPTMR3 IRQ handler */
+    IRQ_HANDLER 38 /* I2C0 IRQ handler */
+    IRQ_HANDLER 39 /* I2C1 IRQ handler */
+    IRQ_HANDLER 40 /* I2C2 IRQ handler */
+    IRQ_HANDLER 41 /* I2C3 IRQ handler */
+    IRQ_HANDLER 42 /* PWM0 IRQ handler */
+    IRQ_HANDLER 43 /* HALL0 IRQ handler */
+    IRQ_HANDLER 44 /* QEI0 IRQ handler */
+    IRQ_HANDLER 45 /* PWM1 IRQ handler */
+    IRQ_HANDLER 46 /* HALL1 IRQ handler */
+    IRQ_HANDLER 47 /* QEI1 IRQ handler */
+    IRQ_HANDLER 48 /* SDP IRQ handler */
+    IRQ_HANDLER 49 /* XPI0 IRQ handler */
+    IRQ_HANDLER 50 /* XPI1 IRQ handler */
+    IRQ_HANDLER 51 /* XDMA IRQ handler */
+    IRQ_HANDLER 52 /* HDMA IRQ handler */
+    IRQ_HANDLER 53 /* DRAM IRQ handler */
+    IRQ_HANDLER 54 /* RNG IRQ handler */
+    IRQ_HANDLER 55 /* I2S0 IRQ handler */
+    IRQ_HANDLER 56 /* I2S1 IRQ handler */
+    IRQ_HANDLER 57 /* DAO IRQ handler */
+    IRQ_HANDLER 58 /* PDM IRQ handler */
+    IRQ_HANDLER 59 /* FFA IRQ handler */
+    IRQ_HANDLER 60 /* NTMR0 IRQ handler */
+    IRQ_HANDLER 61 /* USB0 IRQ handler */
+    IRQ_HANDLER 62 /* ENET0 IRQ handler */
+    IRQ_HANDLER 63 /* SDXC0 IRQ handler */
+    IRQ_HANDLER 64 /* PSEC IRQ handler */
+    IRQ_HANDLER 65 /* PGPIO IRQ handler */
+    IRQ_HANDLER 66 /* PWDG IRQ handler */
+    IRQ_HANDLER 67 /* PTMR IRQ handler */
+    IRQ_HANDLER 68 /* PUART IRQ handler */
+    IRQ_HANDLER 69 /* FUSE IRQ handler */
+    IRQ_HANDLER 70 /* SECMON IRQ handler */
+    IRQ_HANDLER 71 /* RTC IRQ handler */
+    IRQ_HANDLER 72 /* BUTN IRQ handler */
+    IRQ_HANDLER 73 /* BGPIO IRQ handler */
+    IRQ_HANDLER 74 /* BVIO IRQ handler */
+    IRQ_HANDLER 75 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 76 /* SYSCTL IRQ handler */
+    IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */
+    IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <rtthread.h>
+#include "riscv-stackframe.h"
+
+#define MCAUSE_INSTR_ADDR_MISALIGNED (0U)       //!< Instruction Address misaligned
+#define MCAUSE_INSTR_ACCESS_FAULT (1U)          //!< Instruction access fault
+#define MCAUSE_ILLEGAL_INSTR (2U)               //!< Illegal instruction
+#define MCAUSE_BREAKPOINT (3U)                  //!< Breakpoint
+#define MCAUSE_LOAD_ADDR_MISALIGNED (4U)        //!< Load address misaligned
+#define MCAUSE_LOAD_ACCESS_FAULT (5U)           //!< Load access fault
+#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U)   //!< Store/AMO address misaligned
+#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U)      //!< Store/AMO access fault
+#define MCAUSE_ECALL_FROM_USER_MODE (8U)        //!< Environment call from User mode
+#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U)  //!< Environment call from Supervisor mode
+#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U)    //!< Environment call from machine mode
+#define MCAUSE_INSTR_PAGE_FAULT (12U)           //!< Instruction page fault
+#define MCAUSE_LOAD_PAGE_FAULT (13)             //!< Load page fault
+#define MCAUSE_STORE_AMO_PAGE_FAULT (15U)       //!< Store/AMO page fault
+
+#define IRQ_S_SOFT              1
+#define IRQ_H_SOFT              2
+#define IRQ_M_SOFT              3
+#define IRQ_S_TIMER             5
+#define IRQ_H_TIMER             6
+#define IRQ_M_TIMER             7
+#define IRQ_S_EXT               9
+#define IRQ_H_EXT               10
+#define IRQ_M_EXT               11
+#define IRQ_COP                 12
+#define IRQ_HOST                13
+
+typedef void (*isr_func_t)(void);
+
+static volatile rt_hw_stack_frame_t *s_stack_frame;
+
+static void rt_show_stack_frame(void);
+
+__attribute((weak)) void mchtmr_isr(void)
+{
+}
+
+__attribute__((weak)) void mswi_isr(void)
+{
+}
+
+__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
+{
+}
+
+uint32_t exception_handler(uint32_t cause, uint32_t epc)
+{
+    /* Unhandled Trap */
+    uint32_t mdcause = read_csr(CSR_MDCAUSE);
+    uint32_t mtval = read_csr(CSR_MTVAL);
+    switch (cause)
+    {
+    case MCAUSE_INSTR_ADDR_MISALIGNED:
+        rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_INSTR_ACCESS_FAULT:
+        rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_ILLEGAL_INSTR:
+        rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        switch (mdcause & 0x07)
+        {
+        case 0:
+            rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            break;
+        case 1:
+            rt_kprintf("mdcause: FP disabled exception \r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: ACE disabled exception \r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_BREAKPOINT:
+        rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ADDR_MISALIGNED:
+        rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ACCESS_FAULT:
+        rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
+        rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc);
+        break;
+    case MCAUSE_STORE_AMO_ACCESS_FAULT:
+        rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            rt_kprintf("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            rt_kprintf("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        case 7:
+            rt_kprintf("mdcause: PMA NAMO exception \r\n");
+        default:
+            rt_kprintf("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    default:
+        rt_kprintf("Unknown exception happened, cause=%d\n", cause);
+        break;
+    }
+
+    rt_show_stack_frame();
+    while (1)
+    {
+    }
+}
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame);
+
+void trap_entry(rt_hw_stack_frame_t *stack_frame)
+{
+    uint32_t mcause = read_csr(CSR_MCAUSE);
+    uint32_t mepc = read_csr(CSR_MEPC);
+    uint32_t mstatus = read_csr(CSR_MSTATUS);
+
+    s_stack_frame = stack_frame;
+
+#if SUPPORT_PFT_ARCH
+    uint32_t mxstatus = read_csr(CSR_MXSTATUS);
+#endif
+#ifdef __riscv_dsp
+    int ucode = read_csr(CSR_UCODE);
+#endif
+#ifdef __riscv_flen
+    int fcsr = read_fcsr();
+#endif
+
+    /* clobbers list for ecall */
+#ifdef __riscv_32e
+    __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
+#else
+    __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
+#endif
+
+    /* Do your trap handling */
+    uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
+    uint32_t irq_index;
+    if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
+    {
+        switch (cause_type)
+        {
+        /* Machine timer interrupt */
+        case IRQ_M_TIMER:
+            mchtmr_isr();
+            break;
+            /* Machine EXT interrupt */
+        case IRQ_M_EXT:
+            /* Claim interrupt */
+            irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
+            /* Execute EXT interrupt handler */
+            if (irq_index > 0)
+            {
+                ((isr_func_t) __vector_table[irq_index])();
+                /* Complete interrupt */
+                __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
+            }
+            break;
+            /* Machine SWI interrupt */
+        case IRQ_M_SOFT:
+            mswi_isr();
+            intc_m_complete_swi();
+            break;
+        }
+    }
+    else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
+    {
+        /* Machine Syscal call */
+        __asm volatile(
+                "mv a4, a3\n"
+                "mv a3, a2\n"
+                "mv a2, a1\n"
+                "mv a1, a0\n"
+#ifdef __riscv_32e
+                "mv a0, t0\n"
+#else
+                "mv a0, a7\n"
+#endif
+                "call syscall_handler\n"
+                : : : "a4"
+        );
+        mepc += 4;
+    }
+    else
+    {
+        mepc = exception_handler(mcause, mepc);
+    }
+
+    /* Restore CSR */
+    write_csr(CSR_MSTATUS, mstatus);
+    write_csr(CSR_MEPC, mepc);
+#if SUPPORT_PFT_ARCH
+    write_csr(CSR_MXSTATUS, mxstatus);
+#endif
+#ifdef __riscv_dsp
+    write_csr(CSR_UCODE, ucode);
+#endif
+#ifdef __riscv_flen
+    write_fcsr(fcsr);
+#endif
+}
+
+static void rt_show_stack_frame(void)
+{
+    rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
+    rt_kprintf("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS));
+    rt_kprintf("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    rt_kprintf("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    rt_kprintf("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    rt_kprintf("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    rt_kprintf("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    rt_kprintf("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+    rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+}

bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript

@@ -0,0 +1,21 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the startup files
+
+src = Split('''
+   startup.c
+   trap.c
+''')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', rtconfig.CHIP_NAME]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')